JPH06181579A - Picture processor - Google Patents

Abstract

PURPOSE:To enrich the picture processing function of a computer system by providing a register for setting an upper limit value and a lower limit value as key colors and replacing the key color with picture output whose display priority order is low to be synthesized and outputted. CONSTITUTION:For a priority processing at a video encoder, the priority order of respective LSIs for each dot is decided by whether or not picture information sent from the respective devices of a VDP, a controller unit and a picture data expansion unit and a priority register value and data are chroma key data. In data chroma key processings from the respective units, on a color palette data screen, even in what color mode on the run length screens of the VDP, controller and picture data expansion units, color palette data 0 become transparent. For the VDP, a palette number 0 becomes transparent at a color palette bank. Also, on a controller YUV data screen, when the internal Y data of YUV data are 00h, the dot becomes transparent regardless of the value of UV.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chroma key function in an image processing apparatus.

[0002]

2. Description of the Related Art An image processing function performed by a conventional computer will be described below. When image processing and output are performed by a computer device, the background screen is configured in units of a pattern called a character whose unit is the raster of the CRT screen and character pitch. An example is given of a computer game device that employs an expression system in which the screen is superimposed on the background and sprites.

The image processing function of the computer game device mainly includes an external storage device, a CPU, a VRAM, a video display controller (VDC), a video encoder (VDE), and a CRT. Image data is transferred from the external storage device to the VRAM under the control of the CPU,
Image data is obtained from the VRAM, processed, and output.

The background is defined for each character by display position, color, and pattern information, and is managed in a data format of a background attribute table (BAT) and a character generator (CG) in VRAM.

A sprite is defined by information such as a display position, color, and pattern for each sprite, and is managed in a data format of a sprite attribute table buffer (SATB) and a sprite generator (SG).

BAT consists of CG color and character code, and CG defines a character pattern on four sides (16-color mode). The character code is a code for generating a CG address. This code shows which CG the BAT refers to. SATB is mainly composed of a sprite color and a pattern code, and SG defines a pattern of each sprite. With this code SATB
Can see which SG refers to.

The output of the background image data is
An address is generated from the raster position, BAT is read, and a character code and a CG color code are obtained. An CG address is generated from the obtained character code, pattern data is obtained, and the pattern data is output together with the CG color code.

When outputting sprite image data, SA
Reading is sequentially performed from the beginning of the TB address. After obtaining the sprite pattern code and the SG color code, the SG address is generated from the sprite pattern code, the pattern data is obtained, and the SG color code is output together with the SG color code. Sequentially, the coordinate data designating the CRT display position of SATB and all the data in the SAT area are rewritten to change the screen display.

The superposition of the background and the sprite is performed using a priority circuit. When the sprite data and the background data are sent to the priority circuit, only the data to be displayed is output at the overlapping coordinate positions according to the instruction written in the priority register.

Display data consisting of CG pattern data and CG color code or SG pattern data and SG color code output from VDP is input to VDE, converted by a color palette, converted into D / A, and then converted into actual RGB.
Output as a signal. RGB digital data is written in the color palette by the CPU.

FIG. 1 shows an example of the structure of a color palette. There is a 256-address x 9-bit color palette, which is divided into 16 addresses x 9-bit block 16 areas. The 9-bit color data is RGB 3-bit color data, and one address is color information for one dot. Each block holds 16 of the 256 colors.

A block is designated by a color code, and 25
Decide which of 16 colors to use. The address in the block designated by the color code is designated by the pattern data to determine which one of the 16 colors is to be used.

[0013]

As described above, the prior art is as follows.
A priority circuit superimposes multiple screens created by the video display controller in order of priority and controls the output. Further, the color data uses a color palette data format and has a means for changing the palette to be used by a color code to realize many colors.

The superposition of the background and the sprite is such that the background occupies most of the screen. In the conventional background and sprite display format, chroma key is not effective, and it is sufficient to select and display images and sprites that constitute the background by designating priorities.

In fact, the conventional image processing apparatus cannot perform chroma key processing. In the color palette described in the conventional example, one color is defined by 9 bits, 256 colors out of 2 ⁹ = 512 colors are arranged at the address of 256, color data is taken out from the color palette, and the priority circuit is prioritized. It is output as it is. Among the 512 colors that can be output, there is no transparent color setting that allows transparent display of lower priority images. Both the color data definition by the color palette and the data format in which the color code is used as it is are colored data, and an expression of a transparent color cannot be obtained.

However, in order to promote the computerization of multimedia, there is a trend to increase the kinds of image data to be handled and to enhance the image processing functions such as complicated screen synthesizing technology. There is an urgent need to express various images by using transparent colors and overlapping multiple screens that incorporate transparent colors.

It is an object of the present invention to enhance the image processing function of a computer device by providing a transparent color setting means for image output.

[0018]

In order to solve the above-mentioned problems, in the present invention, in the color data in the color palette data format, the portion of the color data which can be designated by the color palette is 0 is judged to be transparent. In the color data in the form of the YUV signal, Y = 00h of the color signal is set as a key color judged to be transparent, and a transparent color is obtained in the same manner.

At the time of priority processing, data is judged in dot units, and an invalid signal is output to the portion using the key color, so that there is no color signal. The transparent color becomes effective by determining and outputting the priority order with respect to other screens and special effects. A value in a certain range may be set for the key color depending on the nature of the data. Eg ID
On the CT plane, the color within the range set by the chroma key register is used as the key color.

An example of the chroma key processing of the present invention will be described below. In the case of an image in the data format of YUV code that is expanded by IDCT, the upper limit Y value of the chroma key Y is Yu, the lower limit Y value is Yl, the upper limit U value of the chroma key U is Uu, and the lower limit U.
If the value is set to Ul, the upper limit V value of the chroma key V is set to Vu, the lower limit V value is set to Vl, and the Y value of the color to be displayed is Ys, the U value is Us, and the V value is Vs, the following formula becomes true. When
The color to be displayed is the key color and is transparent.

(Yu> = Ys> = Yl) and (Uu>
= Us> = Ul) and (Vu> = Vs> = Vl)

In the case of an image of a data format based on a normal YUV code, a transparent color is obtained by designating one of the YUV codes as a key color. For example, Y = 0 of the screen
When it is desired to make the black color output at 0, U = 80, V = 80 the key color and to make it transparent, set chroma key Y = 0080, chroma key U = 8080, chroma key V = 8080. Only the Y code or the U code may be designated.

In the case of an image in the color palette data format, the palette data or a part of the palette data is set as a key color in the register to be a transparent color. For example,
When the color palette data = 0, the key color is used, or one of the palette numbers is used as the key. According to the value set in the register, the priority circuit determines that the color is transparent.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus of the present invention will be described based on embodiments. FIG. 2 is a block diagram of the apparatus of the embodiment.

A game software recording medium such as a CD-ROM,
32-bit CPU, controller unit mainly for image / sound data transfer control and interface of each device,
The image data expansion / conversion unit, the image data output unit, the audio data output unit, the video encoder unit, the VDP unit, and the like. K-RAM, M-RAM, R-RAM, V-RA dedicated to each unit
It has a memory such as M.

The CPU directly drives the DR through the memory support.
It has a memory control function that can control AM and an I / O control function that can communicate with various peripheral devices through an I / O port. It also has a timer, parallel input / output port, and interrupt control mechanism.

The display data written in the VRAM by the CPU is read by the VDP unit and is displayed on the screen by sending the data to the video encoder unit.

The controller unit has a built-in SCSI controller, and an external storage device such as a CD-ROM drives
Capture data such as images and sounds via the CSI interface. The captured data is once K-RA
Buffered in M.

The controller unit has a built-in DRAM controller, and the function allows the data stored in the K-RAM to be read at a predetermined timing.

The background image data of the natural image is sent to the video encoder unit after being subjected to priority determination in the unit of dot data in the controller unit.

The data-compressed moving image (full color, palette) data is sent to the image data expansion unit. The image data decompression unit decompresses the data and sends it to the video encoder unit.

In the video encoder unit, the VDP image sent from the VDP unit, the controller unit, and the image data expansion unit, the background image of the natural image, the superimposing process of the moving image (full color, palette) data, the color palette reproduction, and the special effect. The image signal, which has been subjected to processing, D / A conversion, and the like, is output, and finally an image signal encoded into an NTSC signal is output by an external circuit.

ADP read from a CD-ROM or the like
The CM audio data is buffered in the KRAM like the image data, and then sent to the audio data output unit by the controller unit and reproduced.

A block diagram of the video encoder unit is shown in FIG. The video encoder unit has a sync signal generation circuit, a color palette RAM, a priority calculation circuit, a cellophane calculation circuit, and a video signal D / C on the IC chip.
It is made by integrating an A converter, an 8 / 16-bit data bus (M-bus) interface, a VDP interface, a controller unit interface, and an image data expansion unit interface.

The 8 / 16-bit data bus (M-bus) interface is an I / F for determining whether the operation on the video encoder unit side is 8 bits or 16 bits in accordance with the data width of the data bus of the processing system including the CPU.
It is a switching circuit.

The VDP interface is an interface for data sent from two VDPs, and normally receives data from the upper VDP, and receives data from the lower VDP only when the upper VDP outputs chroma key data.

The color palette RAM converts a video data input signal into a YUV digital signal.

The video encoder unit has registers (16 bits × 24 lines) inside. By accessing these from the CPU, functions such as operation mode setting and color palette read / write are fulfilled.

The color palette RAM will be described.
The color palette data is converted into YUV data by the color palette RAM and becomes data that can be actually displayed. The color palette RAM is a color information table composed of 512 addresses in the address direction and 16 bits in the data direction.

As shown in FIG. 4, a color palette RAM
Is composed of a RAM having 512 addresses in the address direction and 16 bits in the data direction. One address has data of one color and can have data of 512 colors in total.

Data of one color (one address) is composed of Y8 bits, U4 bits and V4 bits as shown below, and can represent 65536 colors. The Y data indicates brightness, has a value of 00 (black) to FFh (white), and the U data is blue-yellow color difference information, has a value of 0 to 15, and is 8 in the case of colorless. V data is red-green color difference information, 0 to
It has a value of 15 and is 8 when it is colorless.

After resetting, YY = 00h, U = 0h, V = 0h are set in the color palette address 0. Therefore, it is necessary to set the color data to the color palette address 0 again after the reset.

A method of setting YUV data in the color palette RAM will be described. The contents of the color palette RAM are written by the CPU, read by the color palette information from the VDP, the controller unit, and the image data expansion unit, and converted into Y, U, and V data. The CPU can also read the contents of the color palette RAM if necessary.

Writing to the color palette RAM (when writing data continuously) is performed as follows.

1step: The register number 01h of the color palette address register (CPA) is set in the address register (AR) 2step: Color palette address register (CP)
Write the start address in A) 3step: Register number 02 of color palette data write register (CPW) in address register (AR)
Set h. 4step: Write data to the color palette data write register. (CPA is incremented.) 5step: Write data to the color palette data write register. (CPA is incremented.)

When the 8-bit bus is selected, writing to the data write register is performed in the order of the lower byte and the upper byte. When the upper byte is written, the actual writing to the internal register is performed and CPA is incremented. .

The reading of the contents of the color palette RAM (when the data is continuously read) is performed as follows.

1step: The register number 01h of the color palette address register (CPA) is set in the address register (AR) 2step: Color palette address register (CP)
Write the start address in A) 3step: Register number 03 of color palette data read register (CPR) in address register (AR)
Set h. 4step: Read the data of the color palette data read register. (CPA is incremented.) 5step: Read the data of the color palette data read register. (CPA is incremented.)

When the 8-bit bus is selected, the reading from the data read register is performed in the order of the lower byte and the upper byte. When the upper byte is read, the actual writing to the internal register is performed and the CPA is incremented. .

The display of the color palette data will be described. The color palette data surface of the VDP, the controller unit, and the image data decompressing unit stores the color palette data in Y, U, and
Convert to V data and display the actual image.

Since there is only one set of color palette RAM, all surfaces using color palette data use the same color palette RAM. However, by utilizing the color palette address offset register, the color palette address to be used can be set for each surface.

In the display processing, the priority processing block first determines the surface to be displayed in 1 dot units. If the surface is the color palette data surface, the color palette address offset value of the surface is read from the register, and twice the value and the color palette data are added to calculate the color palette address.

The data designated by the calculated color palette address becomes the color of the dot, and the Y, U and V data are sent to the next functional block.

The color palette address is determined by calculating the color palette data and the color palette offset value set for each surface. Therefore, even if the color palette data is the same, different colors can be output if the surfaces are different. The calculation formula is shown below.

Color palette address (9 bits) = color palette data (8 bits) + (color palette address offset value × 2) (8 bits)

There is only one set of color palette offset register for VDP. The upper VDP and the lower VDP use the same register. If the color palette address exceeds 511, the 10th bit is simply truncated and follows the 0 address. This is shown in FIG. The color palette address offset is not relevant when the CPU accesses the color palette RAM.

From each LSI, the detailed color palette data as shown in FIG. 6 is sent. When calculating the color palette address, the palette bank number is simply treated as the upper bits of the palette number, and the palette bank number and palette number are not distinguished. Therefore, all the 8-bit data in each of the modes named above are treated as color palette data.

The priority function is to process the image dot information at that time sent from each of the VDP, the controller unit and the image data decompression unit at the same time according to the priority order of the screen specified in the priority register. This is a function of determining the image dots to be displayed.

The screen configuration of the image processing apparatus according to the embodiment of the present invention is such that VDP has two surfaces, a sprite (SP) surface and a background (BG) surface, and the controller unit has BM.
G0 surface, BMG1 surface, BMG2 surface, BMG3 surface, 4 surfaces,
The image data expansion unit has one of the IDCT / RL surfaces.

The video encoder in the apparatus of the embodiment can connect two VDPs. Two VDPs are selected in the input interface portion. Normally, the upper VDP is selected, and the lower VDP is selected only when the upper VDP outputs chroma key data.

Since the priority register of the VDP SP / BG and the controller units BMG0 to BMG3 cannot be changed only by the priority register of the video encoder in this example, it is necessary to change the setting of each unit as well.

The priority processing in the video encoder is such that the priority order of each LSI is determined for each dot depending on the surface information and priority register value sent from each device of the VDP, the controller unit, and the image data expansion unit, and whether the data is chroma key data. Decide.

FIG. 7 is an explanatory diagram of the priority process in the 256 dot mode. Dot clock 4 here
Processing is performed with double the clock, and priority processing is performed along with special processing such as chroma key processing and cellophane processing.

In the 320-dot mode, the controller unit and the image data expansion unit have 256 dots, VD
Since P is 320 dots, the surface to be displayed is determined in a cycle of 21 Mhz, the surface (device) is selected, and it is immediately displayed.

The chroma key function (transparency processing) will be described. The chroma key function (transparency processing) is a function of treating a part of a certain surface as transparent and displaying a low priority surface on the transparent portion.

Specifically, the color (key color) determined to be transparent is determined, and the portion using that color becomes transparent. The key color is color palette data for the surface or IDCT
-Handling differs depending on whether it is YUV data or YUV data of the controller unit.

When the chroma key is not used, the key color is not used when creating a picture. FIG. 8 shows an explanatory diagram of the chroma key.

FIG. 9 is an explanatory view of the data chroma key processing from each unit. On the color palette data side, V
On the run surface of the DP, controller unit, and image data decompression unit, the color palette data 0 is transparent in any color mode. In VDP, palette number 0 becomes transparent in all color palette banks.

On the color palette data side of the controller unit, the controller unit may perform chroma key determination and may send an invalid signal.

On the controller unit-YUV data surface (16M color, 64K color mode), if Y data of YUV data is 00h, regardless of the UV value,
The dot becomes transparent. Y at the part you don't want to be transparent
It is necessary to add 01h to the data so that the data will not be 00h.

In the IDCT-YUV data, the color of the range set in the chroma key register becomes transparent.

Set the upper limit Y value of the chroma key Y register to Yu.
Lower limit Y value is Yl Upper limit U value of chroma key U register is Uu Lower limit U value is U
l Upper limit V value of chroma key V register is Vu Lower limit V value is V
l Y value of the color to be displayed is Ys, U value is Us, V value is Vs

Then, when the following expression becomes true, the color to be displayed is the key color and becomes transparent.

(Yu> = Ys> = Yl) and (Uu>
= Us> = Ul) and (Vu> = Vs> = Vl)

The processing of the invalid signal from the controller unit and the image data expansion unit will be described. When an invalid signal is input from the controller unit and the image data expansion unit, the video encoder of the present invention uses the LS for that dot.
It is treated as transparent as if the chroma key color was input from I.

Next, the synchronizing signal generating function of the video encoder of the present invention will be described. The video encoder of the present invention has a built-in synchronizing signal generation circuit, and by inputting a color subcarrier frequency of 12 times, dot clocks to peripheral ICs, -HSYNCA, HSY of horizontal synchronizing signals.
NCB, HSYNC, and vertical sync signal -VSY
Output NC. Also, because it has an external synchronization function,
It is possible to synchronize with external video.

The YUV signal of the video encoder of the present invention is converted into an analog signal by each built-in D / A converter. The D / A converter is 8 bits for both YUV. However, if UV has only 4-bit data, such as palette data, the lower 4 bits of each will be 0000.
To add 8 bits.

Y is linearly converted to an analog signal with 00h being black and FFh being white. The data of U and V are also linearly converted into analog signals as they are, but since they are color difference signals, they have polarities.

Since the color depth is proportional to the difference from 80h, 00h and FFh are the darkest, and U and V are colorless when 80h. Hue is 80h for U and V
It is determined by the ratio of the difference from and each polarity.

Upon D / A conversion, the Y signal can be selected with / without a sync signal, and the U and V signals can be selected with / without modulation by a color subcarrier. When the color subcarrier is modulated, the color burst is superimposed on the U signal at the specified timing and amplitude. The D / A converter is a current addition type,
It is converted into a voltage by the input impedance of the external circuit.

An RGB signal can be created by performing an analog operation on the Y signal without synchronization and the UV signal without modulation by an external circuit. In addition, a Y signal with synchronization and U with modulation
A composite video signal for CRT can be produced by mixing the V signal in an external circuit.

A method of accessing the internal register of the video encoder of the present invention will be described. Registers are addressed indirectly using address registers.

(Step 1) -CET (chip enable) and A1 terminal are both set to "L". Since the address register (AR) is selected, the register number to be accessed is written. (Step 2) -Set CET (chip enable) to "L"
And A1 terminal to "H".

Since the register indicated by the address register is selected, necessary read / write is performed. Since the address register does not change unless it is rewritten, step 1 can be omitted when accessing the same register.

When the address register is read, it becomes a status register, and in addition to the value of the address register, the raster count value, interlace information, etc. are read at the same time.

Selection of data bus width of 16 bits or 8 bits The selection of the data bus width is performed by the EX8 / -16 terminal.
Access to the register in each case is the data width 8
When it is a bit, the low byte and high byte of the register are accessed by "0/1" of A0. Data width 16
When it is a bit, 16 bits can be directly read and written, so A0 is ignored.

Functions of Internal Registers (1) Address Register (AR) As shown in FIG. 10, the address register (AR) specifies registers R00 to R15 inside the video encoder. When A1 is at "L" level, AR is selected by writing to the video encoder. When writing or reading to R00 to R15, first, the number of the register designated in AR is written.

(2) Status register (SR) When A1 is at "L" level, the status register is selected when the video encoder is read. In addition to the value of the address register, the raster number being displayed and information on the display surface of the interlace can be obtained. The status register is shown in FIG.

A. AR (bits 0 to 4) Current address register value.

B. RASTERCOUNT (bit5
~ 13) Indicates the raster number currently displayed on the CRT. Display period is 2
It is from 2 to 261. It should be noted that the scanning line number defined by the NTSC signal does not match. Further, during external synchronization, when the external synchronization signal is disturbed, it becomes 1FFh.

C. O / E (bit 14) Indicates whether the screen currently displayed on the CRT in the interlaced mode is an odd field or an even field. 0: Even,
1: Odd.

D. DISP (bit 15) Indicates whether the video encoder is currently in the display period or in the non-display period (H blank, V blank). 0:
Not displayed, 1: Displayed.

(3) Control register (CR: R0
0) Bits 8 to 14 are valid from the next horizontal period, and the others are valid from the next vertical period. The control register is a register that sets the display mode of the video encoder. FIG. 12 shows the control register.

A. DCC (bit 0, 1) This is a register for setting mode switching between interlaced and non-interlaced.

B. EX Set to 1 to perform external synchronization. Free-runs until the external sync signal is detected, and locks when the sync signal with the correct cycle is detected. When 0 is set, external synchronization is released, but if the external synchronization signal is severely disturbed, it may not be released during that time. 0 after reset
Is set.

C. It is a bit for displaying DC7 VDP in horizontal 320 dots. 1
When set to, horizontal 320 dots display is obtained. In this mode, the dot clock only for VDP becomes 7 MHz.

D. Blanking (bits 8 to 14) This is a bit for setting whether or not to display each screen on the screen. It will be effective from the next horizontal period.

R00 bit8 0: BG is erased 1: BG is displayed R00 bit9 0: SP is erased 1: SP is displayed R00 bit10 0: BMG0 is erased 1: BMG0 is displayed R00 bit11 0: BMG1 is erased 1: BMG1 is displayed Display R00 bit12 0: BMG2 is erased 1: BMG2 is displayed R00 bit13 0: BMG3 is erased 1: BMG3 is displayed R00 bit14 0: IDCT / RL image is erased 1: IDCT / RL image is displayed

In the case of all blanking (reset state in which all bits 8 to 14 are set to 0), black (Y = 00h, U = 80h, V = 80h) is output to the YUV output.

(4) Color palette address register (CPA: R01) The color palette address register is a register for setting a color palette address when the CPU accesses the color palette RAM. FIG. 13 shows the structure of the register.

The color palette data write register and the color palette data read register address the color palette with the color palette address register and read / write data.

Once data is set in the color palette address register, it is automatically incremented each time each register of color palette data write and color palette data read is accessed.

(5) Color palette data write register (CPW: R02) The color palette data write register shown in FIG.
It is a data write register when the CPU writes data in the color palette RAM.

The data is written to the color palette address indicated by CPA. The data is set in a positive integer format with YUV. Regarding UV, since the D / A converter has 8 bits, it is internally handled with 8 bits with the lower 4 bits set to 0000.

Since the color palette address register has the automatic increment function, data can be continuously written.

When the data bus is 8 bits, since the actual writing to the register is performed at the time when the upper byte is written, the writing must be performed in the order of the lower byte and the upper byte. The CPA is also incremented after writing the upper byte.

(6) Color palette data read register (CPR: R03) The CPU reads the color palette data read register from the color palette address register indicated by the color palette address register. Since the color palette address register has an automatic increment function, data can be read continuously.

When the data bus is 8 bits, the upper byte is read and then incremented. Therefore, it is necessary to read the lower byte and the upper byte in this order.

(7) Color palette address offset register Color palette address offset register 1 is VD
Each side of P is a register that indicates from which color palette address to use the color palette. FIG. 15 shows a register.

In practice, the set value is doubled to obtain the color palette address offset value. Each set address offset value becomes valid from the next horizontal display period.

SP color palette address = SP color palette data + (SP color palette offset ×
2)

BG color palette address = BG color palette data + (BG color palette offset ×
2)

The color palette address offset register 2 shown in FIG. 16 is a register for instructing which color palette to use from the side of the color palette data from the controller unit. Here, BMG
0 and BMG1 are set.

In practice, the set value is doubled to obtain the offset value of the color palette address. Each set address offset value becomes valid from the next horizontal display period.

BMG0 color palette address = BMG
0 color palette data + (BMG0 color palette address offset x 2)

BMG1 color palette address = BMG
1 color palette data + (BMG1 color palette address offset x 2)

The color palette address offset register 3 of FIG. 17 is a register for instructing from which number the color palette to be used for the surface of the color palette data from the controller unit.

Here, BMG2 and BMG3 are set. Actually, the set value is doubled to obtain the offset value of the color palette address. Each set address offset value becomes valid from the next horizontal display period.

BMG2 color palette address = BMG
2 color palette data + (BMG2 color palette address offset x 2)

BMG3 color palette address = BMG
3 color palette data + (BMG3 color palette address offset x 2)

The color palette address offset register 4 shown in FIG. 18 is a register for instructing from which number the color palette used by the run-lens plane from the image data expansion unit. Actually, the set value is doubled to obtain the offset value of the color palette address.

Each set address offset value becomes valid from the next horizontal display period. Color palette address of image data expansion unit = image data expansion unit color palette data + (image data expansion unit color palette address offset × 2).

(8) Priority register Priority registers 1 and 2 shown in FIGS.
Is a register that specifies the priority of the screen and is 3 bits (0
(Numbers from 1 to 7), the higher the numerical value, the higher the priority. However, do not set the same value in multiple registers.

(9) Chroma key register (used on IDCT surface) The chroma key Y (luminance) register shown in FIG.
It is a register showing the upper limit and the lower limit of the Y component in the chroma key processing of the T surface.

The data format is a positive integer and black = 00.
H, white = FFH. The set data becomes valid from the next horizontal display period.

The chroma key U (color difference) register of FIG. 22 is used to determine the upper limit of the U component during chroma key processing on the IDCT surface.
This is a register indicating the lower limit. The data format is a positive integer. The set data becomes valid from the next horizontal display period.

The chroma key V (color difference) register shown in FIG. 23 is used to determine the upper limit of the V component during chroma key processing on the IDCT surface.
This is a register indicating the lower limit. The set data becomes valid from the next horizontal display period.

[0128]

As described above, according to the image processing apparatus of the present invention, the chroma key processing can be performed by providing the register for setting the transparent color and making the dot determination by the priority circuit. Since the chroma key processing is controlled in dot units, a screen with good image quality is obtained. In the present invention, the chroma key processing is incorporated and used in combination with the compositing of a plurality of screens, thereby making it possible to display a complicated screen and realize a multimedia computer device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an example of a structure of a color palette.

FIG. 2 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of a video encoder unit used in the image processing apparatus of the present invention.

FIG. 4 is a configuration diagram of a color palette RAM.

FIG. 5 is an explanatory diagram of a color palette address.

FIG. 6 is a table of color palette data of each unit.

FIG. 7 is an explanatory diagram of priority processing in a 256 dot mode.

FIG. 8 is an explanatory diagram of chroma key processing.

FIG. 9 is an explanatory diagram of data chroma key processing from each unit.

FIG. 10 is an explanatory diagram of an address register.

FIG. 11 is an explanatory diagram of a status register.

FIG. 12 is an explanatory diagram of a control register.

FIG. 13 is an explanatory diagram of a color palette address register.

FIG. 14 is an explanatory diagram of a color palette data write register.

FIG. 15 is an explanatory diagram of a color palette address offset register.

FIG. 16 is an explanatory diagram of a color palette address offset register.

FIG. 17 is an explanatory diagram of a color palette address offset register.

FIG. 18 is an explanatory diagram of a color palette address offset register.

FIG. 19 is an explanatory diagram of a priority register.

FIG. 20 is an explanatory diagram of a priority register.

FIG. 21 is an explanatory diagram of a chroma key Y (luminance) register.

FIG. 22 is an explanatory diagram of a chroma key U (color difference) register.

FIG. 23 is an explanatory diagram of a chroma key V (color difference) register.

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[Procedure amendment]

[Submission date] November 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction content]

When the 8-bit bus is selected, reading from the data read register is performed in the order of the lower byte and the upper byte, and the CPA is incremented when the upper byte is read.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0076

[Correction method] Change

[Correction content]

Next, the synchronizing signal generating function of the video encoder of the present invention will be described. The video encoder of the present invention has a built-in sync signal generation circuit, and by inputting a 12-fold color subcarrier frequency, dot clocks, -HSYNCA, -HS of horizontal sync signals are supplied to peripheral ICs.
YNCB, -HSYNC, and -V of vertical sync signal
Output SYNC. Also, since it has an external synchronization function, it can be synchronized with external video.

Claims (1)

[Claims] 1. An image processing apparatus capable of superposing and synthesizing a plurality of images, having a register for setting data of an appropriate value among color data capable of producing color as a key color and / or a value of an appropriate range. An image characterized by including a register for setting an upper limit value and a lower limit value corresponding to a key color using color data as a key color, and replacing the key color with an image output having a lower display priority and performing a composite output. Processing equipment.