JPH07320037A - Video data transfer device - Google Patents

Abstract

PURPOSE:To transfer only a part of a desired color of an animation to a frame memory at a high speed. CONSTITUTION:A color comparison part sets its color comparison signal CCMP to an L level when the color of animation video data MDATA is nearly equal to a specific color, or to an H level when not equal. An OR gate 610 inhibits video data from being written in a VRAM by holding a write signal/MWR at the H level when the color comparison signal CCMP is at the L level, and writes the video data in the VRAM by allowing the write signal/MWR to fall to the L level when the color comparison signal CCMP is at the H level. Consequently, only the animation part except a color specified as an object not to be transferred is transferred to a 2-port VRAM and displayed on a display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video data transfer device for transferring video data to a frame memory.

[0002]

2. Description of the Related Art As a method of transferring video data given from the outside to a video memory of a personal computer,
So-called DMA (Direct Memory Access) transfer can be used.

FIG. 39 is a block diagram showing a conventional computer system having a DMA controller for transferring video data to a video RAM. The three video memories 51R, 51G and 51B have color data Dr and D which are color-separated into red (R), green (G) and blue (B).
g and Db are stored respectively. These color data Dr, Dg, Db are binarized in advance by, for example, the dither method. The DMA controller 55 uses the address bus 53
The right to use the data bus 52 and the control bus 54 to the CPU
59 video, three video memories 51R, 51G, 5
Video RAM 56R, 56G, 56 for displaying binary color data Dr, Dg, Db stored in 1B in real time
Transfer to B respectively. The transferred binary color data Dr,
Dg and Db are sent to the monitor-control unit 57 through the VRAMs 56R, 56G and 56B to display the image on the monitor-58.

In the DMA transfer, first, the CPU 59
Sends the display start address in the VRAM 56R for the R component to the DMA controller 55 to activate the DMA controller 55. The DMA controller 55 acquires the right to use the bus from the CPU 59, transfers the binary color data Dr of the R component of the first line to the VRAM 56R for the R component, and then returns the right to use the bus to the CPU 59. next,
When the CPU 59 sends the display start address of the VRAM 56G for the G component to the DMA controller 55 and activates the DMA controller 55, the binary color data D is generated in the same manner as the R component.
Transfer of g is performed. Further, the B component is transferred in the same manner. When transferring the video data of the second line, use CP
U59 is 2 for each of VRAM 56R, 56G, 56B
The display start address of the line is calculated and sent to the DMA controller 55, and the binary color data Dr of each color of RGB is drawn.
, Dg, Db are sequentially transferred.

As described above, the CPU 59 controls the V for each line.
The display start address of the RAM 56R, 56G, 56B is calculated and taught to the DMA controller 55, and the DMA controller 55 responds to this by the color data Dr, D of each line.
By sequentially DMA-transferring g and Db, color data for one field is transferred to the VRAM 56. The "1 field" refers to an image covered by one scan from the upper left corner to the lower right corner of the screen. In many cases, 2: 1 interlace (interlaced scanning) is performed, and one field (one screen) image is composed of two fields. In this way, a moving image is displayed on the monitor 58 by sequentially DMA-transferring about 60 fields of binary color data per second.

[0006]

[Problems to be Solved by the Invention] NTSC (National T
When a video signal based on the Elevation System Commuttee method is used, the scanning period for one horizontal line is 63 μs. On the other hand, in the system of FIG. 39, the time when the CPU 59 calculates the display start address and transfers it to the DMA controller 55, the time when the DMA controller 55 acquires the right to use each bus from the CPU 59, and each binary color data D
When the time for DMA transfer of one line of r, Dg, and Db is summed up, only a few fields worth of data can be transferred per second. This is considered to be because it takes more time than necessary for the CPU 59 to calculate the display start address and to set the display start address in the DMA controller 55. Thus, in the conventional data transfer device,
Since only a few fields of data can be transferred per second,
It was impossible to display a smooth video.

Further, as shown below, the conventional data transfer device cannot transfer only the desired color portion of the transferred image. FIG. 40 is an explanatory diagram showing a method of synthesizing (superimposing) two videos by the device of FIG. 39. The image of the note symbol shown in FIG. 40 (A) is a still image generated by a personal computer, and is an image stored in advance in the VRAMs 56R, 56G, 56B of FIG. The image of the doll shown in FIG. 40B is a moving image DMA-transferred to the VRAM, and is an image stored in the memories 51R, 51G, and 51B.
The background of the doll has a predetermined uniform color. DM
When the A transfer is executed, the still image and the moving image are combined and the result shown in FIG.
An image like 0 (C) is displayed.

In FIG. 40 (C), since it is not necessary to display the uniform color portion (shown by diagonal lines in the figure) which is the background of the doll, the image data representing such background is not transferred to the VRAM. , There was a demand to display an image generated by a personal computer (that is, an image of a musical note symbol) instead of the background. However, in the past, since the entire moving image was transferred, it was impossible to prohibit only the transfer of the background portion.

The present invention has been made to solve the above-mentioned problems in the prior art, and an object thereof is to transfer only a desired color portion of a moving image to a frame memory at high speed.

[0010]

In order to solve the above problems, a video data transfer apparatus according to a first aspect of the present invention is provided with a frame memory for storing video data of a video displayed on a display device. A moving picture image data supplying means for supplying moving picture image data transferred to the frame memory, a bus connected to the frame memory,
A write address for writing the moving image video data in the frame memory is calculated, and a data transfer means for outputting the write address and the moving image video data to the bus, and a predetermined chromaticity range are defined. Color data memory for storing color data for storing, color comparison means for comparing the moving image video data with the color data and generating a color comparison signal indicating the comparison result, and the moving image according to the color comparison signal. Writing control means for controlling writing of video data to the frame memory.

Since the data transfer means calculates the write address by itself without receiving the write address from other means such as the CPU, the moving picture image data can be outputted on the bus at high speed. Further, since the writing of the moving image video data is controlled according to the color comparison signal, only the desired color portion of the moving image can be transferred to the frame memory at high speed.

In the video data transfer device according to a second aspect of the present invention, the color comparison means writes the frame memory when the chromaticity represented by the moving image data is within the predetermined chromaticity range. The color comparison signal is set to a prohibited first level, and when the chromaticity represented by the moving image data is out of the predetermined chromaticity range, the writing to the frame memory is permitted. And a color comparison signal setting means for setting the color comparison signal to the level.

In this way, only the image portion of the moving image outside the range of the predetermined chromaticity is written in the frame memory.

In the video data transfer device according to a third aspect of the present invention, the color data includes an upper limit value and a lower limit value of the video data component with respect to the three primary colors of RGB, respectively, and the color comparison signal setting means has the When the components of the three primary colors represented by the moving image data are in the range between the upper limit value and the lower limit value, the color comparison signal is set to the first level and each color of the moving image data is set. Means for setting the color comparison signal to the second level when at least one of the components is outside the range between the respective upper and lower limits.

In this way, the chromaticity range can be set arbitrarily by setting the upper limit value and the lower limit value for the three primary color components of the video data.

According to another aspect of the present invention, in the video data transfer device, the color data includes reference values of video data components for the three primary colors of RGB, and the color comparison signal setting means sets the video image data. When the three primary color components are equal to the respective reference values, the color comparison signal is set to the first level, and when at least one of the respective color components of the moving image data is different from the reference value, the color comparison signal is set to the first level. A comparator for setting the color comparison signal to the second level.

In this case, when the three primary color components of the moving image data are equal to the respective reference values, the writing to the frame memory is prohibited, and when at least one is not equal to the reference value, the writing to the frame memory is prohibited. Allowed

According to another aspect of the video data transfer device of the present invention, the data transfer means includes means for generating a write signal for permitting a write operation of the frame memory, and the write control means includes the write control means. A write signal adjusting means for adjusting the level of the write signal according to the value of the color comparison signal is provided.

If the level of the write signal is adjusted, writing of the moving picture image data to the frame memory can be permitted with a simple circuit configuration as compared with the method of controlling the moving picture image data having a large number of bits and the address. You can ban it.

According to another aspect of the video data transfer device of the present invention, the write signal adjusting means adjusts the level of the write signal for each dot by a logical operation of the color comparison signal and the write signal. Have means.

With such a structure, the level of the write signal can be easily adjusted.

In the video data transfer device according to claim 7, the data transfer means includes an address calculation means for calculating the frame memory and the write address when transferring the moving picture video data, and the address calculation means. Is a first memory that stores an offset address value that indicates the start position of the moving image video data writing area in the frame memory, and an addition address that indicates the difference between the addresses of adjacent scanning lines in the frame memory. A second memory for storing a value, and an order of scanning lines specified based on the number of pulses of the given horizontal synchronizing signal according to a vertical synchronizing signal and a horizontal synchronizing signal synchronized with the moving image data. Calculating a vertical address value equal to a value obtained by multiplying the scanning line number shown by the addition address value;
Calculating means, a horizontal counter for generating a horizontal address value on each scanning line in the moving image, which indicates a difference in address from a starting point of each scanning line to each pixel on each scanning line, the offset address value and the vertical Second arithmetic means for generating an address in the frame memory corresponding to a position of each pixel on each scanning line by adding an address value and the horizontal address value.

Since the write address is calculated by the arithmetic operation by the first calculating means and the second calculating means, the write address of the frame memory can be calculated at high speed and the video data can be transferred at high speed. .

[0024]

【Example】

A. Preparation of moving image data: FIG. 1 is an explanatory diagram showing how to specify a color to be excluded from DMA transfer. In FIG. 1, a doll is placed in front of a background BG (screen) having a uniform color. The background BG is an image portion that does not need to be displayed and has a predetermined color different from the color of the doll. As will be described later, a video portion having almost the same color as the background BG is not subject to DMA transfer.

The background BG color is analyzed as follows. First, a region including only the background BG (for example, the region R
1) is imaged by a video camera and the image data is analyzed by a personal computer. Fig. 2 shows the background BG
R (red) and G obtained by color separation of the video data of
It is a histogram showing the brightness of each color of (green) and B (blue). The horizontal axis represents% of brightness, and the vertical axis represents the number of pixels N. The term "luminance" in this specification indicates the stimulus values of the three primary colors. As shown in FIG.
A predetermined margin ε is set for the maximum value and the minimum value of the brightness of each color of RGB, and the upper limit values DUR, DUG, DUB and the lower limit value D of each color are set.
LR, DLG and DLB are determined respectively. At the time of DMA transfer, as will be described later, the respective upper limit values DU of RGB are
It is determined that the moving image data which falls between R, DUG, DUB and the lower limit values DLR, DLG, DLB has substantially the same color as the background BG. The process of analyzing the image data of the background BG and determining the upper limit values DUR, DUG, DUB and the lower limit values DLR, DLG, DLB is realized by a predetermined software program.

FIG. 3 is a diagram showing, on the CIE chromaticity diagram, the designated color range CA defined by the upper limit values DUR, DUG, DUB and the lower limit values DLR, DLG, DLB of the RGB colors thus obtained. This CIE chromaticity diagram is a chromaticity diagram recommended by the International Commission on Illumination, and is JIS Z870 in Japan.
It is specified in 1. The designated color range C in FIG.
A is a range of chromaticity close to pink. As the color of the background BG, it is possible to select any color which is not included in the desired image portion (the doll portion in the example of FIG. 1) desired to be DMA-transferred.

Next, an image of the doll moving in front of the background BG is captured. Although FIG. 1 shows an image of a planar object, an image of a three-dimensional object (human, animal, robot, etc.) moving in front of a background BG of a predetermined color may be captured. When the video signal of the moving image created in this way is given to the personal computer, the video portion having a color other than the designated color range CA is DMA-transferred to the frame memory and displayed on the color monitor.

B. System configuration: FIG. 4 shows the first of the present invention.
3 is a block diagram showing the configuration of a computer system as an example of the present invention. This computer system includes a personal computer main body 200 and a color CRT 300.
And a color liquid crystal display (LCD) 302. The personal computer body 200 is a CPU
202, RAM 204, ROM 206, I / O interface 208, and video accelerator 210
, 2-port VRAM 212, DA converter (DA
C) 214, an LCD driver 216, a DMA controller 220, an A / D converter 222, a video decoder 224, and a video input terminal 226. Of these, CPU 202, RAM 204, ROM 20
6, the I / O interface 208, the video accelerator 210, and the DMA controller 220 are CPs.
They are connected to each other by a U bus 201. Also, a video accelerator 210, a 2-port VRAM 212, a D
The MA controllers 220 are mutually connected by a local bus (address bus 228, data bus 229, control bus 230).

The DMA controller 220 and AD
Converter 222, video decoder 224, and video input terminal 22
6 can be implemented on one expansion board or expansion card.

The video input terminal 226 has a composite video signal VS from a video player or a television tuner.
Is given. Input composite video signal VS
Is decoded by the video decoder 224 and includes a color signal CS (component video signal) including luminance components of RGB colors, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HS.
It is decomposed into YNC and field indicating signal FIS.
The field instruction signal FIS is a signal that indicates an odd field or an even field in the case of interlaced scanning.

The color signal CS is converted from an analog signal to a digital signal by the AD converter 222, and the digitized video data DS is given to the DMA controller 220. The DMA controller 220 adjusts the number of bits of the digitized video data, and then transfers the video data to the 2-port VRAM 212. 2 port VR
The video data read from the AM 212 is given to the color CRT 300 via the D / A converter 214, and the liquid crystal display 3 via the LCD driver 216.
Given to 02.

FIG. 5 is a block diagram showing the internal structure of the DMA controller 220. DMA controller 22
0 is a 3-state OR with the CPU interface 310
Gate 610 and two 3-state buffer circuits 61
2, 614, a color comparison unit 550, a DMA address calculation unit 312, a data output unit 314, and a DMA control unit 31.
6, the FIFO memory unit 318, and the color adjustment unit 32
It has 0 and.

The digital video signal DS supplied to the color adjusting section 320 is 24-bit (8 bits for each RGB) full-color video data. The color adjusting unit 320 can reproduce the 24-bit digital video signal DS in 16 bits (R: G: B = 5: 6: 5 bits can reproduce 16.77 million colors) and 8 bits (R: G). : B = 3: 3: 60,000 colors can be reproduced with 2 bits, 4 bits (16 colors can be reproduced with a color palette), 3 bits (8 colors can be reproduced with a color palette) Is.
When converting to 4-bit or 3-bit video data,
Binarization by the dither method is executed. The color palette is provided on the output side of the 2-port VRAM 212. The type of video data to be converted is set by the CPU 202 according to the operator's designation. However, in the following, 24-bit full-color video data (referred to as “component video data”) is used as the color adjustment unit 3.
The case where 20 outputs as it is will be described.

The FIFO memory unit 318 incorporates the video data VD supplied from the color adjusting section 320.
It has a function of temporarily storing the data in one FIFO memory and adjusting the timing of data transfer. The video data VD (= MD output from the FIFO memory unit 318
ATA) is held by the latch in the data output unit 314 and is output to the local data bus 229 (FIG. 1) via the 3-state buffer circuit 614.

The DMA controller 316 uses the address bus 22.
8, the data bus 229 and the control bus 230 are acquired from the video accelerator 210, and the video data M is acquired.
Transfer DATA to the 2-port VRAM 212. At this time, the DMA address calculation unit 312 calculates an address,
3-state buffer circuit 612 and address bus 22
The address is supplied to the 2-port VRAM 212 via 8.

A DMA request signal / DMARQ is used as a control signal related to the transfer of the video data MDATA.
, DMA permission signal / DMAACK, and write signal / MW
There is R. It should be noted that in FIG. 5, a line drawn above the signal name means negative logic, and in the specification, a slash “/” is added before each signal name. . DMA request signal / DMARQ is DMA
The control unit 316 is a signal for requesting the DMA transfer to the video accelerator 210. DMA enable signal / DMAAC
In K, the video accelerator 210 is the DMA control unit 31.
6 is a signal for permitting DMA transfer. Write signal / MW
R is a signal that causes the 2-port VRAM 212 to write data.

The 3-state OR gate 610 masks the write signal / MWE output from the DMA control unit 316 with the color comparison signal CCMP supplied from the color comparison unit 550 when transferring the video data to the 2-port VRAM 212. It is a gate to do. That is, the color comparison signal C
If CMP is at H level, the write signal / MWE output from the DMA control unit 316 is the 3-state OR gate 61.
It passes through 0 as it is and is given to the 2-port VRAM 212 as a write signal / MWR. On the other hand, the color comparison signal CCM
If P is at L level, write signal / MWE output from DMA control unit 316 is blocked by 3-state OR gate 610, and write signal / MWR provided to 2-port VRAM 212 is always kept at L level. Be done. That is, 3
The state OR gate 610 has a function as a write signal adjusting unit. Details of such an operation will be described later.

The 3-state OR gate 610 and 2
The three 3-state buffer circuits 612 and 614 are kept in a high impedance state during the operation of the video accelerator 210.

In this embodiment, the OR gate 610 adjusts the level of the write signal / MWR to control the writing of the video data MDATA into the 2-port VRAM 212, so that the circuit configuration is simple. There is an advantage. Further, since the video data MDATA and the address MADD may be output on the bus as in the case of DMA transfer of the entire moving image, the video data MDAT
It is not necessary to adjust A and the address MADD according to the colors not to be transferred. That is, since the operation of the DMA transfer process itself is simple, high-speed DMA transfer can be realized.

Conventionally, when a moving image and a still image are combined, a video memory dedicated to the moving image is required in addition to the frame memory for display. The computer system according to this embodiment also has an advantage that moving image data can be transferred at high speed without the need for a moving image dedicated video memory.

FIG. 6 is a block diagram showing the internal structure of the color comparing section 550. The color comparison unit 550 has a comparison value storage circuit 552 and a color comparison circuit 554. The comparison value storage circuit 552 uses the background BG provided from the CPU 202.
Upper limit value DUR, DUG, DUB and lower limit value DLR of each RGB color of
Memorize DLG and DLB (Fig. 2). The upper limit value and the lower limit value are given from the comparison value storage circuit 552 to the color comparison circuit 554. The comparison value recording circuit 552 has a function as a color data memory, and the color comparison circuit 554 has a function as a color comparison signal setting means.

FIG. 7A is a block diagram showing the internal structure of the color comparison circuit 554. The color comparison circuit 554 is RG
Window comparator 5 for the video data component of each color of B
60 and an AND circuit 570. However, in FIG. 7A, the window comparators for the G component and the B component are omitted for convenience of illustration. The processing of the color comparison circuit 554 for the R component of the video data will be described below.

The window comparator 560 has two comparators 562 and 564 and an AND circuit 566.
The first comparator 562 compares the upper limit value DUR given from the comparison value storage circuit 552 with the R component of the video data MDATA given from the data output unit 314. on the other hand,
The second comparator 564 compares the lower limit value DLR given from the comparison value storage circuit 552 with the R component of the video data MDATA. The outputs of the two comparators 562 and 564 are AN
It is input to the D circuit 566. As a result, the AND circuit 56
A comparison signal CR is output from 6. The comparison signal CR becomes H level when the value of the R component of the video data MDATA is within the range of the upper limit value DUR and the lower limit value DLR, and the upper limit value D
When it is outside the range of UR and the lower limit value DLR, it becomes L level. Window comparator 56 for G component and B component
Similarly, 0 also generates the comparison signals CG and CB, respectively. These comparison signals CR, CG and CB are 3-input AND
It is input to the circuit 570.

The color comparison signal CCMP, which is the inverted output of the 3-input AND circuit 570, is the RGB of the video data MDATA.
When all the values of each color component of are within the range of the respective upper limit value and lower limit value, the L level is set. On the other hand, when the value of at least one color component is outside the range between the upper limit value and the lower limit value, the color comparison signal CCMP becomes H level. In other words, the color comparison signal CCMP is the video data MDATA.
When the color represented by is included in the designated color range CA shown in FIG. 4, it becomes L level, and when it is outside the designated color range CA, it becomes H level. Since the designated color range CA indicates the chromaticity of the background BG of the image, the image data MDA
In the portion where the color represented by TA has the same chromaticity as the background BG, the color comparison signal CCMP becomes L level.

FIG. 7B shows the moving image data MDATA.
Shows the configuration of the color comparison circuit 554a when is data of 4 bits. For video data that uses a color palette during color reproduction, such as 4-bit video data, a 4-bit comparator 554a as shown in FIG. 7B is used as a color comparison circuit. This comparator 554a
Generates a color comparison signal CCMP by comparing the 4-bit video data MDATA with the 4-bit reference value Dref.
The reference value Dref is the upper limit value DU and the lower limit value D described above.
It can be regarded as a comparison value when L and L are equal. When the video data MDATA and the reference value Dref are equal to each other, the comparator 554a outputs an L level color comparison signal CCMP.
When the video data MDATA and the reference value Dref are not equal, the H level color comparison signal CCMP is output.

As shown in FIG. 5, the color comparison signal CCMP is applied to the OR gate 610 as the write signal adjusting means. The background B is the color represented by the video data MDATA.
When the chromaticity is almost equal to G, the color comparison signal C
Since CMP becomes L level, transfer of the video data MDATA to the 2-port VRAM 212 is blocked. on the other hand,
When the color represented by the video data MDATA is different from the color of the background BG, the color comparison signal CCMP becomes H level,
The video data MDATA is written in the 2-port VRAM 212. As a result, as shown in FIG. 8, only the video part of the doll in the moving image is superimposed on a part of the still image of the musical note symbol. Note that the still image of the musical notation is the CPU
2 port VRAM 212 created in advance by 202
It is the image that was stored in.

The moving image data MDATA is, for example, 30
DMA transfer is performed to the 2-port VRAM 212 at a rate of frame / second (60 fields / second). Since the doll in the moving image is moving, the appearance of the doll in each field of the moving image to be DMA transferred is sequentially changing. When these fields are overwritten in the 2-port VRAM 212, the image actually displayed on the display device becomes an image showing the locus of movement of the doll. For example, if a video showing a golf swing of a person is used as a moving image, the trajectory of the swing is sequentially displayed on the display device. The data transfer device according to this embodiment can easily display the locus of such an operation.

When it is not desired to display the motion locus, D
1 field for MA controller 220 or 1
The DMA transfer of the moving image for the frame and the writing of the still image to the 2-port VRAM 212 by the video accelerator 210 may be alternately performed. CPU
Each time the 202 receives the interrupt of the vertical synchronization signal VSYNC twice, it allows the DMA controller 220 to perform DMA transfer for one field, and allows the video accelerator 210 to write a still image during this DMA transfer. In this case, 30 fields / second (15 frames / second)
It is possible to transfer a moving image by DMA. in this way,
If the moving image and the still image are alternately written in the 2-port VRAM 212, the locus of operation is not displayed, and
A moving video is displayed.

C. Outline of DMA transfer processing of moving image data: In the following, the DMA transfer processing along the vertical direction (on the Y1-Y2 line) in FIG. 8C and the horizontal direction (X1-X2).
The operation of the DMA transfer process along the line) will be described.

FIG. 9 is a timing chart showing the operation of vertical DMA transfer. First, the CPU 202
When the operation start instruction is given to the MA control unit 316 (FIG. 5) (FIG. 9A), the DMA control unit 316 outputs the DMA request signal / DMARQ onto the control bus 230.
Then, the video accelerator 210 gives a DMA permission signal / DMAACK to the DMA control unit 316,
DMA controller 220 uses local buses 228, 22
Acquire usage rights of 9,230.

On the other hand, when the vertical synchronizing signal VSYNC is given to the DMA controller 220 after the DMA transfer instruction is given from the CPU 202, the DMA controller 2
20 is set to the initial state.

Although the back porch period continues after the vertical synchronizing signal VSYNC, the details thereof are omitted in FIG. During the effective video period after the back porch period, D
While the MA permission signal / DMAACK (FIG. 9 (e)) is at the L level, the DMA controller 220 sets the address MAD
D (Fig. 9 (f)) and video data MDATA (Fig. 9
(G)) and the write signal / MWR (FIG. 9 (i)) are output onto the local bus to perform DMA transfer.

While the color comparison signal CCMP (FIG. 9 (h)) output from the color comparison unit 550 is at L level, the write signal / MWR output from the OR gate 610 (FIG. 5) is kept at H level. Since it falls down, writing of the moving image video data MDATA into the 2-port VRAM 212 is prohibited. on the other hand,
While the color comparison signal CCMP is at the H level, the write signal / MWR output from the DMA control unit 316 is the OR gate 6.
Since it passes through 10 as it is and becomes the write signal / MWR of the 2-port VRAM 212, the moving image data MDATA is written in the 2-port VRAM 212.

The DMA permission signal / DMAACK is H
During the level period, the video accelerator 210 uses the bus (FIGS. 9 (j) to 9 (l)).

FIG. 10 is a timing chart showing the operation of the DMA transfer in the horizontal direction. The horizontal synchronizing signal X of FIG.
The operation during one cycle of HSYNC is shown. The horizontal synchronizing signal XHSYNC is supplied to the video decoder 224.
The first horizontal synchronizing signal HSYNC given from (FIG. 4)
The sync signal is generated by the FIFO memory unit 318 (FIG. 5) based on the above, and is a synchronization signal that defines the period of one horizontal line of the moving image video data MDATA written in the two-port VRAM 212.

In FIG. 10, DMA permission signal / DMA
The address MADD of the DMA transfer and the video data MDATA are output to the local bus while the ACK is kept at the L level. However, while the color comparison signal CCMP is at the L level, the write signal / MWR applied to the 2-port VRAM 212 is kept at the H level, so that the video data MD
Writing of ATA is prohibited. On the other hand, the color comparison signal CCM
While P is at the H level, the write signal / MWR falls to the L level for each dot, and the video data MDATA of each dot is generated.
(RGB data) is written in the 2-port VRAM 212.

FIG. 11 shows part A (color comparison signal CC of FIG.
It is a timing chart which shows the detail of the step part of MP.
As can be seen from FIG. 11, the address MADD (= TADD) and the video data MDA for each dot (one pixel) on the screen.
TA and have been updated. Further, the write signal / MWR falls to the L level only while the color comparison signal CCMP is at the H level, and in response to this, the video data MDATA is converted into the 2-port V signal.
It is written in the RAM 212.

As described above, the moving image data MDATA
Of the color comparison signal C to the 2-port VRAM 212
It is permitted when CMP is at H level and prohibited when it is at L level. As described in FIG. 7, the color comparison signal C
The CMP is a signal that becomes H level when the color of the moving image is outside the range of the predetermined designated color, and becomes L level when it is within the range of the designated color. Therefore, only the moving image video data MDATA outside the specified color range is written in the 2-port VRAM 212. As described with reference to FIG. 1 to FIG. 3, the designated color range CA indicates a color that is substantially the same as the background BG of the moving image, and therefore the image data MDA representing the background BG of the moving image
TA is not written to the 2-port VRAM 212 and the background B
Only the video data MDATA representing the video portion other than G (that is, the doll portion) is written in the 2-port VRAM 212.

Instead of controlling the writing of the video data by controlling the level of the write signal / MWR by the color comparison signal CCMP, the 2-port VRAM2 is used in the write per bit mode which is a function peculiar to the video RAM.
It is also possible to prohibit the 12 write operations in bit units.

D. Details of Circuit Configuration in DMA Controller 220: The DMA controller 220 shown in FIG. 5 has a function of calculating an address at the time of DMA transfer of moving image data, and a function of arbitrarily scaling a moving image vertically and horizontally. have. Below, these functions and the configuration of circuits related thereto will be described.

FIG. 12 is a block diagram showing an internal structure of the FIFO memory unit 318 shown in FIG. 12
As shown in (A), a FIFO memory unit 318
Is a FIFO control unit 321 and two FIFO memories 3
22 and 324 are provided. Further, as shown in FIG. 12B, the FIFO control unit 321 has five PLL circuits 32.
It has 5-328,510 and the waveform shaping part 511. The first to third PLL circuits 325 to 327 multiply the frequency of the horizontal synchronization signal HSYNC by NH0, (NH0 * H).
X) times and NH times signals CLKI, CLKO,
Generate DCLK respectively. Further, the fourth PLL circuit 328 generates a signal HINC that is the frequency of the vertical synchronizing signal VSYNC multiplied by NV. Fifth PLL circuit 510
Is the horizontal synchronization signal HSYN, as shown in FIG.
A signal HSYNC * HX obtained by multiplying the frequency of C by HX is generated, and the waveform shaping section 511 detects the rising edge thereof to generate the second horizontal synchronization signal XHSYNC. The second horizontal synchronizing signal XHSYNC is a synchronizing signal having a frequency that is HX times the frequency of the first horizontal synchronizing signal HSYNC.
The set values NH0, (NH0 * HX) in each PLL circuit,
NH, NV and HX are set by the CPU 202. These PLL circuits 325 to 328 are circuits for enlarging / reducing images, and their functions will be described later.

The two FIFO memories 322 and 32 are
Reference numeral 4 has a function as a video data buffer for temporarily storing a predetermined amount of video data, and the FIFO control unit 321 has a function as a video data buffer control unit. Further, the first PLL circuit 325 serves as an input clock generation means, the second PLL circuit 326 serves as an output clock generation means, the third PLL circuit 327 serves as a dot clock generation means, and the fourth PLL circuit 328 serves as a line increment. Each has a function as a signal generation means. The second and fourth PLL circuits 326, 3
28 and the FIFO memory unit 318 work together,
It exerts a function as a scaling unit that can scale an image vertically. In addition, the second and third PLL circuits 326 and 327
Cooperate with each other to exert a function as a scaling means capable of scaling a video represented by video data in the horizontal direction.

As shown in FIG. 5, the video data output from the FIFO memory unit 318 is output to the data bus 229 via the data output unit 314. Then, the DMA control unit 316 acquires the right to use the address bus 228, the data bus 229, and the control bus 230 from the video accelerator 210, and transfers the video data MDATA to the 2-port VRAM 212.

FIG. 13 shows a DMA address calculation unit 312 and a data output unit 314 in the DMA controller 220.
3 is a block diagram showing an internal configuration of a DMA control unit 316. FIG. The data output unit 314 includes a latch 364 for holding the component video data VD. When outputting the component video data VD for a plurality of pixels together on the data bus 229, serial / serial
A parallel converter may be provided.

The DMA address calculation unit 312 has an offset address storage unit 330 and an addition address value storage unit 33.
2, a vertical counter unit 334, and a horizontal counter unit 336.
, And a multiplier 338 and two adders 340 and 342. The multiplier 338 is used by the addition address value storage unit 3
The added address value stored in 32 and the vertical counter unit 3
It is multiplied by the vertical count value output from 34. The first adder 340 adds an offset address (described later) stored in advance in the offset address storage unit 330 and the multiplication result of the multiplier 338. The second adder 342 adds the addition result of the first adder 340 and the count value of the horizontal counter unit 336. The output AD2 of the second adder 342 is VR
It becomes the address MADD given to the AM 212. Second
Adder 342 has a tri-state output.

E. Address calculation during data transfer: Fig. 14
Is a memory map of the 2-port VRAM 212. One word of this VRAM 212 is 24 bits, and one word contains R component, G component and B component of video data. Further, one pixel (one dot) on the screen corresponds to one word.

FIG. 15 is an explanatory diagram showing the correspondence between the memory space of the VRAM 212 and the screen. In this figure, V
The number of pixels of the horizontal range 80 of the RAM 212 is 640 (50
The number of scanning lines in the vertical range 81 is 199h.
(= 409). The moving image area MPA in which the moving image data is written by the DMA transfer has a width of 2 pixels in the horizontal direction from the start position of the second pixel in the horizontal direction on the second line in the vertical direction, as shown by the diagonal lines in FIG. It is an area of 4 pixels in total having a width of 2 lines in the vertical direction.
It should be noted that the position and size of the moving image area MPA can be set by the operator in the color CRT 300 or the color liquid crystal display 30.
Specify on screen 2.

Although the moving image area MPA is a rectangular area, as described above, only the video data having a color other than the designated color according to the level of the color comparison signal CCMP is written in the 2-port VRAM 212. However, for convenience of description, a case where all the video data in the moving image area MPA is written in the 2-port VRAM 212 will be described below.

FIG. 16 is a plan view showing a moving image area MPA on the screen of the color CRT 300. The memory space shown in FIG. 15 has a 1: 1 correspondence with the display screen of the color CRT 300 shown in FIG.

In the following, address calculation when interlaced scanning is not performed will be described first, and address calculation when interlaced scanning is performed will be described later.

FIG. 17 is an enlarged block diagram showing the address calculation unit 312. Offset address storage unit 3
The offset address OFAD stored in 30 is shown in FIG.
5, the moving image area MP from the start address 0000h
It is an offset value (51h) up to the address (0051h) of the write start position of A.

Address of write start position (= 0051
h) is determined according to the position of the upper left point P1 of the moving image area MPA (FIG. 16) designated by the operator on the screen. When the operator specifies the moving image area MPA, the CPU
202 calculates the address (= 0051h) of the write start position corresponding to the upper left point P1, and this address (= 005
1h) is set in the offset address storage unit 330 as the offset address OFAD. The operator can set the moving image area MPA of any size at any position on the screen of the color CRT 300 or the color liquid crystal display 302, and the offset address O can be set accordingly.
FAD is set.

The addition address ADAD stored in the addition address value storage unit 332 is equal to the number of pixels of one scanning line in the memory space, and is set to 50h in this embodiment.

The output MUL of the multiplier 338 and the outputs AD1 and AD2 of the two adders 340 and 342 are given by the following arithmetic expressions, respectively. MUL = ADAD × VCNT… (1) AD1 = OFAD + MUL… (2) AD2 = AD1 + HCNT… (3)

Summarizing the above equations (1) to (3), the output AD2 of the second adder 342 for each pixel is given by the following arithmetic equation. AD2 = (ADAD × VCNT) + OFAD + HCNT (4)

The vertical count VCNT indicates the scanning line number in the moving image area MPA. The horizontal count HCNT indicates the position measured from the left end point of each scanning line in pixel units, and corresponds to the horizontal address value in the present invention. In addition,
The output MUL of the multiplier 338 corresponds to the vertical address value in the present invention.

Equation (4) above is the vertical count VCNT.
And an address AD2 corresponding to the position indicated by the horizontal count HCNT. In this embodiment, A
Since DAD = 50h and OFAD = 51h, the equation (4) can be rewritten as the following equation (5). AD2 = (50h × VCNT) + 51h + HCNT… (5)

As will be described later, the moving image area MPA (see FIG.
Each time the DMA transfer for one scanning line in 6) is completed, the vertical count VCNT is incremented by one, and each time one-word video data of each pixel is DMA transferred on the same scanning line. The horizontal count HCNT is incremented by 1.
As a result, the component video data VD representing the video in the moving image area MPA is written in the VRAM 212 according to the address shown by the above equation (5).

F. Detailed operation of data transfer: FIG. 18 is a timing chart showing details of the operation of the DMA transfer shown in FIG. When the back porch period has passed and the second horizontal synchronizing signal XHSYNC becomes L level in the effective video period, the horizontal counter section 336 is reset to 0 to start the operation, and the vertical counter section 334 starts counting up. It Here, the vertical counter unit 33
In order to understand the operation of No. 4, the internal configuration will be described.

FIG. 19 is a block diagram showing an internal structure of the vertical counter section 334 and a related portion in the FIFO control section 321. PLL circuit 327 of FIFO control section 321
Is the horizontal synchronizing signal H supplied from the video decoder 224.
Dot clock signal DC with SYNC frequency multiplied by NH
Generate LK. Further, the other PLL circuit 328 generates a line increment signal HINC obtained by multiplying the frequency of the vertical synchronization signal VSYNC by NV. The line increment signal HINC is used when the image is reduced in the vertical direction, as described later. Here, first, the frequency of the line increment signal HINC is the second horizontal synchronization signal X.
The DMA transfer when it is the same as HSYNC will be described. If the frequency of the line increment signal HINC is the same as the second horizontal synchronization signal XHSYNC,
The image is not reduced.

The vertical counter unit 334 has a back porch storage unit 402, a comparator 404, a back porch counter 406, a vertical counter 408, and a latch 410. The back porch storage unit 402 is a back porch number BP given from the CPU 202 via the CPU bus.
Memorize Here, the back porch number BP is the pulse number of the horizontal synchronizing signal HSYNC in the back porch period. The back porch counter 406 is supplied with the first horizontal synchronizing signal HSYNC, and the clock input terminal of the latch 410 is supplied with the second horizontal synchronizing signal XHSYNC. A line increment signal HINC is given to the clock input terminal of the vertical counter 408. The vertical sync signal VSYNC is applied to the reset input terminals of the back porch counter 406 and the vertical counter 408.
Is given. The comparator 404 compares the back porch number BP stored in the back porch storage unit 402 with the count value BPC of the back porch counter 406.

The output CMP of the comparator 404 is BP = BPC
When it is, it becomes H level, and when BP ≠ BPC, it becomes L level. The back porch counter 406 is the comparator 4
When the output CMP of 04 is L level, it is enabled,
The vertical counter 408 is enabled when CMP is at H level.

When the vertical synchronizing signal VSYNC is applied to the vertical counter section 334, the back porch counter 406 and the vertical counter 408 are reset. At this time, since the output CMP of the comparator 404 is L level, the back porch counter 406 is enabled, and the horizontal synchronization signal HS is output.
Count the number of YNC pulses. On the other hand, the vertical counter 408 remains stopped. Horizontal sync signal HSYNC
When the number of pulses of (1) is input to the back porch counter 406 by the number equal to the back porch number BP, BP = BPC. As a result, the output CMP of the comparator 404 becomes H level, the back porch counter 406 stops, and the vertical counter 408 starts counting up.
The count value CNT of the vertical counter 408 is latched 410 at the rising edge of the second horizontal synchronization signal XHSYNC.
, And is output as the vertical count VCNT. This vertical count VCNT indicates the scanning line number on the screen. When no reduction is performed in the vertical direction, the frequencies of the second horizontal synchronizing signal XHSYNC and the line increment signal HINC are equal, and thus the vertical count VCNT is equal to the number of pulses of the second horizontal synchronizing signal XHSYNC.

As described above, the vertical counter 408 and the latch 410 have a function as means for adding the scanning line numbers.

Control signal generator 3 in DMA controller 316
60 (FIG. 13), the dot clock signal D generated by the PLL circuit 327 (FIG. 19) of the FIFO control unit 321.
CLK is given. The control signal generating section 360 controls the horizontal counter section 336 in synchronization with the dot clock signal DCLK.

In the period TT1 of FIG. 18, one pixel (=
1 word = 24 bits) worth of video data MDATA is D
Upon MA transfer, the control signal generator 360 outputs the word synchronization signal WSYNC to the horizontal counter 336. The control signal generation unit 360 uses the dot clock signal DC
One pulse of the word synchronization signal WSYNC is output for each pulse of LK. The horizontal counter unit 336 counts the horizontal count HCNT in response to each pulse of the word synchronization signal WSYNC.
Count up by one. In the period TT1, since VCNT = 0h and HCNT = 0h in the above equation (5), AD2 = 0051h. This address AD
2 corresponds to the address of the upper left portion of the moving image area MPA shown in FIG.

In the period TT2, VCNT = 0h, HCN
Since T = 1h, AD2 = A0052h. The address AD2 corresponds to the address in the upper right portion of the moving image area MPA shown in FIG.

As described above, in the periods TT1 and TT2, the first scanning line L1 in the moving image area MPA shown in FIG.
Ends the transfer. Therefore, when the period TT2 ends, the second horizontal synchronizing signal XHSYNC indicating the end and start of the scanning line is given to the DMA control unit 316. The second horizontal synchronization signal XHSYNC is shown in FIG.
As shown in (B), it is a signal generated by multiplying the frequency of the first horizontal synchronization signal HSYNC by HX in the FIFO control unit 321.

In response to the pulse of the second horizontal synchronizing signal XHSYNC indicating the start of the period TT3, the vertical counter unit 33
Vertical count VCNT of 4 is incremented by 1 and VCNT = 1
At the same time as h, the horizontal count HCNT of the horizontal counter unit 336 is reset to 0. After that, the video data MDATA is transferred to the VRAM2 by the same procedure as described above.
Twelve addresses 00A1h and 00A2h are sequentially transferred.

When the DMA transfer for all the scanning lines L1 and L2 in the moving image area MPA (FIG. 16) is completed in this way, the vertical counter section 334 and the horizontal counter section 336 are reset to 0 according to the vertical synchronizing signal VSYNC. As a result, the DMA controller 220 returns to the initial state and waits until the video data of the next field is sent.

As described above, when the image is not reduced in the vertical direction, the vertical count VCNT and the horizontal count HCNT are reset to 0 each time the vertical synchronization signal VSYNC is applied, and the second horizontal synchronization signal XHSYNC is set. Each time it is applied, the vertical count VCNT is incremented by 1 and the horizontal count HCNT is reset to 0.
When the image is reduced in the vertical direction, the vertical count VCNT increases according to the second horizontal synchronizing signal XHSYNC and the line increment signal HINC, which will be described later.

As described above, the vertical count VCNT
Is counted up according to the second horizontal synchronizing signal XHSYNC and the line increment signal HINC, and the horizontal count HCNT is counted up according to the word synchronizing signal WSYNC. Since the address on the VRAM 212 is obtained according to the above equation (5), the second
The address on the VRAM is sequentially updated according to the horizontal synchronizing signal XHSYNC, the line increment signal HINC, and the word synchronizing signal WSYNC. As a result, the video data MDATA representing the video in the moving image area MPA is stored in the VRAM2 every 1/60 seconds.
12, and the moving image is displayed.

G. Address calculation when interlaced scanning is performed: FIG. 20 is an explanatory diagram showing a memory space of odd line fields and even line fields when interlaced scanning is performed, and is a diagram corresponding to FIG. The odd line field has two addresses 00A1h, 00A out of the four addresses in the moving image area MPA.
2h only, the even line field is
Only one address 0051Ah, 0052A is included.

When interlacing is performed, an offset address OFAD1 = A1h for odd line fields and an offset address OFAD2 for even line fields are stored in the offset address storage unit 330 (FIG. 13).
= 51h is registered. Offset address storage unit 33
0 represents these two offset addresses OFAD1,
One of OFAD2 is selectively output according to the field instruction signal FIS. In the case of 2: 1 interlace, the addition address ADAD is twice (= A0h) the value (= 50h) when there is no interlace. Thus, in the case of interlaced scanning, by adjusting the offset address OFAD and the addition address ADAD, the address of the video data can be calculated according to the above equation (5), as in the case without interlacing.

Even when video data for interlacing is transferred, it is possible to write video data of odd line fields and even line fields at the same address without intentionally performing interlacing. In this case, the offset address OFAD and the addition address ADAD when there is no interlace may be commonly used for both fields.

According to the above embodiment, the address calculation unit 312 inside the DMA controller 220 is composed of only one multiplier and a plurality of adders, so that the address can be calculated at high speed. Furthermore, since the DMA transfer can be executed without requiring a video memory other than the VRAM 212, there is an advantage that the circuit configuration of the entire computer system is relatively simple and can be configured at low cost.

H. Image enlargement / reduction processing: In this computer system, the FIFO memory unit 318 (FIG. 12) has a function of enlarging / reducing an image. Figure 2
FIG. 1 is an explanatory view for explaining the function of vertically expanding, (a) shows input video data VDI, (b) shows output video data VDO, and (c) shows operations of two FIFO memories. . However, in FIGS. 21A and 21B, for convenience of illustration, the video data is drawn in the form of the original analog video signal VS.

As shown in FIG. 21C, two FIFs are
Input terminals and output terminals of the O memories 322 and 324 are complementarily and alternately switched by virtual toggle switches 323a and 323b. These virtual toggle switches 323a and 323b receive the two FIFO memories 322 and 32 according to the input enable signal RE and the output enable signal OE provided from the FIFO control section 321.
It is equivalently shown that the inputs and outputs of 4 are complementarily and alternately switched. Two FIFO memories 322,3
An input clock signal CLKI and an output clock signal CLKO are commonly supplied to 24. As can be seen from FIG. 12B, the frequency fCLKI of the input clock signal CLKI is the frequency of the horizontal synchronizing signal HSYNC multiplied by NH0, and when the video signal VS given to the video input terminal 226 is an NTSC signal. Has a constant frequency of about 6 MHz. On the other hand, the frequency f of the output clock signal CLKO
CLKO is H of the frequency fCLKI of the input clock signal CLKI.
The value is X times (HX is an integer) (see FIG. 12B).
That is, the PLL that generates the output clock signal CLKO
The set value (NH0 * HX) of the circuit 326 is set to HX times the set value NH0 of the PLL circuit 325 that generates the input clock signal CLKI. In this example, assume HX = 3.

21A and 21B, the first period TT1
In the first and third periods TT13, the first FIFO memory 3
The input video data VDI is written in 22 and the second FI
The output video data VDO is read from the FO memory 324. In the second period TT12, the input video data VDI is written in the second FIFO memory 324, and the first F
The output video data VDO is read from the IFO memory 322. As a result, in the first period TT11, the video data regarding the first scanning line L1 is stored in the first FIFO memory 32.
Written to 2. In addition, in the second period TT12, the video data regarding the second scanning line L2 is written in the second FIFO memory 324. In the example of FIG. 21, the frequency fCLKO of the output clock signal CLKO is the input clock signal CLK.
Since the frequency is set to 3 times the frequency fCLKI of I, the video data regarding the first scanning line L1 is read from the first FIFO memory 322 three times in the second period TT12.

FIG. 22 is an explanatory diagram showing how the image is enlarged and reduced in the vertical direction. 22A shows the input video data VDI, and FIG. 22B shows the output video data VDO.
Is shown. In the output video data VDO, each scanning line of the input video data VDI is repeated HX (= 3) times, so that the video is HX vertically.
(= 3) times as large. In FIG. 22 (B),
For example, “L1a”, “L1b”, and “L1c” indicate that the video data of the original scanning line L1 is repeatedly output three times. As described above, the frequency fCLKO of the output clock signal CLKO is changed to the frequency fCLKI of the input clock signal CLKI by using the two FIFO memories 322 and 324.
It is possible to enlarge the image in the vertical direction by an integral multiple by setting the integral multiple of.

The vertical reduction is performed by the FIFO shown in FIG.
It is realized by the PLL circuit 328 in the control unit 321 and the vertical counter 408 and the latch 410 in the vertical counter unit 334. FIG. 23 is a timing chart showing the reduction operation in the vertical direction. The line increment signal HINC generated by the PLL circuit 328 (see FIG.
(A)) shows the frequency fVSYNC of the vertical synchronization signal VSYNC.
Of the frequency fHINC. The second horizontal synchronizing signal XHSYNC (FIG. 23 (c)) is the vertical synchronizing signal V
The frequency fXHSYNC is (NV0 * HX) times the frequency fVSYNC of SYNC, and the value of NV0 is the number of scanning lines in one field in the original analog video signal VS (hereinafter, referred to as "total number of image lines"). It is a constant value (NV0 = 262.5 in the case of NTSC signal) shown. Note that FIG.
As shown in (B), if the total number of image lines of the image represented by the analog image signal VS is NV0, the number of effective image lines is NVL, and the number of display lines when displaying the image on the display device is NVM, The set value NV of the PLL circuit 328 is given by the following equation. NV = NVM * HX * NVO / (HX * NVL) = NVM * NV0 / NVL However, NVM≤HX * NVL.

In the above equation, for example, NV0 = 262.
5, NVL = 240, NVM = 480 are substituted, NV = 5
25.

The vertical counter 408 (FIG. 19) counts up the count value CNT (FIG. 23 (b)) in response to the rising edge of the line increment signal HINC,
Further, the latch 410 receives the second horizontal synchronizing signal XHSYNC.
The count value CNT of the vertical counter 408 is latched according to the rising edge of
(D)) is output.

In the example of FIG. 23, the frequency fHINC of the line increment signal HINC and the second horizontal synchronizing signal XHS
YNC frequency fXHSYNC ratio (NV / NV0 * HX) is 2
/ 3, and accordingly, the vertical count VCNT (Fig. 23 (d)) has the same value of 1 for every second such as 0, 1, 2, 2, 3, 4, 4, 5. Repeated times. Since the vertical count VCNT indicates the vertical address in the VRAM 212, the video data of the third scanning line L1c and the video data of the fourth scanning line L2a are written at the third vertical address VCNT = 2. . As a result, the video data of the scanning line L1c first written at the third vertical address VCNT = 2 is changed to the next scanning line L2.
It is replaced with the video data of a. When this is repeated, the image data of the scanning lines located at the multiples of 3 are thinned out, and the result is reduced in the vertical direction.

FIGS. 22B and 22C show the manner in which the image is vertically reduced by the operation of FIG. The video data VDO enlarged by HX times by switching between the two FIFO memories 322 and 324 extends over nine scanning lines L1a to L3c. Among them, the video data of the third scanning line L1c is the next. The video data of the scanning line L2a is replaced, and the video data of the sixth scanning line L2c is also replaced by the video data of the next scanning line L3a. As a result, the video is displayed vertically in the NV / (NV0
* HX) multiplied. The two FIFO memories 32
Since the image data is previously expanded in the vertical direction by HX times 2 and 324, the total vertical magnification MV is given by the following equation. MV = NV / NV0 (6)

Magnification factor MH for horizontal enlargement / reduction of image
Is the frequency fDCLK of the dot clock signal DCLK (FIG. 19) when writing the video data to the VRAM 212, and F
It is equal to the ratio fDCLK / fCLKO to the frequency fCLKO of the output clock signal CLKO (FIG. 21 (c)) when the video data is read from the IFO memories 322 and 324. As described in FIG. 21, the frequency fCLKO of the output clock CLKO
Is HX times the frequency fCLKI of the input clock signal CLKI, and the input clock signal CLKI is a constant value according to the frequency characteristics of the composite video signal VS. Therefore,
The horizontal magnification MH is given by the following equation (7). MH = fDCLK / fCLKO = fDCLK / (HX * fCLKI) (7)

Further, as can be seen from FIG. 12 (B),
The frequency fCLKI of the input clock signal CLKI is NH0 times the frequency fHSYNC of the horizontal synchronization signal HSYNC, and fHS
YNC and NH0 are constants. Also, the dot clock signal D
CLK has a frequency that is NH times the frequency fHSYNC of the horizontal synchronization signal HSYNC. Therefore, the above equation (7) can be rewritten as follows. MH = fDCLK / (HX * fCLKI) = fHSYNC * NH / (HX * fHSYNC * NH0) = NH / (HX * NH0) (8)

Equation (6) showing the vertical magnification MV and the horizontal magnification M
In the equation (8) indicating H, the three values that can be set from the CPU 202 are HX, NV, and NH, all of which are set values in the FIFO control unit 321. These three values HX, NV and NH are determined by the following equations, for example.

HX = RND (MV) (9a) NV = NV0 * MV (9b) NH = NH0 * MH * HX (9c) Here, the operator RND is rounded up to the right of the decimal point. Indicates an integer.

The expressions (9b) and (9c) are integers HX.
Since it holds even if any value is used as
It is also possible to determine the value of by an equation other than the equation (9a).

FIG. 24 (A) shows the video OR represented by the original composite video signal VS, and FIG. 24 (B).
Indicates a VRAM space for storing the enlarged / reduced image MR. Here, the maximum number of pixels in the horizontal direction is 780, the number of effective pixels is 640, the maximum number of lines in the vertical direction is 525, and the number of effective lines is 480. The image MR in the VRAM space is displayed as it is on the color CRT 300 or the color liquid crystal display 302. Therefore, the vertical magnification MV and the horizontal magnification MH are equal to the ratio of the size of the video display window set on the display device and the size of the original video OR. The CPU 202 calculates the magnifications MV and MH from the size of the video display window set on the display device, and further calculates (9) above.
Three values HX, NV, and NH are calculated according to a) to (9c) and set in the FIFO control unit 321.

As described above, in the above embodiment, the VRAM is
When performing DMA transfer of video data to the 212, the video can be enlarged or reduced at an arbitrary magnification. Further, since the display position of the image can be arbitrarily set by the address calculation unit 312, it is possible to display the moving image at any position on the display device at any magnification.

I. Modifications of DMA transfer circuit: Various modifications as described below are possible with respect to the configuration of circuits related to DMA transfer.

As the video memory, any RAM having two or more ports can be used. Also,
Actually, even if the RAM has only one port, it is also possible to use, as the video memory, one that realizes a function equivalent to that of the two-port RAM by switching the input / output of the port.

The present invention can be applied to the case of processing a video signal of another system such as a YUV signal of the NTSC system instead of the color signal (component video signal) of each color of RGB.

The present invention can also be applied to the case where compressed digital video data is expanded and written in the VRAM. In this case, the DMA controller 220
Image data D between the A and D converter 222
S input port (written as "CD-ROM")
Then, the digital video data from the image decompression unit may be input.

Address A given by the above equation (4)
As the circuit for calculating D2, various configurations other than the above-described embodiment can be considered. For example, the DMA controller 220
Similar results can be obtained by replacing the adder inside with a subtracter or changing the order of addition.

The multiplier 338 shown in FIG. 13 is replaced with an adder and a count-up counter, and the addition address ADA stored in the addition address value storage unit 332.
It is also possible to add D by the number of vertical counts VCNT of the vertical counter unit 334.

As shown in FIG. 25, PL in FIG.
It is also possible to replace the L circuit 328 with the 1 / N frequency divider 329. The 1 / N frequency divider 329 is reset by the vertical synchronizing signal VSYNC, and after being reset, divides the dot clock signal DCLK into 1 / N to generate a line increment signal HINC. 1 like this
The use of the / N frequency divider 329 has an advantage that the jitter of the line increment signal HINC can be reduced as compared with the case where the PLL circuit is used.

FIG. 26 is an explanatory diagram showing the configuration and operation of a circuit for performing vertical enlargement and interpolation between scanning lines using three FIFO memories, and corresponds to FIG. As shown in FIG. 26C, this circuit includes three FIFO memories 421, 422, 423, three equivalent switches 431, 432, 433, two multipliers 441, 442, and an adder 450. Includes and. Figure 2
6 (a) and 6 (b), each period TT21, TT
In 22 and TT23, the video data for one scanning line is written in one FIFO memory, and the video data is read out from the other two FIFO memories. FIFO memory into which video data is written and FI from which video data is read
The FO memory is selected in a predetermined order. FIG. 26 (c)
Indicates the switch connection state in the first half of the third period TT23. At this time, the first FIFO memory 42
The image data of the first scanning line L1 read from the first scanning line L1 is multiplied by k1 by the first multiplier 441, and the image data of the second scanning line L2 read from the second FIFO memory 422 is the second data. It is multiplied by k2 in the multiplier 442 of. Two multipliers 4
Since the outputs of 41 and 442 are added by the adder 450,
In the first half of the period TT23, the output video data VDO output from the adder 450 is (L1 * k1 + L2 * k
2) (FIG. 26 (b)). Here, the coefficients k1 and k2
If both are set to 0.5, the output video data VDO in the first half of the period TT23 is data obtained by simply averaging the video data of the two scanning lines L1 and L2. k1 and k2 are 0
If set to an appropriate value, a weighted average can be obtained. In the latter half of the period TT23, the video data of the second scanning line L2 is output as it is as the output video data VDO.

Also, a FIF for enlarging the vertical direction
By providing a FIFO memory unit that functions similarly to the O memory unit 318 between the AD converter 222 and the color adjusting unit 320, the same effect regarding the vertical expansion and interpolation can be obtained. In this case, FIG. 12 (A)
The FIFO memory unit 318 is used as a circuit for adjusting the timing of data transfer without vertically expanding the video data VD.

In the present invention, the term "enlarge the image vertically" is not limited to the case of simply enlarging the image as shown in FIG. 21, but also the case of enlarging the image by interpolation in the vertical direction as shown in FIG. is doing.

It should be noted that instead of a plurality of FIFO memories, R
It is also possible to construct a circuit having a function equivalent to that of the FIFO memory unit by using another type of video data buffer such as AM. In general, a plurality of video data buffers and a buffer control circuit are provided, and the plurality of video data buffers are switched in a predetermined order by the buffer control circuit, whereby the function of the FIFO memory unit described above can be realized.

The function equivalent to that of the PLL circuit 325 of FIG. 12B is that the signal CLKO obtained by the PLL circuit 326 is input and frequency-divided and output at (1 / NH0) to output the horizontal synchronizing signal HS.
It can also be realized by using a circuit that resets with YNC. As described above, although a plurality of PLL circuits are used in FIG. 12B, an equivalent circuit can be realized by combining frequency divider circuits and the like.

The color adjusting section 320 shown in FIG. 5 may be configured as a circuit which receives the digital video signal DS as the YUV signal and performs the hue conversion, and then outputs the component video data VD as the RGB signal.

The DMA controller 22 shown in FIG.
0 part of the circuit (for example, the DMA address calculation unit 312 and the DMA control unit 316) is connected to the video accelerator 210
It is also possible to include in.

J. Second Embodiment: FIG. 27 is a block diagram showing the configuration of a computer system as a second embodiment of the present invention. This computer system is shown in FIG.
In the system in the first embodiment shown in FIG.
AM 213 is added. As will be described later, the DMA controller 220a is a modification of the internal configuration of the DMA controller 220 shown in FIG.

FIG. 28 is an explanatory diagram showing the correspondence relationship between the 2-port VRAM 212 and the mask data RAM 213.
As shown in FIG. 28A, the 2-port VRAM 212
Is a frame memory that stores 8-bit composite video data of each color of RGB for each dot of the screen of the display device (color CRT 300, liquid crystal display 302). Further, the mask data RAM 213 is an area (hereinafter, referred to as an area of the 2-port VRAM 212 in which a moving image is written).
This is a memory that stores 1-bit mask data for each dot, which represents a "moving image writing area". Also, FIG.
As shown in FIG. 8B, the 2-port VRAM 212 and the mask data RAM 213 are the DMA controller 220a.
Seen from the same address space.

Here, for simplicity, it is assumed that the color comparison signal CCMP is at the H level in the entire area of the moving image. In this case, moving image data is DMA-transferred to the 2-port RAM 212 in the area where the mask data is at the H level, and DMA transfer is prohibited in the area where the mask data is at the L level. As a result, the moving image portion in the area where the mask data is at the H level is displayed on the display device. On the contrary, in the area where the mask data is at the L level, the moving image is not displayed, but the background and the still image are displayed. The operation of displaying a moving image using such mask data will be described later.

FIG. 29 is a block diagram showing the internal structure of the DMA controller 220a. The DMA controller 220a is similar to the DMA controller 220 shown in FIG.
RAM switching unit 604 and 3-state OR gate 606
, An address switching unit 608 and two 3-state buffer circuits 612 and 614 are added, and the 2-input 3-state OR gate 610 is replaced by the 3-input 3-state OR gate 61.
It has a configuration replaced with 1.

The signal exchanged between the DMA controller 220a and the mask data RAM 213 is the address T
ADD, mask data TDATA, and control signal TCONT. The control signal TCONT is
It includes a write signal / TWR for mask data RAM 213 and an output enable signal / TOE. The write signal / TWR is output from the OR gate 606, and the output enable signal / TOE is output from the DMA control unit 316.

The address switching unit 608 uses the address MADD supplied from the DMA address operation unit 312 and CP.
This is a selector that selects one of the addresses MAINADD given from the CPU 202 via the U interface 310 as the address TADD given to the mask data RAM 213. The select signal / TCS instructing the switching in the address switching unit 608 is given from the RAM switching unit 604.

In addition to the select signal / TCS described above, the RAM switching section 604 uses the chip select signal / VC for permitting the operation of the write port of the 2-port VRAM 212.
S and a chip select signal / TCSS for permitting the writing of the mask data to the mask data RAM 213 are output. The RAM switching unit 604 uses the signals for these signals /
It has a latch for holding TCS, / VCS, / TCSS, and C via the CPU interface 310.
It holds the level of each signal designated by the PU 202.

The OR gate 606 is a mask data RAM.
213 chip select signal / TCSS and CP
Negative logical product of the write signal / MAINWR provided from the CPU 202 via the U interface 310 (A
ND) to generate a write signal / TWR to be given to the mask data RAM 213. As will be described later, the mask data is written in the mask data RAM 213 while the write signal / TWR is at the L level. The chip select signal / TCSS becomes L level when the video data is written in the 2-port VRAM 212, but at this time, CP
The write signal / MAINWR applied from U202 is kept at H level, and the write signal / TWR becomes H level,
Writing of data to the mask data RAM 213 is prohibited. In other words, the write signal / TWR becomes L level only when the mask data is written in the mask data RAM 213, and the writing is permitted.

The 3-state OR gate 611 masks the write signal / MWE output from the DMA control unit 316 with the mask data TDATA and the color comparison signal CCMP when transferring the video data to the 2-port VRAM 212. It is a gate. That is, the mask data TD
If both ATA and color comparison signal CCMP are at H level,
The write signal / MWE output from the DMA control unit 316 passes through the 3-state OR gate 611 as it is and is given to the 2-port VRAM 212 as the write signal / MWR. On the other hand, mask data TDATA and color comparison signal CCM
If at least one of the P's is at the L level, the write signal / MWE output from the DMA control unit 316 is in the 3-state O.
2-port VRAM 212 blocked by R gate 611
Write signal / MWR applied to is always maintained at the L level. Details of such an operation will be described later.

In FIG. 30, by using the mask data TDATA and the color comparison signal CCMP, the video data other than the designated color in the area of an arbitrary shape is DMA'd to the 2-port VRAM 212.
It is explanatory drawing which shows the method of transferring. Usually, the shape of the moving image MI represented by the video data MDATA is a rectangle.
The DMA address calculation unit 312 is a 2-port VRAM 21.
The address of the rectangular moving image MI in the two address spaces (that is, the space corresponding to the screen area of the display device) is calculated for each dot and given to the 2-port VRAM 212. This address MADD is the mask data RAM 21.
It is given to 3 at the same time. Therefore, the image data MDATA representing the rectangular moving image MI is 2-port VRA for each dot.
At the same time as being supplied to M212, the mask data TDATA of each dot is read from the mask data RAM 213 and input to the OR gate 611.

The value of the mask data TDATA stored in the mask data RAM 213 is the 2-port VRAM.
It is 1 (H level) for a region (moving image writing region) MR in which a moving image is to be written in the image space 212, and 0 (L level) for regions other than the moving image writing region MR. Since the moving image writing area in the 2-port VRAM 212 corresponds to the moving image display area in which a moving image is displayed on the display device, both the moving image writing area and the moving image display area will be referred to as “moving image display area” below. Call.

The OR gate 611 uses the mask data TDA.
The negative logical product (AND) of the inverted signal / TDATA of TA, the inverted signal / CCMP of the color comparison signal CCMP, and the write signal / MWE output from the DMA control unit 620 is taken, and the output / MWR is obtained. It is given to the 2-port VRAM 212. As a result, when both the mask data TDATA and the color comparison signal CCMP are at the H level, the 2-port VRA
Writing of the video data MDATA to M is permitted, and writing of the video data MDATA to the 2-port VRAM 212 is prohibited when at least one of the mask data TDATA and the color comparison signal CCMP is at the L level.

In the example of FIG. 30, the 2-port VRAM2
In the memory area adjacent to the moving image display area MR in 12,
Video data of the still images SIa and SIb is written by the video accelerator 210. Still images of notes are also written in advance in the moving image display area MR.
When such an image in the 2-port VRAM 212 is displayed on the display device, a state in which a moving image portion other than the designated color is moving is observed in the moving image display region MR behind the windows of the still images SIa and SIb. To be done. Since the moving image video data MDATA is transferred at high speed by DMA, the image in the moving image display area MR looks like actually moving.

If the distribution of the mask data TDATA is changed, the moving picture image data MD in the moving picture display area of any shape can be obtained.
It is possible to selectively transfer the ATA to the 2-port VRAM 212. It should be noted that the mask data TDATA can be restated as having a function of masking a part of the rectangular moving image MI. By changing the value of the address MADD and the distribution of the mask data TDATA, it is possible to arbitrarily change the position of the area where the moving image is displayed on the screen of the display device. Further, as described above, it is also possible to change the magnification of the moving image in the horizontal direction and the vertical direction in the moving image display area of an arbitrary shape at an arbitrary magnification.

K. Mask data writing process:
7 is a timing chart of a mask data write operation to the mask data RAM 213. Mask data RAM 21
The writing of the mask data into 3 is executed during the period in which the video accelerator 210 accesses the 2-port VRAM 212 (hereinafter, referred to as “still image period”). At the time of writing the mask data, the chip select signal / VCS for permitting the operation of the write port of the 2-port VRAM 212 is kept at the H level during the still image period, and the write operation to the 2-port VRAM 212 is prohibited. , DM
Output enable signal / T output from the A control unit 316
OE is kept at the H level to instruct the mask data RAM 213 that it is a data write operation. It should be noted that the 2-port VRAM2 is set by the chip select signal / VCS.
12 write operations are prohibited by the two RAMs 212,
Since 213 is mapped to the same address,
This is to prevent data from being erroneously written in the 2-port VRAM 212 when writing mask data in the mask data RAM 213.

When select signal / TCS applied to address switching unit 608 (FIG. 29) falls to L level, CP
The address MAINADD supplied from U202 is selected by the address switching unit 608 and the mask data RAM21
Given to 3. At this time, the mask data MAINDATA (= TDATA) output from the CPU 202 is also CP.
Mask data RAM2 via U interface 310
Given to 13. After that, chip select signal / TC
During the period when SS falls to L level, the OR gate 606 is opened, and the write signal / TWR is at L level, the mask data RAM 213 stores the mask data TDAT.
A is written.

In the moving image period (DMA transfer period), the mask data TDA is changed from the mask data RAM 213.
TA is read and used for masking the moving image described in FIG.

As described above, the mask data RAM 21
The process of writing the mask data TDATA in 3 is not a DMA transfer but a process executed by the CPU 202. Therefore, the mask data RAM 213 has a 2-port RA
The mask data TDATA may be directly written from the CPU 202 by connecting to the CPU bus 201 using M.

FIG. 32 is a flow chart showing the procedure of the mask data update processing. In step S1, the initial data of the mask data is written in the 2-port VRAM 212. Here, the initial data of the mask data refers to mask data written when the moving image MI is displayed for the first time, and is usually mask data indicating a rectangular moving image display area.

In step S2, the CPU 202 monitors whether or not the state of the moving picture window has been changed on the screen of the display device. The moving image window has the same meaning as the moving image display area on the screen, and is a 2-port VRAM2.
This corresponds to the moving image writing area in 12 image spaces.
The state of the movie window changes only when the size or position of the still image window that overlaps the movie window is changed, when the size or position of the movie window itself is changed, or when the movie window and still image window overlap. There are cases where the hierarchical relationship of is changed.

When the state of the moving image window is changed, the chip select signal / VCS is raised to the H level in step S3, and writing to the 2-port VRAM 212 is prohibited. In step S4, the CPU 202 writes new mask data in the mask data RAM 213 to update the mask data in the mask data RAM 213. In step S5, the chip select signal / VCS is lowered to the L level and the 2-port VRA
Writing of data to M212 is permitted.

As described above, when the position or shape of the moving picture window is changed by the user changing the moving picture window or the still picture window on the screen of the display device,
The mask data is updated each time. The mask data update process of FIG. 32 is realized by the CPU 202 executing a predetermined application program.

L. Outline of DMA transfer processing of moving image data: FIG. 33 is an explanatory diagram showing an image displayed on a display device (color CRT 300, liquid crystal display 302). On this screen, a moving image display area MR exists below the windows of the two still images SIa and SIb, and an image in which a moving image portion having a color other than the designated color is moving is displayed in the moving image display area MR. There is. The moving image data is DMA-transferred to the 2-port VRAM 212 at a rate of 30 frames / second (60 fields / second), for example. The operations of the DMA transfer processing along the vertical direction (on the Y1-Y2 line) and the DMA transfer processing along the horizontal direction (on the X1-X2 line) of FIG. 32 will be described below.

FIG. 34 is a timing chart showing the operation of vertical DMA transfer. Note that FIG. 34 corresponds to FIG.
The chip select signal / VCS
(FIG. 34B) and mask data TDATA (FIG. 34B).
It is the figure which added (i)). 2 for DMA transfer
Since the video image data MDATA is written in the port VRAM 212, the chip select signal / VCS is kept at L level. As described above, the mask data TDATA
(FIG. 34 (i)) and the color comparison signal CCMP (FIG.
(J)) is the H level portion, the moving image video data MDATA is written in the 2-port VRAM 212,
In the portion where at least one of the mask data TDATA and the color comparison signal CCMP is L level, the moving image data M
Writing of DATA is prohibited.

FIG. 35 is a timing chart showing a horizontal DMA transfer operation. FIG. 35 also shows the chip select signal / VCS (see FIG. 3) in the timing chart of FIG.
5 (b)) and mask data TDATA (FIG. 35 (i)).
It is the figure which added and.

FIG. 36 shows the portion A (mask data T
6 is a timing chart showing details of a portion including DATA and a step portion of a color comparison signal CCMP). Mask data TD
The write signal / MWR falls to the L level only while the ATA and the color comparison signal CCMP are both at the H level, and the video data MDATA is written to the 2-port VRAM 212 in response to this.

As described above, since the same address MADD (= TADD) is given to the 2-port VRAM 212 and the mask data TAM213 during the DMA transfer, the mask data TDATA corresponding to the dot position of the video data MDATA on the screen is read. It Then, in accordance with the levels of the mask data TDATA and the color comparison signal CCMP, the video data MDATA to the 2-port VRAM 212
Is controlled. Further, as described above, since the mask data TDATA is updated according to the position and shape of the moving picture window (moving picture display area), it is possible to display a moving picture of any shape at any position on the screen.

M. Third Embodiment: FIG. 37 is a block diagram showing the configuration of a computer system according to a third embodiment of the present invention. This computer system is similar to the system shown in FIG.
20 and a DOS display control unit 522 as a video data conversion unit are added.

The computer system of the third embodiment is
It operates under the control of two operating systems (hereinafter referred to as "OS"), and the 2-port VRAM 212 as the first video memory is the first OS (for example, MS-Win).
managed by dows (a trademark of Microsoft Corporation),
The VRAM 520 as the second video memory is the second OS.
(For example, MS-DOS (trademark of Microsoft Corporation)).

The formats of the video data stored in the two VRAMs 212 and 520 are different from each other as shown below. The video data stored in the 2-port VRAM 212 is bitmap data in which each color of RGB is represented by 8 bits for each dot of the display device (color CRT 300 and color liquid crystal display 302). VR
AM520 is a text VRAM and graphic VRA
Contains M and. When the image is a character, the text VRAM stores a character code indicating the character and attribute data indicating the attribute of each character (character color, reverse display, blink display, etc.). In the attribute data, for example, one of eight colors is designated by 3 bits as the color of the character. The graphic VRAM stores bitmap data representing the graphic for each dot. In the bitmap data of the graphic, 1 bit out of 8 colors may be designated by 3 bits, or 1 color out of 16 colors may be designated by 4 bits.

The DOS display control section 522 has the VRAM 52.
The video data stored in 0 to the 2-port VRAM 212.
It has a function as a video data conversion means for converting into a format of video data stored in. Specifically, DOS
The display control unit 522 serves as a character generator that converts a character code into bitmap data, an attribute generator that gives an attribute to a character, a color palette that converts the color of graphic data, and a video multiplexer that combines a character image and a graphic. It has the function of. The video data converted by the DOS display controller 522 is transferred to the 2-port VRAM 212 at high speed by the DMA controller 220a.

FIG. 38 shows a 2-port V from the VRAM 520.
5 is an explanatory diagram showing a data transfer path to a RAM 212. FIG. As shown in FIG. 38 (A), the video data stored in the VRAM 520 is converted in data format by the DOS display control unit 522 and is given to the DMA controller 220a. The DMA controller 220a transfers the video data supplied from the DOS display control unit 522 or the AD converter 222 to the 2-port VRAM 212 by the procedure described in detail in the first embodiment. The video data stored in the 2-port VRAM 212 is given to the display device. As shown in FIG. 38 (B), VR
The display area corresponding to AM520 is a 2-port VRAM2
It is preferably smaller than the display area corresponding to 12.
In this case, the video stored in the VRAM 520 is displayed on a part of the screen of the display device. Note that FIG.
The display area for the VRAM 520 as in (B) is MS
-It is called DOS-BOX in Windows.

In the third embodiment, the 2-port VRA is used.
Video data in M212 is a data format (data structure)
There is an advantage that the video data in the VRAM 520 different from each other can be transferred to the 2-port VRAM 212 at high speed by the DMA controller 220a while converting the data format. Further, since the data format conversion is performed by the DOS display control unit 522 which is hardware, C
The conversion can be performed at a higher speed than the conversion using the PU 202. Further, there is also an advantage that the above-mentioned enlargement / reduction can be performed on the image on the display screen of the VRAM 520.

In the third embodiment, two VRAMs are used.
Although 212 and 520 are managed by different OSs, the present invention is not limited to this, and the present invention can be applied when two or more VRAMs store video data in different data formats. is there.

In each of the above embodiments, the computer system having the video accelerator 210 has been described, but the present invention can be applied to a computer system not including the video accelerator.

[0162]

As described above, according to the invention described in claim 1, since the writing to the frame memory is controlled according to the comparison result of the color comparing means, only the desired color portion of the moving image is displayed. It can be transferred to the frame memory at high speed.

According to the invention described in claim 2, it is possible to write only the video portion outside the range of the predetermined chromaticity in the moving image in the frame memory.

According to the third aspect of the present invention, the desired chromaticity range can be set arbitrarily by setting the upper limit value and the lower limit value for the three primary color components of the video data.

According to the invention described in claim 4, when the components of the three primary colors of the moving image data are equal to the respective reference values, the writing to the frame memory is prohibited, and at least 1.
If one does not equal the reference value, then writing to the frame memory can be allowed.

According to the fifth aspect of the present invention, the moving picture image data writing to the frame memory is permitted or prohibited with a simple circuit structure as compared with the method of controlling moving picture image data having a large number of bits and addresses. You can

According to the invention described in claim 6, the level of the write signal can be easily adjusted.

According to the invention described in claim 7, since the write address is calculated by the arithmetic operation by the first arithmetic means and the second arithmetic means, the write address of the frame memory is calculated at high speed, Data can be transferred at high speed.

[Brief description of drawings]

FIG. 1 is a plan view showing a moving image to be transferred.

FIG. 2 is a histogram showing the brightness of each color obtained by color-separating the video data of the background of the moving image.

FIG. 3 is a chromaticity diagram showing a designated color area CA defined by an upper limit value and a lower limit value of RGB colors.

FIG. 4 is a block diagram showing a computer system as a first embodiment of the present invention.

FIG. 5 is a block diagram showing an internal configuration of a DMA controller 220.

FIG. 6 is a block diagram showing an internal configuration of a color comparison unit 550.

FIG. 7 is a block diagram showing an internal configuration of a color comparison circuit 554.

FIG. 8 is a plan view showing an image superimposed by the DMA transfer of the embodiment.

FIG. 9 is a timing chart showing a vertical DMA transfer operation.

FIG. 10 is a timing chart showing a horizontal DMA transfer operation.

11 is a timing chart showing details of a portion A in FIG.

FIG. 12 is a block diagram showing an internal configuration of a FIFO memory unit 318.

FIG. 13 is a block diagram showing the internal configuration of a DMA address calculation unit 312, a data output unit 314, and a DMA control unit 316.

FIG. 14 is an address map of the 2-port VRAM 212.

FIG. 15 is an explanatory diagram showing a correspondence relationship between a 2-port VRAM 212 and a screen.

FIG. 16 is a plan view showing a moving image area MPA on the screen of the color monitor.

FIG. 17 is an enlarged block diagram showing an address calculation unit 312 in the DMA controller 220.

FIG. 18 is a timing chart showing details of a DMA transfer operation.

FIG. 19 is a block diagram showing an internal configuration of a vertical counter section 334 and a FIFO control section 321.

FIG. 20 is an explanatory diagram showing a memory space of an odd line field and an even line field when performing interlaced scanning.

FIG. 21 is an explanatory diagram showing a vertical enlargement operation of an image.

FIG. 22 is an explanatory diagram showing a state of vertical enlargement and reduction of an image.

FIG. 23 is a timing chart showing a vertical reduction operation of an image.

FIG. 24 is an explanatory diagram showing how the image is scaled up / down in the vertical and horizontal directions.

FIG. 25 is a block diagram showing a circuit configuration when the second PLL circuit 328 is replaced with a 1 / N frequency divider.

FIG. 26 is an explanatory diagram showing a configuration and operation of performing interpolation between scanning lines along with vertical expansion using three FIFO memories.

FIG. 27 is a block diagram showing a computer system as a second embodiment of the present invention.

FIG. 28 is a 2-port VRAM 212 and mask data RA
Explanatory drawing which shows the structure of M213.

FIG. 29 is a block diagram showing an internal configuration of a DMA controller 220.

FIG. 30 is a 2-port VRAM 212 for converting video data MDATA in a display area having an arbitrary shape by using mask data.
Explanatory diagram showing a method of performing a DMA transfer to.

FIG. 31 is a timing chart of a mask data write operation to the mask data RAM 213.

FIG. 32 is a flowchart showing the procedure of mask data update processing.

FIG. 33 is an explanatory diagram showing an image displayed on a display device.

FIG. 34 is a timing chart showing the operation of vertical DMA transfer.

FIG. 35 is a timing chart showing a horizontal DMA transfer operation.

FIG. 36 is a timing chart showing details of a portion A in FIG. 35.

FIG. 37 is a block diagram showing the configuration of a computer system as a third embodiment of the present invention.

FIG. 38 is an explanatory diagram showing a transfer route of video data in the third embodiment.

FIG. 39 is a block diagram of a computer system using a conventional DMA controller.

FIG. 40 is a plan view showing an image superimposed by conventional DMA transfer.

[Explanation of symbols]

51R, 51G, 51B ... Video memory 52 ... Data bus 53 ... Address bus 54 ... Control bus 55 ... DMA controller 56R, 56G, 56B ... VRAM monitor 57 ... Control unit 59 ... CPU 80 ... Horizontal range 81 ... Vertical range 201 ... CPU Bus 202 ... CPU 204 ... RAM 206 ... ROM 208 ... I / O interface 210 ... Video accelerator 212 ... 2-port VRAM (frame memory) 213 ... Mask data RAM 214 ... DA converter 216 ... LCD driver 220 ... DMA controller 222 ... A-D converter 224 ... Video decoder 226 ... Video input terminal 228 ... Address bus 229 ... Data bus 230 ... Control bus 230 ... Control bus 300 ... Color CRT 302 ... Color liquid crystal display 310 CPU interface 312 ... DMA address calculation unit 314 ... Data output unit 316 ... DMA control unit 318 ... FIFO memory unit 320 ... Color adjustment unit 321 ... FIFO control unit (video data buffer control unit) 322, 324 ... FIFO memory (video data) Buffers 323a, 323b ... Toggle switches 325 ... PLL circuits (input clock generation means) 326 ... PLL circuits (output clock generation means) 327 ... PLL circuits (dot clock generation means) 328 ... PLL circuits (line increment signal generation means) 330 ... offset address storage unit 332 ... addition address value storage unit 334 ... vertical counter unit (scanning line number generation means) 336 ... horizontal counter unit 338 ... multipliers 340, 342 ... adder 360 ... control signal generation unit 362 ... bus control Control unit 364 ... Latch 402 ... Back porch storage unit 404 ... Comparator 406 ... Back porch counter 408 ... Vertical counter 410 ... Latch 421, 422, 423 ... FIFO memory 431, 432, 433 ... Switch 441, 442 ... Multiplier 450 ... Adder 460 ... Accelerator unit 462 ... CPU interface 470 ... Image processing unit 471 ... Data bus 472 ... Control bus 474 ... Image formation control section 510 ... PLL circuit 511 ... Waveform shaping section 520 ... VRAM 522 ... DOS display control section 550 ... Color comparison unit 552 ... Comparison value storage circuit 544 ... Color comparison circuit 544a ... Comparator 560 ... Window comparator 562, 564 ... Comparator 566 ... AND gate 570 ... NAND gate 604 ... RAM switching unit 606 ... OR gate 608 ... Address switching unit 610 ... 3-state OR gate 612, 614 ... 3-state buffer AD2 ... Address ADAD ... Addition address BG ... Background BP ... Back porch number BPC ... Count value CA ... Specified color range indicating color not to be transferred CCMP ... Color Comparison signal CLKI ... Input clock signal CLKO ... Output clock signal CNT ... Count value DCLK ... Dot clock signals DL, DLR ... Color lower limit value DU, DUR ... Color upper limit value FIS ... Field instruction signal HCNT ... Horizontal count HINC ... Line increment Signal HSYNC ... Horizontal sync signal HX ... Vertical magnification ratio INTACK ... Transfer enable signal L1-L3 ... Scan line MH ... Horizontal magnification MV ... Vertical magnification MADD ... DMA address MCONT ... Control signal MDATA ... Video image data MPA ... Video area FAD ... Offset address TADD ... Address of mask data RAM 213 TCONT ... Control signal TDATA ... Mask data VCNT ... Vertical address VD ... Component video data VS ... Composite video signal VSYNC ... Vertical sync signal WINT ... Interrupt signal WSYNC ... Word sync signal / DMAACK ... DMA enable signal / DMARQ ... DMA request signal / MWE ... write signal / MWR ... write signal / TCS ... select signal / TCSS ... mask data RAM213 chip select signal / VCS ... 2-port VRAM212 chip select signal fCLKI ... FIFO Frequency of input clock signal CLKI fCLKO ... Frequency of FIFO output clock signal CLKO fDCLK ... Frequency of dot clock signal DCLK fHINC ... Line ink Frequency of the rement signal HINC fHSYNC ... frequency of the horizontal sync signal HSYNC fVSYNC ... frequency of the vertical sync signal VSYNC

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location // H04N 9/75 G06F 15/64 310 450 E 15/66 450

Claims (7)

[Claims] 1. An apparatus for transferring video data to a frame memory, the frame memory storing video data of a video displayed on a display device, and a video video for supplying video video data transferred to the frame memory. Data supply means, a bus connected to the frame memory, a write address for writing the moving image video data in the frame memory, and the write address and the moving image data are output to the bus. Data transfer means, a color data memory for storing color data for defining a predetermined chromaticity range, the moving image data is compared with the color data, and a color comparison signal indicating the comparison result is generated. Color comparing means for controlling the writing of the moving image data to the frame memory according to the color comparing signal. Video data transfer apparatus comprising: a control means. 2. The video data transfer device according to claim 1, wherein the color comparison unit is configured to operate the frame memory when the chromaticity represented by the moving image data is within the predetermined chromaticity range. The color comparison signal is set to a first level that prohibits writing of the data, and if the chromaticity represented by the moving image data is outside the range of the predetermined chromaticity, writing to the frame memory is permitted. A video data transfer device comprising: color comparison signal setting means for setting the color comparison signal to the second level. 3. The video data transfer device according to claim 2, wherein the color data includes an upper limit value and a lower limit value of a video data component for each of the three primary colors RGB, and the color comparison signal setting. The means sets the color comparison signal to the first level when the components of the three primary colors represented by the moving image data are within the range between the upper limit value and the lower limit value, respectively. A video data transfer device comprising: means for setting the color comparison signal to the second level when at least one of the components of each color of the video data is outside the range between the upper limit value and the lower limit value. 4. The video data transfer device according to claim 2, wherein the color data includes reference values of video data components for three primary colors of RGB, and the color comparison signal setting unit includes the moving image. When the three primary color components of the video data are equal to the respective reference values, the color comparison signal is set to the first level, and at least one of the color components of the moving image data is different from the reference value. And a comparator for setting the color comparison signal to the second level. 5. The video data transfer device according to claim 1, wherein the data transfer means includes means for generating a write signal for permitting a write operation of the frame memory. The video data transfer device, wherein the writing control means includes writing signal adjusting means for adjusting the level of the writing signal according to the value of the color comparison signal. 6. The video data transfer device according to claim 5, wherein the write signal adjusting means sets the level of the write signal for each dot by a logical operation of the color comparison signal and the write signal. A video data transfer device having means for adjusting to. 7. The video data transfer device according to claim 1, wherein the data transfer unit calculates the frame memory and the write address when transferring the video image data. A first memory that stores an offset address value that indicates a start position of the moving image video data writing area in the frame memory; and an adjacent scanning line in the frame memory. A second memory for storing an added address value indicating a difference in address between the two; and a pulse number of the given horizontal synchronizing signal according to a vertical synchronizing signal and a horizontal synchronizing signal synchronized with the moving image data. Calculates a vertical address value equal to the product of the scan line number indicating the order of the scan lines specified by A first computing means, a horizontal counter for generating a horizontal address value on each scanning line in the moving image, the horizontal address value indicating a difference in address from a starting point of each scanning line to each pixel on each scanning line, and the offset address value. And a second arithmetic means for generating an address in the frame memory corresponding to the position of each pixel on each scanning line by adding the vertical address value and the horizontal address value. .