US7327371B2 - Graphic controller, microcomputer and navigation system - Google Patents
Graphic controller, microcomputer and navigation system Download PDFInfo
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- US7327371B2 US7327371B2 US10/716,459 US71645903A US7327371B2 US 7327371 B2 US7327371 B2 US 7327371B2 US 71645903 A US71645903 A US 71645903A US 7327371 B2 US7327371 B2 US 7327371B2
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- display
- image data
- information
- switching
- control device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
- G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
Definitions
- the present invention relates to technology effectively applied to a display control device that superimposes plural display faces to make display output, and more particularly to technology effectively used for a navigation system that displays a current position on a map.
- a display system that makes a display on a liquid crystal display panel and the screen of a CRT (Cathode Ray Tube) display device generally has a frame memory for storing image data containing pixel data of one screen.
- the display system makes display output as follows. While pixel data of display dots is written to the frame memory by using a drawing processor or the like, a display processing circuit successively reads the pixel data from the frame memory, converts the pixel data into display signals synchronously with vertical synchronous signals of the display device, and outputs the display signals.
- a frame memory as described above is provided for two screens so that drawing, and display output are performed through alternate switching between an area to which image data is written and an area from which image data is read for display output.
- some display systems having a frame memory capable of storing image data of two screens, if display contents do not need to be updated over plural display frame periods, without switching between a memory area to which image data is written and a memory area from which image data is read, display output is made by repeatedly using image data of an identical memory area.
- some display systems have an automatic switching function (automatic rendering mode) that, when it has become possible to update display contents at the termination of drawing processing for a next screen, automatically switches between a memory area to which image data is written and a memory area from which image data is read at appropriate timing.
- Such an automatic switching function is achieved, for example, in such a way that, when a drawing circuit fetches a predetermined command (instruction) indicating the termination of drawing processing for one screen, the drawing circuit notifies a display processing circuit of the termination of the drawing processing and the display processing circuit switches the memory area to a memory area from which image data is read in step with a synchronous signal of a display device (e.g., Non-patent Publication 1).
- a display device e.g., Non-patent Publication 1
- the inventor et al. had the idea of performing control in a manner that allocates image data storage areas of two pages on a display memory for each display plane and alternately switches between an image data storage area to which image data is written and an image data storage area from which image data is read for display output.
- various cases are considered such that it is useful to concurrently perform switching of the image data storage area with respect to a plurality display planes depending on display contents, or it is useful to perform switching at different timing for each of the display planes. Therefore, switching between the image data storage areas with uniform pattern cannot cover various display processings.
- An object of the present invention is to provide a display system that makes display output with plural display planes superimposed and is capable of eliminating display flicker without using a high-performance processor, and furthermore a display system that makes display output with plural display planes superimposed and is capable of versatile and redundancy-free, optimum switching between image data storage areas.
- Another object of the present invention is to provide a display system that is capable of switching between image data storage areas for display planes without heavily loading a CPU responsible for system control.
- attribute bits of a first instruction e.g., TRAP command
- display switching enable bits D 0 to D 7
- switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.
- switching to an image data storage area from which image data is read can be performed independently for each of the display planes, even in cases where the updating of display contents is performed differently for different display planes, redundancy-free, optimum switching can be performed. Since the switching setting of an image data storage area can be performed during image data expansion processing by use of a command interpreted and executed within a display control device, switching between image data storage areas can be controlled without increasing the load of the CPU and the like.
- FIG. 1 is a block diagram showing the overall configuration of a car navigation system to which the present invention is applied;
- FIG. 2 is a block diagram showing details of a display control device of FIG. 1 ;
- FIG. 3 is a diagram showing part of a drawing attribute register provided in a drawing unit of FIG. 1 ;
- FIG. 4 is a diagram showing the bit configuration of a TRAP control command of an embodiment
- FIG. 5 is a drawing showing a rough configuration of a display plane generating unit of FIG. 1 ;
- FIG. 6 is a time chart showing a first operation example of drawing processing and display switching
- FIG. 7 is a time chart showing a second operation example of drawing processing and display switching
- FIG. 8 is a time chart showing a third operation example of drawing processing and display switching.
- FIG. 9 is a block diagram showing another configuration of a display system to which the present invention is applied.
- FIG. 1 is a block diagram showing details of the whole and main portions of a car navigation system to which the present invention is applied. Although there is no particular limitation, in the drawing, plural circuit blocks within an area indicated by a reference numeral 2 are formed on one semiconductor board such as a monocrystalline silicon.
- the car navigation system of this embodiment comprises: a CPU (central processing unit) 1 that performs system control such as the determination of a current position based on position information from measuring apparatuses, processing for user input, and instructions for display output; a display control device 2 that performs drawing processing for writing image data to a display memory 4 according to drawing commands (drawing instruction) produced by the CPU 1 and display output processing for converting the image data read from the display memory 4 into display signals and displaying them; a memory 3 such as DRAM (Direct Random Access Memory) for providing a work memory space to the CPU 1 ; the display memory 4 such as DRAM for storing drawing commands and image data; a display device 5 such as a liquid crystal display; a nonvolatile memory 6 capable of holding data even after power off, such as a flash memory and a mask ROM (Read Only Memory) for storing an activation program and the like; a storage device 7 in which high-capacity storage media such as DVD (digital versatile disc) and hardware disk storing map data and the like are mounted; a system
- an input device such as a touch panel
- measuring apparatuses for measuring a current position such as a GPS (global positioning system) receiver, a direction measuring apparatus, and a gas rate sensor.
- GPS global positioning system
- the above-described map data may not be stored in the storage device 7 but be received from a computer network through communication means.
- the car navigation system of this embodiment is configured to make display output by superimposing plural display planes on which different types of displays such as, e.g., global map display, detailed map display, and menu display are made.
- the CPU 1 generates a series of drawing commands (hereinafter referred to as a display list) for expanding image data on the display memory 4 according to display contents for each of display planes, and stores the series of drawing commands in the display memory 4 .
- a drawing unit 20 of the display control device 2 reads drawing commands from the specified display list for execution and expands image data in a specified image data storage area of a display plane.
- a display list is followed by a TRAP command, which is a first instruction to indicate the end of drawing.
- the drawing unit 20 stops the drawing processing, outputs an interrupt signal to the CPU 1 , and waits for the next instruction to start drawing from the CPU 1 .
- image data storage areas are allocated for each of display planes, and image data of display planes corresponding to the image data storage areas is expanded by the drawing unit 20 .
- image data storage areas of plural pages e.g., 2 pages, 3 pages, etc.
- the drawing unit 20 has a drawing destination address register for storing the start address of an image data storage area of a drawing destination.
- the CPU 1 sets the start address of an image data storage area used for drawing from among image data storage areas of plural pages of plural display planes in the drawing destination address register to start drawing processing and thereby can expand image data in the image data storage area of a specified page of a specified display plane.
- FIG. 2 shows a more detailed block configuration of the display control device 2 .
- the display control device 2 comprises: a drawing unit 20 including a drawing processing unit 27 for interpreting and executing drawing commands, and a buffer unit 28 ; a CPU interface unit 21 , connected to the system bus 10 , through which data is inputted from and outputted to the CPU 1 ; a display unit 22 that reads pixel data of plural display planes from the display memory 4 , superimposes the pixel data on top of each other, converts the superimposed pixel data into video signals, and outputs the video signals; and a memory control unit 23 that controls the reading and writing of data from and to the display memory 4 .
- the display control device 2 is provided with: memory buses MDB and MAB over which data and addresses of the display memory 4 are transferred; CPU buses CDB and CAB over which data and addresses of the system bus 10 side are transferred; and a bus controller 25 that controls access of the blocks to these buses.
- the CPU interface unit 21 , the display unit 22 , and the memory control unit 23 input and output data through I/O buffers 26 a to 26 c , respectively, and the drawing processing unit 27 fetches drawing commands and writes pixel data through the buffer unit 28 .
- the display unit 22 is provided with a display plane generating unit 24 that reads image data of a specified page of each display plane from the display memory 4 in step with display timing, superimposes pixel data of different display planes in the display positions of the display planes, converts the pixel data into display signals, and outputs the display signals.
- the drawing processing unit 27 is provided with various registers such as a drawing attribute register (DAR) 201 , a control register, and a status register.
- DAR drawing attribute register
- FIG. 3 shows the format and partial functions of the drawing attribute register 201 provided in the drawing processing unit 27 .
- the drawing processing unit 27 sequentially reads and executes drawing commands from a display list for each display, generated by the CPU 1 and stored in the display memory 4 .
- the drawing processing unit 27 is internally provided with the drawing attribute register 201 as described previously, and the drawing commands are executed according to attribute contents set in the drawing attribute register 201 .
- Drawing commands decodable by the display control device 2 of this embodiment also contain a drawing attribute value. If an attribute value set in the drawing attribute register 201 and a drawing attribute value contained in individual drawing commands are different from each other, one of them is selected according to a value set in advance in a control register or the like not shown.
- the drawing attribute register 201 are provided with eight automatic switching mode enable bits D 00 to D 07 indicating whether to permit or not automatic display switching control for each of plural (e.g., eight) display planes.
- the automatic display switching control refers to control processing that, after the termination of drawing processing for one display plane, switches a page of an image data storage area from which image data is read for display output to the next page from the next display frame period, based on display switching enable bits D 0 to D 7 described later.
- the CPU 1 may directly write an attribute value, or the drawing processing unit 27 may write an attribute value by a control command interpretable to it.
- the above-described automatic switching mode enable bits D 00 to D 07 may be included in, for example, a display register provided in the display unit 22 , or the drawing processing unit 27 or a setting register external to the display unit 22 .
- FIG. 4 is a diagram showing the bit configuration of a TRAP control command for specifying the termination of drawing processing for one display plane.
- a display list stored in the display memory 4 includes not only drawing commands for drawing lines and polygons but also a control command for writing values to the drawing attribute register 201 , a control command for terminating drawing, and other control commands.
- the TRAP command specifies the termination of processing of a display list generated for each display plane.
- the drawing processing unit 27 sets a predetermined bit of a control register for controlling the operation of, e.g., the drawing processing unit 27 at “0” to stop the operation of the drawing processing unit 27 , sets a predetermined bit of the status register at “1” to output an interrupt signal to the CPU 1 , and thus notifies the CPU 1 of the termination of the drawing processing.
- a drawing attribute part of the TRAP command for terminating drawing processing is provided with display switching enable bits D 0 to D 7 for switching an image data storage area from which image data is read of each display plane to the next page.
- the display switching enable bits D 0 to D 7 are used to control switching between image data storage areas of display planes.
- FIG. 5 is a drawing showing a rough configuration of the display plane generating unit 24 included in the display unit 22 .
- the display plane generating unit 24 is provided with: one display synthesizing unit 241 that processes pixel data to obtain an image with images of plural display planes superimposed; and plural groups (e.g., eight) of display plane processing units respectively provided correspondingly to plural display planes.
- Each display plane processing unit includes: pixel data buffers (line buffers) 242 A; buffer control units 242 B; selection circuits 243 ; display address registers 244 ; and selection signal generation state machines 245 as first registers.
- the display synthesizing unit 241 based on information about a blend ratio of pixel data of display planes set in an attribute register not shown and a vertical position relationship among the display planes, performs operations for superimposing pixel data inputted from plural pixel data buffers 242 A and outputs the superimposed pixel data.
- the outputted pixel data is converted into analog display signals before being outputted to the display device 5 , so that display output is made in a form that superimposes plural display planes in a predetermined position.
- the blend ratio of one to zero produces display output that wholly hides a lower plane by an upper plane.
- the blend ratio of, e.g., three to one produces display output that brings a lower plane into a slight transparent view. It may be selected which of logical operations such as OR, AND, and Ex-OR should be used for image superimposing.
- the pixel data buffers 242 A are buffer memories sized to be capable of storing a fraction of, e.g., pixel data of one display line.
- the buffer control units 242 B count high-frequency clock signals internally generated synchronously with a vertical synchronous signal VSYNC of the display device 5 , read pixel data in a display position of a corresponding display plane from the display memory 4 so that the pixel data is outputted to the display synthesizing unit 241 at timing appropriate for the display position, and store the pixel data in the pixel data buffers 242 A for output.
- the display address registers 244 each store the start addresses (display information) of image data storage areas of plural pages for a corresponding display plane. When the number of display planes changes or the size of a display plane is changed, the start addresses of image data storage areas changed accordingly are written to the display address register 244 s by the CPU 1 . Preferably, the values of the display address registers 244 are updated on the falling edge of a vertical synchronous signal VSYNC of the display device 5 .
- the selection circuits 243 selectively feed one of plural start addresses stored in the display address registers 244 to the buffer control units 242 B according to a display destination selection control signal described later. Based on the start address, the buffer control units 242 B can read image data of any of plural pages of image data storage areas.
- the selection signal generation state machines 245 point to one of image data storage areas of plural pages allocated for a corresponding display plane. At timing (e.g., on the falling edge of the synchronous signal VSYNC) synchronous with the vertical synchronous signal VSYNC of the display device 5 , a signal indicating a page of an image data storage area used at that time is outputted to the selection circuits 243 . This signal serves as a display destination selection control signal of the selection circuits 243 .
- the state machines 245 receive a bit of a corresponding display plane of the display switching enable bits D 0 to D 7 of the TRAP command, and when its value is “1”, cause the state to transition to point to the next page; when “0”, cause no state transition to continue to point to the same page as a previous one. Pages pointed to are shifted in the same order as a page order in which drawing processing is performed.
- the above-described display switching enable bits D 0 to D 7 are sent from the drawing unit 20 to the display unit 22 over signal lines L 0 and inputted to the selection signal generation state machines.
- the state machines 245 can consist of, e.g., a shift register and logical circuits for identifying signals and performing other operations.
- the selection signal generation state machine 245 of the display plane causes transition, and pages of the display plane are switched synchronously with the vertical synchronous signal VSYNC.
- image data is read from one of image data storage areas of plural pages associated with individual display planes and subjected to display output processing, and whether or not a page for display output in the next display frame is switched, based on the display switching enable bits D 0 to D 7 of the TRAP command, is determined for each of display planes so that page switching control can be performed independently for each of the display planes.
- FIGS. 6 to 8 are time charts of first to third examples for explaining drawing processing and display switching timing.
- VSYNC designates a vertical synchronous signal of the display device 5 .
- FIGS. 6 to 8 it is assumed that image data storage areas of two pages are allocated per display plane.
- the setting of switching to a page from which image data is read for display output is performed independently for each of display planes by a TRAP command executed at the termination of drawing of any one display plane.
- actual switching to the page from which image data is read is performed at timing synchronous with the vertical synchronous signal VSYNC of the display device 5 .
- display output processing is performed for an image data storage area of “ADR11” in which drawing has already terminated.
- display output processing is performed for the image data storage area of “ADR10” in which drawing terminated previously.
- Such a control pattern that performs page switching setting for display frames in which drawing has terminated is effectively applied when the display is to be updated immediately after the termination of drawing.
- page switching setting is not performed at the termination of drawing of the first display plane “0”, and at the termination of drawing of the second display plane “1”, page switching setting of 0-th and first display planes is performed.
- Such a control pattern is useful for concurrent switching of the displays of plural display planes.
- page switching setting is performed for display planes in which drawing has terminated.
- the time chart shows a case where drawing processing of plural display planes terminated during the period of one display frame T 1 .
- display output by input of analog video signals generally requires image data storage areas of three pages.
- the display system of this embodiment can perform page switching control without problem also in cases where image data storage areas of different pages are allocated for different display planes, such as image data storage areas of two pages allocated for a display plane for displaying graphic images having been subjected to drawing processing, and image data storage areas of three pages allocated for a display plane for video output.
- the load on the CPU 1 is not increased to control display switching.
- display switching control not using drawing commands requires that the CPU 1 controls which display planes are to be subjected to display switching at each termination of drawing processing of one display list, so that the load on the CPU 1 increases.
- the setting of switching to a page from which image data is read is performed by a TRAP command indicating the termination of drawing processing
- the same switching setting may be performed by other commands and dedicated control commands.
- the drawing attribute register 201 is provided with automatic switching mode enable bits D 00 to D 07 for deciding the validity of display switching enable bits D 0 to D 7 of a TRAP command.
- the automatic switching mode enable bits D 00 to D 07 may not be used so that the setting of switching to a page from which image data is read is performed by only the display switching enable bits D 0 to D 7 of a TRAP command.
- the display switching enable bits D 0 to D 7 of a TRAP command may not be used so that display switching setting is performed by only the automatic switching mode enable bits D 00 to D 07 of the drawing attribute register 201 .
- page switching setting may be automatically performed for display planes with automatic switching mode enable bits D 00 to D 07 set at enable “1”, at the termination of drawing.
- display planes with which the display switching enable bits D 0 to D 7 and the automatic mode enable bits D 00 to D 07 correspond are fixed in advance.
- a setting register for setting a correspondence relationship between the bits and plural display planes may be provided and the correspondence relationship may be changed dynamically or statically.
- FIG. 9 shows another configuration of a display system to which the present invention is applied.
- the display control device 2 is configured with one chip, as shown in FIG. 9 , a microcomputer 100 with the CPU 1 , the drawing unit 20 , and the display unit 22 disposed on one chip may be mounted in a car navigation system.
- the semiconductor memory 3 and the display memory 4 to provide working areas of the CPU 1 may be configured with one memory without being separate from each other.
- the drawing unit 20 is shown as image data generating means, various configurations may be applied, such as an MPEG (Motion Picture Experts Group) decoder 29 that can expand image data of plural video pictures in image data storage areas of plural display planes.
- MPEG Motion Picture Experts Group
- page switching setting for each display plane may be performed independently at the termination of expansion processing of image data of one screen.
- the present invention is effective because page switching timing is different depending on display planes.
- the present invention is not limited to the car navigation system.
- the present invention can be widely used for various display systems such as a handy navigation system and PDA (Personal Digital Assistant).
- display switching is performed only for display planes whose display contents have been updated, or display switching is performed at the same time for two or more related display planes, so that versatile and redundancy-free, optimum display switching control can be performed.
- display switching setting can be performed using commands executed by a display control device, display switching can be performed at appropriate timing without increasing the load of a CPU responsible for system control.
Abstract
Description
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002-361971 | 2002-12-13 | ||
JP2002361971A JP4050605B2 (en) | 2002-12-13 | 2002-12-13 | Display control device and navigation system |
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US20040113904A1 US20040113904A1 (en) | 2004-06-17 |
US7327371B2 true US7327371B2 (en) | 2008-02-05 |
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US10/716,459 Active 2025-05-07 US7327371B2 (en) | 2002-12-13 | 2003-11-20 | Graphic controller, microcomputer and navigation system |
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US (1) | US7327371B2 (en) |
JP (1) | JP4050605B2 (en) |
TW (1) | TW200416666A (en) |
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WO2005105449A1 (en) * | 2004-05-04 | 2005-11-10 | Sys Tec, S.R.L. | Method and machine for aligning flexographic printing plates on printing cylinders |
JP4862470B2 (en) * | 2006-04-21 | 2012-01-25 | ヤマハ株式会社 | Image processing device |
US8463424B2 (en) * | 2007-11-07 | 2013-06-11 | Research In Motion Limited | System and method for displaying address information on a map |
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- 2003-12-10 TW TW092134848A patent/TW200416666A/en unknown
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JP4050605B2 (en) | 2008-02-20 |
TW200416666A (en) | 2004-09-01 |
US20040113904A1 (en) | 2004-06-17 |
JP2004191818A (en) | 2004-07-08 |
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