JPH1011047A - Picture display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the processing load of a host device and to reduce the data amount of a frame memory at the time of displaying a picture while changing the size of the picture. SOLUTION: A picture display controller 20 is constituted of a frame memory control part 210, the frame memory 220 of a plane for pixel display size 221 and a plane for display data 222 and a pixel display size changing circuit 230. A host device 10 delivers picture data before a size changing and a size changing instruction to the device 20. The control part 210 performs the coordinate transformation of the picture data according to the size changing instruction and stores the picture data in the corresponding position of the plane 222 as they are and stores display size data in the same position of the plane 221. Then, both planes 112, 222 are read out by being synchronized with each other and the display size changing circuit 230 changes the picture data according to the display size data every pixel and transmits them to a display device 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display control device for controlling display of a display device, and more particularly to an image display control device effective for displaying an image at an arbitrary size at a high speed.

[0002]

2. Description of the Related Art Conventionally, in an image processing system, when changing the size of original image data and displaying the image data on a screen, a higher-level device uses a software or hardware to convert the image data whose size has been changed from the original image data. The image data is generated and provided to the image display control device, and the image display control device writes the image data after the size change into the frame memory and outputs the image data to the display device.

FIG. 6 shows an example of a conventional configuration of this type of image processing system. In the figure, reference numeral 10 denotes a host device such as an image processing device, 20 denotes an image display control device, 30 denotes a display device, and the image display control device 20 includes a frame memory control unit 2.
10, the frame memory 220. The host device 10 generates image data whose size has been changed from the original image data by software or hardware, and provides the image data to the image display control device 20. The image display control device 20 writes the resized image data into the frame memory 220 by the frame memory control unit 210,
The image data is directly output to the display device 30 and displayed.

FIG. 7 shows a specific example of processing, in which 700 is original image data, 710 is image data obtained by enlarging the size of “A” in the image data by two times vertically and horizontally, 720 is the contents of the frame memory 220, 730 is the output of the display device 30. Here, since “I” in the original image data 700 does not change the size, the image display control device 20 can write the image data into the frame memory 220 as it is. It needs to be stored in the memory 220. In this case, conventionally, the host device 10 generates image data 710 by resizing the “A” in the original image data 700 by software or hardware, and generates the image data 710.
Had to give. Then, the image display control device 20 writes the image data 710 into the frame memory 220 (720) and outputs the image data 710 to the display device 30 as it is (730).

[0005]

In the prior art,
In a case where the original image data is resized and displayed on the display device, processing for obtaining image data corresponding to the display size is required by software or hardware in a higher-level device, and the burden on the higher-level device increases. there were. In addition, when the display size is large, the data amount also becomes large, and it takes time to write and read image data to and from the frame memory in the image display control device, which has been a bottleneck in high-speed display.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the load on a host device when displaying an original image data with its size changed, and to speed up the display by eliminating the increase in the writing / reading time of a frame memory. Another object of the present invention is to provide an image display control device capable of improving the processing performance of the entire image processing system.

[0007]

According to the present invention, there is provided an image display control apparatus comprising: a frame memory control unit for controlling writing / reading of a frame memory; a first plane (display data plane) for storing image data; A frame memory including a second plane (plane for pixel display size) for storing pixel display size data, and image data read from the first plane are stored in the second plane.
A display size changing unit that changes the size according to the display size data read from the plane is provided.

The frame memory control unit receives a change instruction based on the original image data and the size before the size change from the host device, converts the original image data according to the size change instruction, and copes with the first plane. The original image data is stored as is at the pixel position to be displayed, the display size data is stored at the same corresponding pixel position on the second plane, and the contents of both planes are read out synchronously during display. The display size changing unit has, for example, a hardware logic circuit configuration, and for each pixel position, converts the image data read from the first plane at high speed in accordance with the display size data read from the second plane. Change the size and send it to the display device.

Thus, when the original image data is resized and displayed, the host device only needs to supply the original image data to the image display control device as it is, and is released from the resizing process. Also in the image display control device, the original image data can be basically written or read from the frame memory as it is, so that the data amount does not increase and high-speed display is possible.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a higher-level device (CPU) such as an image processing device, reference numeral 20 denotes an image display control device according to the present invention, and reference numeral 30 denotes a display device. The image display control device 20 includes a frame memory control unit 210, a frame memory 220, and a pixel display size changing circuit 230. The frame memory 220 further includes a pixel display size plane 221 and a display data plane 222. The pixel display size plane 221 is a frame memory indicating the display size of each pixel represented by the display data plane 222.

FIG. 2 shows a pixel display size plane 2.
21 shows the relationship between 21 and the display data plane 222. In the present embodiment, the pixel display size plane 221 has a configuration of one bit per pixel. When this bit is “0”, the corresponding pixel of the display data plane 222 is displayed as it is, and when this bit is “1”. Indicates that the corresponding pixel of the display data plane 222 is enlarged and displayed twice vertically and horizontally based on the pixel. For example, the pixel P of the pixel display size plane 221
When _6,0 is "1", the corresponding pixel P _6,0 of the display data plane 222 is enlarged to twice vertically and horizontally, the pixel P _6,0 with pixels P _7,0, P _6,1, P _7,1 is filled. Here, P _{i, j} means a pixel at the x position i and the y position (line) j. Pixels P _12,0 , P
_{12, 1,} is the same for P _12,2. Accordingly, the pixels P _6,0 , P _4,2 ,
When _P8,2 is "1", the display data plane 222 is displayed with the area surrounded by the thick line painted out. On the other hand, the pixels P _12,0 , P _12,1 ,
Pixel display size plane 221 corresponding to P _12,2
The pixel is "0", in this case, the pixel P _12,0, P _12,1, P _12,2 is displayed as it is.

Next, the operation of FIG. 1 will be described with reference to FIG. FIG. 3 shows a specific processing example of one embodiment of the present invention, where 300 is the original image data, 310 is the output image data of the host device 10, 320 is the contents of the pixel display size plane 221 and 330 is the display data The plane content 340 is a display output of the display device.

When the image size is changed, the host device 10 instructs the image display control device 20 of the changed image display size, and the image data is stored regardless of the image size change.
The original image data 300 is directly used as the image display control device 20
(310). Therefore, the host device 10 does not need to generate the image data after the size change (for example, 710 in FIG. 7), and the processing of software and the like is reduced.

The image display control device 20 sets the pixel display size data in the pixel display size plane 221 of the frame memory 220 as indicated by 320 based on the image data 310 and the image display size instruction by the frame memory control unit 210. Then, the image data is written into the display data plane 222 as indicated by 330.

Here, pixel display size plane 2
The contents 320 of 21 can be easily obtained by performing coordinate conversion of each pixel position of the character “A” in the image data 310 that is the same as the original image data 300 based on the image display size. Contents 33 of display data plane 222
0 is “I” of the image data 310 for the character “I”.
Is written as it is, and the character “A” is obtained by writing “A” of the image data 310 at the pixel position after size conversion obtained by coordinate conversion. That is,
The content 330 of the display data plane 222 has the same data amount as the original image data 300, and the content 320 of the pixel display size plane 221 has a data amount equal to or less than the original image data 300, The data write / read time of the memory 220 can be made substantially constant irrespective of whether or not the image display size has been changed.

At the time of display, the pixel display size data 320 of the pixel display size plane 221 and the image data 330 of the display data plane 222 in the frame memory 220 are converted by the frame memory control unit 210.
Synchronously, for example, the data is read out serially from left to right and from top to bottom, and is input to the pixel display size conversion circuit 230. In the pixel display size conversion circuit 230, when the pixel of the pixel display size data 320 is “0”,
The content of the corresponding pixel of the image data 330 is output to the display device 30 as it is, and the pixel display size data 32 is output.
When the pixel of “0” is “1”, the contents of the corresponding pixel of the image data 330 are doubled vertically and horizontally and displayed on the display device 3.
Output to 0. As a result, in the example of FIG. 3, as shown at 340, “A” is doubled vertically and horizontally in the original image data 300, and “I” is displayed as it is.

FIG. 4 shows a pixel display size changing circuit 23.
An example of a hardware logical configuration of 0 is shown. For convenience, FIG. 4 shows each plane 221 and 222 of the frame memory 220.
Is assumed to be composed of 16 pixels. Further, it is assumed that the pixel display size data and the image data are composed of one bit per pixel, and that the pixel display size is changed twice and vertically and horizontally.

In FIG. 4, reference numeral 401 denotes a pixel display size data input line from the pixel display size plane 221; 402, an image data input line from the display data plane 222; and 403, a display data output line to the display device 30. is there. An X coordinate counter 404 operates in synchronization with the reading of both planes 221 and 222 of the frame memory 220, and a decoder 405 for the counter 404.
410 is an AND circuit, 411, 415, 421, 430
Is an OR circuit. 416 and 423 are decremented (D
EC) circuit. Reference numerals 412 _{0 to} 412 ₁₅ denote AND circuit groups for one run in the X direction. One input side of each AND circuit is individually connected to each output of the decoder 405, and the other input side has a common output of the OR circuit 411. Connected to. Similarly, 413 ₀ to 413 ₁₅ are latch circuit groups for one line,
Reference numerals 414 _{0 to} 414 ₁₅ denote AND circuits for one line. Input side of the latch circuits 413 _{0 to 413 15} are individually connected to an AND circuit group 412 _{0-412 15,} the output side, respectively, are individually connected to the one input of the AND circuits 414 _{0 to 414 15} You. AND circuit group 414 _{0 to} 414
On the other input side of ₁₅ , each output of the decoder 405 is individually connected. Reference numeral 422 denotes a one-pixel latch circuit.

Display size data and image data of each pixel are sequentially read from the pixel display size plane 221 and the display data plane 222 of the frame memory 220 from left to right and from top to bottom.
2 to the pixel display size changing circuit 230. Here, the image data of the input line 402 is sent to the output line 403 through the OR circuit 430 as it is. At the same time, the pixel display size data of the input line 401 and the image data of the input line 402 are input to the AND circuit 410.

Now, the pixel display size plane 22
1 and the contents of the display data plane 222 are as shown in FIGS. (C) is the output of the display device 30 at this time.

The reading of the frame memory 220 proceeds to the j-th line, and the pixel P at the i-position (x-position) of the j-line
The display size data of _{i, j} and the image data are input lines 401,
Suppose that it has arrived at 402. Pixel P on input line 402
The image data “1” of _{i and j} passes through the OR circuit 430 and is output from the output line 403. Frame memory 22
The reading of 0 and the screen display of the display device 30 are synchronized,
“1” is displayed at the coordinates (i, j) on the display screen. At the same time, the pixel display size data “1” and the image data “1” of the pixels P _{i, j} on the input lines 401 and 402 are input to the AND circuit 410, and the AND circuit 410 outputs “1”. At this time, the count value of the X coordinate counter 404 is "i", the AND circuit 410, OR circuit 411, latch circuit 413 via the AND circuit 412 _{i i}
Becomes “1”. And circuit 410, OR circuit 4
The latch circuit 422 is set to “1” via 21.

Next, the display size data and the image data of the pixel P _{i + 1, j at} the position (i + 1) next to the j-th line arrive at the input lines 401 and 402. The image data of this pixel P _{i + 1, j} is “0”. However, at this time, "1" is held in the latch circuit 422, and the latch circuit 42
2 is output to the output line 403 through the OR circuit 430. Thus, even if the image data of the current pixel P _{i + 1, j} is “0”, “1” is displayed at the coordinates (i + 1, j) on the display screen of the display device 30. The “1” output of the latch circuit 422 is input to the OR circuit 411. At this time, the count value of the X coordinate counter 404 is “i + 1”, and the OR circuit 411 and the AND circuit 412
_The latch circuit 413 _{i + 1} becomes “1” via _{i + 1} . Latch circuit 413 _i remains still "1". Note that the latch circuit 422 is thereafter operated by the decrementer 42
3. Return to "0" via OR circuit 421.

Next, the reading of the frame memory 220 proceeds to the (j + 1) line, and the display size data and the image data of the pixel P _{i, j + 1} at the i position of the (j + 1) line arrive at the input lines 401 and 402. Suppose you did. The image data of this pixel P _{i, j + 1} is “0”. However, this time, "1" is held within the latch circuit 413 _i, also, the count value of the X coordinate counter 404 is "i". Therefore, the output of the AND circuit 414 _i becomes “1”, and “1” is output to the output line 403 via the OR circuits 415 and 430. Thus, the current pixel P _{i, j + 1}
Is "0", "1" is displayed at the coordinates (i, i + 1) on the display screen of the display device 30. Note that the latch circuit 413 _i thereafter operates the decrementer 41
6, the OR circuit 411, through the AND circuit 412 _i returns to "0".

Next, the (i + 1) next to the (j + 1) line
The display size data and the image data of the pixel P _{i + 1, j + 1 at} the position arrive at the input lines 401 and 402. The image data of the pixel P _{i + 1, j + 1} is also “0”. However, at this time, “1” is held in the latch circuit 413 _{i + 1} ,
The count value of the X coordinate counter 404 is “i + 1”
It is. Therefore, the output of the AND circuit 414 _{i + 1} becomes “1”, and “1” is output to the output line 403 via the OR circuits 415 and 430. Thus, even if the image data of the current pixel P _{i + 1, j + 1} is “0”, “1” is displayed at the coordinates (i + 1, j + 1) on the display screen of the display device 30. Thereafter, the latch circuit 413 _{i + 1} returns to “0” via the decrementer 416, the OR circuit 411, and the AND circuit 412 _{i + 1} .

As described above, according to the logical configuration of FIG.
When the contents of the pixel display size plane 221 and the display data plane 222 are as shown in FIGS. 5A and 5B,
The display on the display device 30 is as shown in FIG. That is, the image of the pixel P _{i, j} is enlarged and displayed twice vertically and horizontally.

For the sake of convenience, FIG. 5 focuses on one pixel P _{i, j} , but in the same manner, by the logical configuration of FIG. 4, for example, the contents of the pixel display size plane 221 and the display data plane 222 are changed to 320 in FIG. , 330, it can be easily analogized that the output content of the display device becomes 340 in FIG.

Although the image display control device of the present invention has been specifically described based on the illustrated embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say, For example, in the embodiment, the case has been described where the display size corresponds to 16 dots in the X direction and the pixel display change size corresponds to twice the height and width. However, the present invention is not limited to this embodiment, and the capacity of the frame memory is not limited. , And the display change size can correspond to a plurality of vertical and horizontal sizes. As an example, in FIG.
13 is provided for two lines and the latch circuit 422 is provided for two pixels, and by additionally providing an AND / OR circuit or the like corresponding thereto, it is possible to cope with a change in the display size by three times in the vertical and horizontal directions.

[0028]

As described above, according to the image display control apparatus of the present invention, it is possible to reduce the processing load on software or the like in the host apparatus when the original image data is resized and displayed. it can. In addition, since the original image data is written to the frame memory as it is, even if the size is changed, the increase in the time for writing / reading to the frame memory is almost negligible, and the display can be speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a plane for pixel display size and a plane for display data according to the present invention.

FIG. 3 is a specific example for explaining the operation of FIG. 1;

FIG. 4 is a logic configuration diagram of an embodiment of a pixel display size changing circuit of FIG. 1;

FIG. 5 is a specific example for explaining the operation of the pixel display size changing circuit of FIG. 4;

FIG. 6 is a conceptual diagram of a conventional image display control device.

FIG. 7 is a specific example for explaining the operation of FIG. 6;

[Explanation of symbols]

 Reference Signs List 10 host device 20 image display control device 210 frame memory control unit 220 frame memory 221 pixel display size plane 222 display data plane 230 pixel display size change circuit 30 display device

Claims (3)

[Claims] 1. An image display control device for changing the size of original image data and displaying the image data on a display device, comprising: a first plane for storing image data and a second plane for storing display size data of the image data. And a coordinate conversion of the original image data, and stores the original image data at the corresponding pixel position of the first plane, and stores the display size data at the corresponding pixel position of the second plane. When displaying, the frame memory control unit reads out the image data of the first plane and the display size data of the second plane synchronously, and reads the image data read from the first plane from the second plane. A display size changing unit that changes the size according to the read display size data and outputs the size to the display device. apparatus. 2. The image display control device according to claim 1, wherein the frame memory control unit receives original image data before size change and a size change instruction from a higher-level device,
The original image data is coordinate-transformed in response to the size change instruction, the original image data is stored at a corresponding pixel position on the first plane, and display size data is stored at a corresponding pixel position on the second plane. An image display control device characterized by storing. 3. The image display control device according to claim 1, wherein the display size changing unit is configured by a hardware logic circuit, and the image data read from the first plane is provided for each pixel position. And changing the size in accordance with the display size data read from the second plane.