JP2000250510A - Display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently read a display data out of a storage device and to display them on a display device. SOLUTION: The display controller is equipped with a storage control part 8 which stores a frame buffer with a high-color-resolution pixel group as image data requiring high color resolution and a low-color-resolution pixel group as an irreducible pixel group needed to constitute an image of image data as a background capable of being displayed with low color resolution, displays pixels in order on the screen of the display device when the high-color-resolution pixel group is read out, and expands the color resolution of image data to the same color resolution with the high-color resolution pixel group and puts together the expanded low-color-resolution pixel group and high-color-resolution pixel group when the low-color-resolution pixel group is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display control device, and more particularly, to an LCD used in an information processing device.
The present invention relates to a display control device for performing display control on a screen of a display device such as a display device.

[0002]

2. Description of the Related Art FIG. 18 is a block diagram of a general display control device, which is shown together with its peripheral devices. The display control device 1 connects a display device 2 such as an LCD, a frame buffer 3 as a storage device for storing display data, and a host bus 4 to each other. Data can be exchanged with the CPU.

The display control device 1 also includes a display timing control unit 5 for controlling display timing, and temporarily stores display data read out from the frame buffer 3, and outputs a first input data from a FIFO (first FIFO). -in f
an irst-out) unit 6, a display interface 7 for converting display data sent from the FIFO unit 6 into display data corresponding to the display device 2 and generating control timing, and a storage control unit 8 for controlling the frame buffer 3. And a host interface 9 for controlling data exchange between the host bus 4 and the display control device 1.

[0004] In FIG. 18, reference numerals 10 to 15 indicate the flow of signals. Reference numeral 10 denotes a flow of display coordinates flowing from the display timing control unit 5 to the storage control unit 8, and the display coordinates represent coordinates on the screen of the display device 2.
Expressed by (X, Y). Reference numeral 11 denotes a flow of transmission of display data.
It flows toward the IFO unit 6. Reference numeral 12 denotes an address flow for the upper CPU to access the frame buffer 3 through the host bus 4. 13 is the upper CPU
2 shows the flow of display data when the frame buffer 3 is accessed through the host bus 4. Reference numeral 14 denotes a frame when the storage control unit 8 performs read / write / display.
This is a flow of addresses performed on the buffer 3. Reference numeral 15 denotes a flow of display data when the storage controller 8 accesses the frame buffer 3 at the time of writing / reading / display.

Next, the flow of display data at the time of write / read / display will be described. The time of writing means the time when display data transmitted from the host CPU is written into the frame buffer 3. The time of reading means the time when display data read from the frame buffer 3 is transmitted to the host CPU. The display time is a time when the display data read from the frame buffer 3 is displayed on the screen of the display device 2.

At the time of writing, display data is supplied from the host CPU via the host bus 4 to the display controller 1 together with the address (flow 12) (flow 13).
Via the host interface 9 and the storage controller 8 inside the display control device 1, the data is stored in the frame buffer 3 by the address (flow 14) and the write data (flow 15).

At the time of reading, the address given by the address (flow 12) via the host bus 4 is
The frame buffer 3 is transmitted by the address (flow 14) via the host interface 9 and the storage controller 8.
, The display data corresponding to the address is read from the frame buffer 3, and the display data (flow 1
5) is given to the host CPU via the storage controller 8 and the host interface 9 (flow 13).

At the time of display, when the display timing control unit 5 gives the display coordinates (flow 10) to the storage control unit 8, the storage control unit 8 gives the corresponding address (flow 14) to the frame buffer 3, and The display data corresponding to the address is read from the unit 8 (flow 15), and stored in the FIFO unit 6 via the storage control unit 8 (flow 1).
1). The display data stored in the FIFO unit 6 is transmitted to the display interface 7 at the timing requested by the display interface 7 (that is, the timing corresponding to the display device 2).
And the display interface 7 reads F
The display data from the I / O unit 6 is converted into a format corresponding to the display device 2, supplied to the display device 2 together with a control signal, and scanned and displayed on the screen of the display device 2.

FIG. 19 is a block diagram showing the configuration of the storage control unit. In the figure, reference numeral 16 denotes a read / write access request from the host bus 4 to the frame buffer 3 and a read / write access request from the display timing control unit 5. An arbitration unit that arbitrates requests according to priority. Reference numeral 17 denotes an access type signal which is the arbitration result, and reference numeral 18 denotes a frame buffer 3
, A buffer timing generator 19 for generating a control signal for 3, 20 a frame corresponding to the display coordinates (flow 10) from the display timing controller 5.
An address calculation unit that calculates the address of the buffer 3 according to (Equation-1).

A = (W * Y + X) * b / w (Equation-1) A (Address): Address W (Width): Number of dots in the width of the display screen b (bits per pixel): Bit per pixel w (word) ): Data width of frame buffer X, Y: Display coordinates As described above, there are three types of operations of the storage control unit 8: upper CPU write, upper CPU read, and display data read. Is performed on the frame buffer 3 in accordance with the above request. Numeral 16 arbitrates a write / read access request from the host CPU via the host bus 4 and a display data read request from the display timing control unit 5, and permits access to a higher priority one (priority is displayed. Data requests are usually set above.) The result of the permission is the access type signal 17.
The buffer address generator 18 selects either the address transmitted from the host interface 9 or the output of the address calculator 20, and the buffer timing generator 19
Generates an upper CPU write / read or display read cycle.

At the time of upper CPU write, data transmitted from the host interface 9 is directly provided to the frame buffer 3 as display data, and at the time of upper CPU read, display data from the frame buffer 3 is transmitted to the host via the host interface 9.・ Returned to the bus 4 and when reading display data, the frame buffer 3
Display data from the FIFO controller 6 via the storage controller 8
(Streams 15, 11).

[0012]

SUMMARY OF THE INVENTION The above conventional frame
The buffer memory map configuration is such that all pixels are the same bpp
(Bits per pixel: the number of bits per pixel), so that it is designed to have a uniform bpp regardless of the screen configuration. However, for example, as in the example of the display screen of the information processing apparatus shown in FIG. 20, a complex image requiring many bpp (such as a photographic image) (hereinafter, referred to as multi-bpp data) is displayed. Even if there is a mixed area with an area where a monotonous image (referred to as small bpp data in this specification) is displayed, the area is not distinguished. It is necessary to store the entire bpp in the area that requires the most bpp.

For example, if the screen size is 640 × 480 dots,
If the ratio of the photographic image area to the entire screen is 20%, the bpp in the photographic image part is 16, and the other is 8, the required information amount per frame required for display and to be read is: , (Equation-2). Required information amount = 640 x 480 x (16 x 0.2 + 8 x 0.8) = 2949120 bits ... (Equation-2) On the other hand, in the above conventional case, it is set to the area that requires the most bpp The amount of read information that is actually read is as shown in (Equation 3).

Read information amount = 640 × 480 × 16 = 4915200 bits (Equation-3) From these two equations, as shown in (Equation-4), the information read for display is: It can be seen that there is a 40% redundancy. Redundancy = (amount of read information−amount of required information) / amount of read information = 0.4 (Equation-4) The redundant portion of such information read accesses the frame buffer (frame buffer) 3 for display. The frequency is increased, the required size of the frame buffer 3 and the current consumption are increased, and the access from the host CPU competes with the read for display, and the waiting ratio is increased, so that the performance of the entire system is reduced. Causing the problem.

[0015]

According to the present invention, there is provided a display control apparatus comprising: reading means for reading image data stored in a storage device; and display means for displaying the read image data on a screen of a display device. Stores a high color resolution pixel group, which is image data requiring high color resolution, and a low color resolution pixel group, which is the minimum necessary pixel group for image data that can be used as background image data that can be displayed at low color resolution. When the high-resolution pixel group is read, the reading unit sequentially reads the pixels, displays the pixels on the screen of the display device by the display unit, and reads the low-resolution pixel group. Expands the color resolution so that the image data has the same color resolution as the high color resolution pixel group, and the display means, when the reading means reads the high color resolution pixel group, displays the pixel on the display device. It is displayed above, when reading the low color resolution pixel group by combining the low color resolution pixel group has been extended and high color resolution pixel group, and the like are displayed on the screen of the display device.

In this case, a register for storing the display coordinates on the screen of the display device for displaying the high color resolution pixel group and a register for displaying the low color resolution pixel group when the display coordinate of the register is reached. It is preferable to include a register switching unit for switching from displaying the low color resolution pixel group to the high color resolution pixel group. Also, a flag indicating that a high color resolution pixel group should exist in the low color resolution pixel group was stored in the storage device, and the flag was recognized while the low color resolution pixel group was being displayed. In such a case, it is preferable to provide a flag switching unit for switching from displaying the low color resolution pixel group to the high color resolution pixel group. In this case, in the low color resolution pixel group, the continuous number data in which the high color resolution pixels continue is stored in the storage device, and when the flag is recognized while the low color resolution pixel group is being displayed, It is preferable to include a continuous number switching means for switching from displaying the low color resolution pixel group to the high color resolution pixel group and displaying the high color resolution pixel group only for pixels corresponding to the continuous number data.

Further, a plurality of indexed high color resolution pixel groups and index data of the high color resolution pixel group are arranged in the low color resolution pixel group and stored in a storage device. While displaying the flag, when the flag is recognized, when switching from the display of the low color resolution pixel group to the high color resolution pixel group, an index switching means for reading out the corresponding index and displaying the high color resolution pixel group is provided. May be provided. Also, a color number table indicating the number of colors of the high color resolution pixel group, and when the low color resolution pixel group is being displayed, when the flag is recognized, switching from the low color resolution pixel group display to the high color resolution pixel group is performed. The image processing apparatus may further include a color number switching unit that reads out the corresponding color number and displays a high color resolution pixel group corresponding to the color number.

Further, there is provided an operation speed control means for changing the operation speed of the storage device according to the number of colors of the pixel group,
In the case of a high color resolution pixel group, it is preferable to increase the operation speed and increase the readout timing.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited by this. In the following description, drawings that are common to the description of each embodiment will be appropriately referred to in the description of each embodiment. First Embodiment FIG. 1 is a block diagram illustrating a storage control unit according to a first embodiment. It should be noted that, in contrast to the conventional case of FIG.
A data conversion unit 22 that processes data to the FO unit 6, H output from the address conversion unit 21 to the data conversion unit 22
The CS signal 23 is added. The other configuration is the same as that of the conventional case, and the description is omitted.

FIG. 2 is a block diagram of the address conversion unit according to the first embodiment. In the figure, 24-27 are registers for specifying a rectangular area for displaying multi-bpp data.
(Y0) and (X1, Y1) mean upper left and lower right coordinates, respectively. 28 is the display coordinates (X,
Y) is a comparison part for comparing 24-27 with 30, and 30 is a multiple bp
p HC address calculation unit that calculates the address of the data storage area (high-color address calculator / Hi
gh Color Address Calculator), 29 is an address selector (Address Selector) for switching between the address from the address calculator 20 and the address calculated by the HC address calculator 30.

FIG. 3 is a block diagram of the data conversion unit according to the first embodiment. In FIG. 3, reference numeral 31 denotes a bit for extracting one pixel from the display data from the frame buffer when the display data is small bpp data. Selector, 32 is the extracted small bp
A data extension unit 33 for extending the bits of the p data to multi-bpp data, 33 is an output from the data extension unit 32,
This is a data selection unit that switches the raw data of the display data from the buffer 3.

FIG. 4 is an explanatory diagram of the data storage state of the frame buffer according to the first embodiment. For the sake of simplicity, the description describes the multi-bpp data as 16 bpp and the rest as 8 bpp. However, this value is not limited to this, and other combinations of the number of bits are free. is there. As shown in FIG.
Divide and store bpp data and small bpp data. FIG.
During the display access, the comparison unit 28 displays the display coordinates (X,
Y) is compared with the contents of the registers 24 to 27, and if it is determined that the current display data read is a multi-bpp display rectangular area, the HCS signal 23 is output. The HC address calculation unit 30 calculates a corresponding address in the multi-bpp data storage area from the display coordinates (X, Y) and (X0, Y0) according to (Equation 5), and passes the calculated address to the address selection unit 29. At the address 29, the output of the HC address calculator 30 is output when the HCS signal 23 is output, and otherwise, the display address output from the address calculator 20 is output as it is.

A = (X−X 0) + (Y−Y 0) × W) × b / w (Equation-5) A (Address): Multi-bpp data address W (Width): Number of horizontal dots of multi-bpp data b (bits per pixel): bit per pixel of multiple bpp data w (word): data width of frame buffer X, Y: display coordinates FIG. 5 is a conceptual diagram of the function of the data conversion unit, and is mainly a bit selection unit. 3 illustrates the functions of the data extension unit 31 and the data extension unit 32.
In the figure, the frame buffer has a structure in which data for a plurality of pixels (Pixels) is collected and becomes the same size as one multi-bpp data, as shown in (1) for multi-bpp data and (2) for low bpp data. 3 is supplied to the bit selection unit 31. The bit selection unit 31 extracts the data one pixel at a time,
Give to 2. The data extension unit 32 extends the number of bits by shifting the bits as in (3). That is, between R2 and G5, between G3 and B4, and B3
Are added to the end of the character string to extend the number of bits of the display data.

FIG. 6 is an explanatory diagram of the conversion operation of the data conversion unit. As shown in the figure, data in which both high bpp data and low bpp data are mixed is
Is converted to As described above, by expanding the bit in the low bpp data area and using the data as it is in the high bpp data area, it is possible to mix high bpp data and low bpp data in the screen Becomes

The display operation other than the data conversion of the first embodiment is the same as that of the prior art, so that the description is omitted. According to the first embodiment, for example, it is effective for use in which a high-definition image is displayed in an internal window with a monotonous OS screen as a background, and only data in an area for displaying multi-bpp data is effective. Is stored in the frame buffer as a group of many bits, and in the other areas, only the minimum necessary bits are stored, so that images with different color resolutions can be mixed on the same screen in the conventional case. In comparison, it is possible to realize the frame buffer size with no waste.

As a result, the required frequency of frame buffer access is reduced, so that the device can reduce the power consumption due to the access. In addition, when display data is read / written from the host CPU, the display data competes with read for display, and the waiting ratio is reduced, so that the display performance of the apparatus can be improved.

Second Embodiment FIG. 7 is a conceptual view of the display according to the second embodiment, and explains the differences from the first embodiment. In the first embodiment, as shown in FIG. 7, a non-rectangular multi-bpp data area such as overlapping rectangles could not be handled. In the second embodiment, this was improved. The difference is that shapes other than such rectangles can be handled.

FIG. 8 is a block diagram showing a storage control unit according to the second embodiment. This storage control unit 8 is different from the first embodiment in that the HCS signal 34 is different from 23,
It differs in that it is connected to 22 to 21, and 19, and accordingly, the operations of 22, 21, and 19 also differ. Details will be described later. In the drawings, the same components are denoted by the same reference numerals.

FIG. 9 is a configuration diagram of an address conversion unit according to the second embodiment. The address conversion unit 21 stores a start X register (S
tartX) 35, a start Y register (StartY) 36 indicating the minimum Y coordinate of the multi-bpp area, and registers 24 to 27 of upper left and lower right coordinates of the rectangle of the first embodiment.
Has been deleted.

FIG. 10 is a configuration diagram of a data conversion unit according to the second embodiment. The data conversion unit 22 is different from the first embodiment in that a comparator 37 is added to the output destination of the bit selection unit 31, and the HCS signal 34 is output from the comparator 37. . In the second embodiment, a small bp in the frame buffer 3
In the p data area, specific data (for example, all bits are 1) is previously written at coordinates corresponding to the multi-bpp area. The comparator 37 monitors the output value of the bit selection unit 31 while the screen of the display device 2 is being displayed, and outputs the HCS signal 34 when the output value matches the specific data. The address conversion unit 21 receives this and outputs an address according to (Equation-6).

Address = ((X−StartX) + (Y−StartY) × W) × b / w (Equation-6) A (Address): Address W (Width): Number of horizontal dots of multiple bpp data b ( bits per pixel): bit per pixel w (word): data width of the frame buffer X, Y: display coordinates
Upon receiving the S signal 34, a read cycle for the frame buffer 3 is started. The address given to the frame buffer 3 at this time is the output of the address conversion unit 21 described above.

Thereafter, the frame buffer 3 outputs corresponding data accordingly. This is the pixel information of the multi-bpp data corresponding to the coordinates. Other operations are the same as those in the conventional case, and the description is omitted. According to the second embodiment, a multi-bpp data area that is not rectangular cannot be handled in the first embodiment. However, the present invention is improved to handle such a non-rectangular shape. become.

Third Embodiment FIG. 11 is a configuration diagram of a data conversion unit according to a third embodiment. This data converter 22 differs from the second embodiment in that a counter 38 is added. In the third embodiment, specific data (for example, all bits are 1) is written at coordinates corresponding to the high bpp area in the small bpp data area in the frame buffer 3, and further, at the next coordinate, Write the number of consecutive pixels in the multi-bpp data area on that display line. In the data conversion unit 22, the comparator 37 monitors the output value of the bit selection unit 31 during display, and when the output value matches the specific data, the counter 37 latches the next data. To instruct.
The counter 38 counts the latched data as 1 for each pixel.
The HCS signal 34 is output until the value is reduced to zero. The address conversion unit 21 receives this and outputs an address according to (Equation-6) shown in the second embodiment.

The buffer timing generator 19 is H
Upon receiving the CS signal 34, a read cycle for the frame buffer 3 is started. At this time, the frame
The address given to the buffer 3 is the output of the address conversion unit 21. And the frame buffer 3
In response, the corresponding data is output. This is the pixel information of the multi-bpp data corresponding to the coordinates.

The data converter 22 receives the data,
The data is supplied to the FIFO unit 6. The other operations are the same as those in the conventional case, and a description thereof will be omitted. As described above, in the second embodiment, in order to confirm whether or not a region is a multi-bpp region, all pixels are also displayed by reading all the pixels overlapping with the multi-bpp region of the small bpp region. In this embodiment, only two pixels (specific data + the number of continuous pixels) at which multi-bpp starts for each display line are read.

For this reason, according to the third embodiment, the required access frequency of the frame buffer 3 is reduced, so that the device consumes less power due to the access. In addition, when the display data is read / written from the host CPU, the display data competes with the read for display, and the waiting ratio is reduced, so that the display performance of the apparatus can be improved.

Fourth Embodiment FIG. 12 is a configuration diagram of a data conversion unit according to a fourth embodiment. This data conversion unit 22 is different from the third embodiment in that an index latch 39 is added.
The difference is that the output is connected to the data selection unit 33 and is also supplied to the address conversion unit 21.

FIG. 13 is a configuration diagram of an address conversion unit according to the fourth embodiment. This address translator 21
4, a start X register (StartX) 35 indicating the minimum X coordinate of the multi-bpp area, a start Y register (StartY) 36 indicating the minimum Y coordinate of the multi-bpp area, and an index for displaying a plurality of multi-bpp data. And an offset table 40 for performing coordinate conversion based on.

FIG. 14 is a conceptual view of the display according to the fourth embodiment. As shown in the figure, the high-brightness color storage area is divided into several parts in the frame buffer, an index is assigned to each area, and multiple multi-bpp data areas are displayed on the display screen based on the index. . Hereinafter, the display procedure will be described. In the frame buffer 3, a data storage area corresponding to each multi-bpp data index is prepared, and the start position is stored in the offset table 40.

Then, the small bpp in the frame buffer 3
In the data area, specific data (for example, all bits are 1) is written to coordinates corresponding to the multi-bpp area, and the next coordinate is the number of consecutive pixels of the multi-bpp data area on the display line, Write the index. The index is the index number of the multi-bpp area. In the data conversion unit 22, the comparator 37 monitors the output value of the bit selection unit 31 during display, and instructs the counter 38 to latch the next data when the output value matches the specific data. , Index latch 39
To instruct data latching one after another. Counter 38
Then, the latched data is reduced by one for each pixel, and the HCS signal 34 is output until it becomes zero. During this time, the index latch 39 keeps holding and outputting the latched value as an index. Then, the address converter 21 receives the HCS signal 34 and outputs an address according to (Equation-7).

Address = ((X−StartX) + (Y−StartY) × W) × b / w + O (Equation-7) W (Width): The number of horizontal dots of multi-bpp data b (bits per pixel): Bit Per pixel w (word): data width of frame buffer X, Y: display coordinates O (offset Index): data storage position with respect to index After that, the buffer timing generator 19
Upon receiving the S signal 34, a read cycle for the frame buffer 3 is started. At this time, the address given to the frame buffer 3 is
1 output. Further, the frame buffer 3 outputs corresponding data accordingly. This is the pixel information of the multi-bpp data corresponding to the coordinates.

Then, the data conversion section 22 receives the data and supplies the data to the FIFO section 6. The other operations are the same as those in the conventional case, and a description thereof will be omitted. Therefore, up to the third embodiment,
Although only a single multi-bpp area is displayed, in the fourth embodiment, a plurality of multi-bpp data areas can be displayed.

Fifth Embodiment FIG. 15 is a configuration diagram of an address conversion unit according to a fifth embodiment. This address converter 21 is different from the fourth embodiment in that a depth table 41 is added inside. The depth table 41 stores the color depth indicating the number of bpp corresponding to the index. In the following description, FIG. 12 used in the description of the fourth embodiment will be appropriately referred to.

In this embodiment, the frame buffer 3
In the small bpp data area, the specific data (for example, all bits are 1) is written at the coordinates corresponding to the multi bpp area, and the next coordinate is the number of continuous pixels of the multi bpp data area in the display line. , And writes an index to the next coordinates. The index is the index number of the multi-bpp area. In the data converter 22,
The comparator 37 monitors the output value of the bit selection unit 31 during display, and when the output value matches the data, instructs the counter 38 to latch the next data, and instructs the index latch 39 to successively latch the data. Of the latch. The counter 38 decrements the latched data by one for each pixel until the HCS signal 3
4 is output. During this time, the index latch 39 keeps holding and outputting the latched value as an index.
The address conversion unit 21 receives the HCS signal 34 and
8) Output the address according to.

Address = ((X−StartX) + (Y−StartY) × W) × b (I) / w + O (I) (Equation-7) W (Width): number of horizontal dots of multi-bpp data b ( I) / (bits per pixel Index): the number of bpp corresponding to the index w (word): the data width of the frame buffer X, Y: the display coordinates O (offset Index): the data storage position for the index , HC
Upon receiving the S signal 34, a read cycle for the frame buffer 3 is started. At this time, the address given to the frame buffer 3 is
1 output. The frame buffer 3 outputs corresponding data accordingly. This is the pixel information of the multi-bpp data corresponding to the coordinates.

The data converter 22 receives the data,
The data is supplied to the FIFO unit 6. The other operations are the same as those in the conventional case, and a description thereof will be omitted. Therefore, in the fourth embodiment, even when displaying a plurality of multi-bpp regions, the respective bpp numbers must be the same, but according to the fifth embodiment, a plurality of multi-bpp regions are displayed. The data area can be displayed with different bpp numbers.

Sixth Embodiment FIG. 16 is a block diagram showing a storage control unit according to a sixth embodiment. The storage control unit 8 has a configuration in which a clock driver 42 for controlling a clock frequency to the buffer timing generator 19 is added to the configuration of the first embodiment described with reference to FIG. The color depth information from the address conversion unit 21 is input to the clock driver 42.

FIG. 17 is a time chart showing the operation of the sixth embodiment, in which (1) shows a normal operation timing as a comparative example, and (2) shows a timing chart of the sixth embodiment. The operation timing is shown. As shown in (1), in the normal operation timing, the clock supplied to the buffer timing generator 19 is constant whether reading small bpp data or reading large bpp data.

However, as described above, according to the present invention, since the data in the small bpp area is expanded and used, the read data from the frame buffer at one time is the data in the multiple bpp area. Corresponds to several times the number of pixels. Conversely, this can reduce the speed of the frame buffer by a factor of several when accessing small bpp areas.

For this reason, in the present embodiment, as shown in (2), the clock signal is output from the clock driver 42, and the clock driver 42 responds to the color depth signal from the address conversion unit 21 by The clock frequency is dynamically changed as shown in (Equation 9). Clock frequency = reference clock / (bpp of the area / maximum bpp) (Equation-9) As a result, the data rate from the frame buffer 3 decreases at a rate of (bpp of the area / maximum bpp). Is the reciprocal (maximum bp
p / bpp of the area).
As a result, as shown in (2), the speed of the data sent to the FIFO unit 6 becomes constant, and the display is not hindered.
Can be displayed.

The other operations are the same as those in the above-described embodiments, and a description thereof will be omitted. . According to the sixth embodiment, the frame buffer 3 can be operated at the minimum necessary speed by the number of bpp for each part of the screen. A reduction in power consumption can be expected when the display control device is created with elements that are proportional to the operation speed.

[0052]

As described above, according to the display control device of the present invention, the frequency of the required storage device is reduced, so that the device can obtain the effect of reducing the power consumption due to the access. . Also, when the display data is read / written from the host CPU, it competes with the read for display, and the waiting ratio is reduced.
The effect of improving the display performance of the device is obtained. Therefore, an effect is obtained that the display data in the storage device can be read out and displayed on the display device more efficiently than before.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a storage control unit according to a first embodiment;

FIG. 2 is a configuration diagram of an address conversion unit according to the first embodiment;

FIG. 3 is a configuration diagram of a data conversion unit according to the first embodiment;

FIG. 4 is an explanatory diagram of a data storage state of a frame buffer according to the first embodiment;

FIG. 5 is a conceptual diagram of a function of a data conversion unit.

FIG. 6 is an explanatory diagram of a conversion operation of a data conversion unit.

FIG. 7 is a conceptual view of display according to the second embodiment.

FIG. 8 is a block diagram illustrating a storage control unit according to the second embodiment;

FIG. 9 is a configuration diagram of an address conversion unit according to the second embodiment;

FIG. 10 is a configuration diagram of a data conversion unit according to the second embodiment;

FIG. 11 is a configuration diagram of a data conversion unit according to the third embodiment;

FIG. 12 is a configuration diagram of a data conversion unit according to a fourth embodiment;

FIG. 13 is a configuration diagram of an address conversion unit according to a fourth embodiment;

FIG. 14 is a conceptual view of display according to the fourth embodiment.

FIG. 15 is a configuration diagram of an address conversion unit according to the fifth embodiment;

FIG. 16 is a block diagram illustrating a storage control unit according to a sixth embodiment.

FIG. 17 is a time chart showing the operation of the sixth embodiment;

FIG. 18 is a block diagram of a display control device.

FIG. 19 is a block diagram of a conventional storage control unit.

FIG. 20 is an explanatory diagram of a data storage state of a conventional frame buffer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Display control device 2 Display device 3 Frame buffer 8 Storage control unit 16 Arbitration unit 18 Buffer address generator 19 Buffer timing generator 20 Address calculation unit 21 Address conversion unit 22 Data conversion unit

Claims (7)

[Claims] An image requiring a high color resolution is provided in a display control device having reading means for reading image data stored in a storage device and display means for displaying the read image data on a screen of a display device. A high-resolution pixel group, which is data, and a low-resolution pixel group, which is the minimum pixel group required for image formation, are stored in a storage device, and read out image data as background that can be displayed at a low color resolution. The means reads out the high color resolution pixel group in order when the pixel group is read out and displays the pixels in order on the screen of the display device by the display means, and reads out the image data when the low color resolution pixel group is read out. The color resolution is extended so as to have the same color resolution as the group, and the display means, when the reading means reads the high color resolution pixel group, displays the pixel on the screen of the display device, and performs the low color separation. A display control device, wherein when an active pixel group is read, an extended low color resolution pixel group and a high color resolution pixel group are combined and displayed on a screen of a display device. 2. The register according to claim 1, wherein the register stores display coordinates on the screen of the display device for displaying the high color resolution pixel group, and the display coordinates of the register are displayed while the low color resolution pixel group is being displayed. A display switching device for switching the display of the low color resolution pixel group to the high color resolution pixel group. 3. The low color resolution pixel group according to claim 1, wherein a flag indicating that a high color resolution pixel group should exist is arranged in the low color resolution pixel group and stored in a storage device. A display control device, further comprising: a flag switching unit for switching from displaying a low color resolution pixel group to a high color resolution pixel group when the flag is recognized. 4. The low color resolution pixel group according to claim 3, wherein the continuous color number data in which the high color resolution pixels continue is arranged in the low color resolution pixel group and stored in a storage device. When the flag is recognized, a continuous number switching means is provided for switching from displaying the low color resolution pixel group to the high color resolution pixel group, and displaying the high color resolution pixel group only for pixels corresponding to the continuous number data. Display control device. 5. The storage device according to claim 3, wherein a plurality of indexed high color resolution pixel groups and index data of the high color resolution pixel group are arranged in the low color resolution pixel group. If the flag is recognized while the low color resolution pixel group is being displayed, when switching from the low color resolution pixel group display to the high color resolution pixel group, the corresponding index is read and the high color resolution pixel is read. A display control device comprising: index switching means for displaying a group. 6. A color number table indicating the number of colors of a high color resolution pixel group according to claim 3, 4, or 5, wherein a flag is recognized during display of the low color resolution pixel group. When switching from the display of the low color resolution pixel group to the high color resolution pixel group, there is provided a color number switching means for reading out the corresponding color number and displaying the high color resolution pixel group according to the color number. Display control device. 7. An image processing apparatus according to claim 1, further comprising an operation speed control unit for changing an operation speed of the storage device according to the number of colors of the pixel group. A display device wherein the operation speed is increased to increase the read timing.