JPS6267632A - Method and apparatus for transferring data to display unit from memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a method and apparatus for displaying graphical ink information, and more particularly to direct memory access ( (DMA) apparatus and method.

[Background of the invention and its problems]

It is quite common in the computer industry to represent and communicate information to users through graphical ink representations. These representations can take the form of, for example, alphanumeric characters, graphs with Cartesian or other coordinates, and well-known physical objects. Traditionally, the interface between humans and computers has been through individual command systems. The individual command system includes a combination of text and mathematical symbol characters. There are many examples of such individual command systems, including FORTRAN, ALGOL, and PLI.
, BA-8IC, and programming languages such as COBOL. These programming languages translate a given set of user commands into ``object'' code that a machine can execute.

However, the ease with which a user becomes proficient in programming and interacting with computer-based devices is generally related to how close the user's own logical thinking is to the model of the system. Systems developed to shorten the learning and adaptation period that users must be smart about in order to become proficient at interacting with computer systems are
oriented) J system.

This system utilizes multiple "windows" displayed on a cathode ray tube (CRT). These multiple windows use a combination of text and graphics to convey information. For example, each window may take the form of a file holder of the type used in standard filing cabinets. The filing holder is superimposed on the other holder. The topmost holder of the stacked holders constitutes the current working file. The user can add information to the window, remove information from the window, and refile the file folder to another location, just as if the actual file were being used in the office. Can generally work in windows. Therefore, it graphically presents an image representing the purpose of the user's commands, allowing the user to manipulate and process the image in much the same way that the user would do if the image consisted of real objects. This makes it easier for the user to operate the computer device and achieves a strong user interface.

One of the traditional limitations to the use of window-based display devices is when it is desired to use animation within the window. In such cases, a series of frames of data are displayed within a window over a period of time, thereby making it appear as if what is being displayed is moving, such as in a television or movie.

However, it has traditionally been difficult to animate these images due to memory access speed constraints. Generally, the time required for a central processing unit (CPU) to read the data that makes up an image from memory and display that data is about υ or 2, and the image is continuous from one frame to another. and flowingly.
It didn't seem like it was moving. As will be explained below, the present invention provides a direct memory access (DMA) device that allows images stored in memory to be displayed in a window on a CRT at such speed that animation effects are achieved. It is something to do.

[Summary of the invention]

The present invention discloses an apparatus and method for direct memory access (DMA) that has particular application for displaying digital video in an animated manner on a CRT display. The present invention includes a DMA controller coupled to a frame buffer by a bus. Adjacent blocks of memory within the frame buffer are sequentially mapped to picture elements (vixels) on the display device. 5 frame buffers are CR
Continuously run the bitmap representing the T screen. Multiple windows can be displayed on the CRT with varying predetermined widths that are appropriately represented within the frame buffer. Digital video stored as sequential "frames" of data in a memory, such as a hard disk or RAM memory, can be moved from memory to a frame buffer for display without the need for central processing unit intervention and address recalculation. Can be transferred directly to the window.

The user first determines the width of the window. The height of the window is implied by the number of data to be transferred for completion. Thereby, a rectangular area to which the graphic data is transferred is determined.

The user then sets the base address corresponding to the first memory address. Its base address is the predetermined origin of the window.

That is, it is assigned to the top left pixel that determines the window. The DMA controller initiates a read operation so that frames of data defining the image are sequentially read from the disk or main memory and written to the graphics controller. To view incoming data later,
Graphink controls forward their incoming data to the window.

The host software then performs subsequent data transfer operations after a predetermined period of time "T" has elapsed. If additional frames are to be displayed, a new base address is set for the first sequential frame and the operations described above are then repeated. By using the present invention, digital video stored in memory can be transferred directly to a "window" in a frame buffer at high speed, thereby achieving animation effects.

[About terminology]

The detailed description that follows is presented primarily in terms of algorithms and symbols for operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art.

The term algorithm is considered in this specification to be a self-consistent sequence of processes leading to a desired result. These processes require physical manipulations of physical quantities.

Usually, those physical quantities are.

in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated.

It doesn't necessarily have to be like that. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, ring numbers, or the like. It should be remembered, however, that all these and similar terms are to be associated with specific physical quantities and are merely convenient labels applied to those quantities.

Additionally, the operations performed are often referred to with terms such as addition, movement, or comparison that are commonly associated with mental operations performed by one person. None of the operations described in this specification that form part of the present invention (which operations are machine operations) require that an operator be capable of performing such operations. Machines useful for carrying out the operations of the present invention include general purpose digital computers or similar devices. In all cases, one must be aware of the distinction between the method of operating a computer and the method of calculation itself. The present invention relates to a method of processing electrical or other (e.g. mechanical, chemical or physical) signals to operate a computer and generate other desired signals.

One invention also relates to an apparatus for performing those operations. The device can be specifically configured for the purpose sought (i.e.

direct memory access controllers and frame buffers),
Alternatively, the apparatus may include a general purpose digital computer, selectively activated or configured by a computer program contained in the computer.

The algorithms and circuits described in this specification are not inherently related to any particular computer or other apparatus.

In this specification, direct memory access (DMA) is used to display digital video in an animated manner.
) are disclosed. In the following description, numerous details are set forth regarding specific matters, such as number of bits, architecture, order of operation, etc., in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention may be practiced without such specific details. In other instances, well-known circuits and structures have not been described in detail in order to avoid obscuring the present invention with unnecessary detail.

Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

Reference is first made to FIG. 1, which shows an apparatus for generating and displaying digital images in accordance with the present invention. bus 1
Coupled to 2 is a host CPU (in the embodiment described herein, the host CPU comprises a 32-bit microprocessor based on the Motorola 68010). The host CPU 12 is given by the user,
It performs various functions, including running application software that can determine the images to be displayed in a window on cathode ray tube (CRT) display 14. Memory 15 is C
is coupled to PU10 to enable data to be transferred via the bus to various data processing units attached to the CPU. In order to display the video, the present invention uses bus 1
2 and a color frame buffer 18 coupled to the CRT 14. Frame buffer 18 contains one or more "bitmaps" of the display screen of CRT 14. For each bitmap, blocks of memory within frame buffer 18 are allocated such that each memory address and data value is mapped onto a corresponding image element (pixel) on the display. Thus, for each bitmap, the entire CRT screen is represented as a 1 (eg, foreground) or a 0 (eg, background) in a block of memory called 1-bitmap J. In multi-image systems, it is common for the "N-focus" value at each memory address to be mapped through a color map lookup RAM to provide a range of colors for each pixel. The frame buffer 18 continuously scans a bitmap representing the CRT screen in a manner well known in the art so that corrections to the data focus within the frame 79 software are correspondingly displayed on the CRT 14. do. DMA controller 20 connects bus 12
and a hard disk drive 22 . Also,
The DMA controller 20 is connected to an Ethernet (ETHERNET).
), DECNET, etc., or to an additional hard disk drive R or other network 24.

Referring now to FIG. 3, in accordance with the present invention, by appropriately writing data into areas within the frame buffer 18, a plurality of windows 1 can be displayed on the CRT 14. In practice, frame buffer 18 includes dual-vote dynamic RAM bitmap memory. This Taikamitsuku R
In AM focus map memory, each memory byte is CR
Corresponds to a pixel on a T14 display. Frame buffer 18 may also include a plurality of bitmaps representing CRT 14 so that one memory set can be updated while another memory set is being read for display. For example, while the first memory set is displayed, the second memory set is updated. This technique, called double buffering, allows instantaneous switching from one video to the next without the visual effect of displaying partially updated video. As shown, each window displayed on CRT 14 may include various alphanumeric characters and graphics. Windows can be stacked on top of other windows, giving the appearance of holders stacked on a desk. In most cases, the data to be displayed is processed by CPU 10 through the execution of application software programs. The data to be displayed is then transmitted via bus 12 to
The data is transferred to one or more bitmaps that make up frame buffer 18. However, when displaying digital images in an animated manner, it has been found that the processing demands of CPU 10, for example in accessing images stored in memory 15, are too slow to achieve an animated effect. There is. In addition, the storage space required to store several or thousands of pre-calculated images in the CPU 0 main memory is the disk 22
Compared to the cost of mass storage devices such as The present invention allows the DMA controller to read the entire disk 22 and transfer data to the network 24.
9, the frame of digital information that makes up the video, the processing by the CPU 10 and the large-capacity C
By providing the DMA controller 22 with a circuit that allows images to be displayed on the CRT14 without the need to use the PU main memory, the limitations of conventional display devices are overcome. be. The present invention allows a "window" of a desired width to be formed on the CRT 14 and to sequentially write to the portion of the frame buffer 18 where the window is located.

Next, refer also to FIG. - As an example, the magnetic disk 22
Assume that the user desires a series of digital images (defined as frames) stored in the computer. In the embodiment described here, screen 1
The corresponding bitmap in CRT14 and frame buffer 18 is configured such that the pixel in the upper left corner of CRT14 is named as the origin of the display (0,0). Also,
In the embodiment described herein, the CRT display 14 sequentially numbers each successive pixel along the scan line in a somewhat linear fashion. Currently, there are 1152 pixels along each scan line of CRT display 14, numbered 0 through 1151. 11 for pixels starting on the next scan line
It is numbered 52, etc. As best shown in FIGS. 1 and 3, a window within a display screen is defined by the area contained within a large bitmap. Users wishing to sequentially and directly transfer Graphink images stored in digital form in a memory such as 5 memory 15 or disk 22 in accordance with the present invention may use the bitmap of each frame buffer 18 and the corresponding area of CRT 14. First determine the width of the window within. As best shown in FIG. 3, the window borders define a rectangular area into which graphics data is transferred. In the embodiment described herein, the dimensions of the video stored in storage correspond to the dimensions of the video subsequently displayed on the CRTiJ, as stored in frame buffer 18. For example, a digital image stored on the hard disk 22 having a size of 512 points x 512 bits is
C as an image of 512 pixels wide x 512 pixels high
Displayed on RTl4. Therefore, it is important for the user to specify a window width that corresponds to the width of the video to be displayed within the window. The user then sets the base address for memory access. The base address corresponds to the first memory address assigned to the predetermined window origin, ie, the upper left point that defines the window.

In the example shown in FIG. 3, the base address point is identified as point rBJ. DMA controller 20 then initiates a sequential read operation whereby frames of data defining the video are read from memory (eg, hard disk 22 or memory 22) and transferred to frame buffer 1 via path 12 at a predetermined address range.
Transferred to 8.

Logic located on graphics controller 26 and frame buffer 18 determines the supplied address and CR
Redirect the incoming data to the appropriate location in the frame buffer containing the desired window on Tl4. The data transferred to frame buffer 18 is scanned and displayed on CRT 14, as is well known in the art. The host software then waits a predetermined amount of time (eg, 1/24th of a second or 1/16th of a second) before continuing further data processing to display subsequent frames of digital graphics data. Assuming that the frame buffer 18 is double buffered during the vertical retrace period of the CRTl 4 (e.g., so that the frame buffer 18 contains two full-sized bitmaps that can be alternately "toggled"), the DMA controller 20 will alternate between the frame buffer bitmaps for each write cycle.

If an additional frame is to be displayed for an animation effect, the DMA controller 20 sets a new base address for the next memory access and fetches the next frame of digital video - i.e. the additional frame from memory. Start read operation.

The cycle continues until all frames have been mapped from memory via DMA controller 20 to windows in frame buffer 18.

Reference is now made to FIG. 2, where a block diagram illustrating a portion of the memory access logic within frame buffer 18 is shown. As will be explained in more detail below, the illustrated circuit generates a row address signal (RAS) and a column address signal (CAS). Those signals are stored in a suitable storage device for storing digital images.

The user sets the initial base address and provides that address to the base counter 30. Similarly, the width of the DMA window to be displayed on the CRT 14 is set by determining the number of pixels specifying the width of the window in binary, and the number is written into the width register 32. The output terminal of width register 32 is coupled to counter 34 such that the width value is provided to the data load input terminal of counter 34. Counter end of limit counter 36 (TC)
An output terminal is coupled to the count enable incoming data of counter 30. The counter 30 counts up to a predetermined number of cycles before holding. For example, in the example shown in FIG. 3, the dimensions of the CRT screen,
Therefore, the bit size of the frame buffer is 1152 pixels wide. That value represents the scan line length limit for a particular display and the maximum count value of counter 36, which the number of cycles in counter 30 will increment before holding. 20
Bit counter 38 is loaded from the output terminal of base counter 30, and as explained later, counter 3
The output of RAS 8 drives the accessed frame buffer memory.

Assuming that no DMA transfer is performed, the system clock changes from the initially given base value to the base counter 30.
increases at the same time. When the limit counter reaches its maximum count, it no longer increases its count value and also prevents the base counter 30 from increasing its count value. Therefore, the final base value is the initial base value plus the limit counter range (i.e.
1152). Since a DMA transfer occurred, the value contained in 20-bit counter 38 was the original initial base address value, and therefore the count of 20-bit counter 38 was not incremented. Similarly, D! Since no vIA transfer has occurred, the value of 1-width register 32 and the value of 12-bit counter 34 also remain the same.

When performing a DMA transfer from memory to frame buffer 18, an initial base value and an initial width value are provided, as will be explained later. Therefore, before the start of DMA transfer, the initial base value is the base counter 30 and 20.
Bit counter 38 is stored and the first width value from the @ register is provided to 12 bit counter 34. As shown, a signal provided on line 40 causes the count of 12-bit counter 34 to be incremented at the end of each memory cycle. Every memory cycle increments the counts in the 12-bit wide counter 34 and the 20-bit counter 38. Therefore, the 20-bit counter 38 is
Each time new data is received through system path 12, it outputs an incrementing frame buffer address. 1
When the 2-bit counter 34 reaches the predetermined maximum window width, a end-of-count (TC) signal is applied to line 4.
Output to 2. That signal causes the new base value to be loaded back into the base counter 30. As explained earlier, the new base address given is the previous base address plus the value of the limit counter (i.e. 1152)'e
It was added. Loading this modified address into the base counter 30 results in the count of that counter.

Incremented to the start address of the next scan line within the defined window. Also, the assertion of the TC signal 42 reloads the limit counter so that the limit counter 3G starts counting again up to its limit count. The series of operations described above continues until all data frames are read out and written into the frame buffer 1B.

Thus, an apparatus and method for displaying digital video in animated form on a CRT has been described. Although the invention has been described with particular reference to FIGS. 1-4, many changes and modifications may be made to the materials and construction of the elements of the invention without departing from the spirit of the invention. It will be obvious to those skilled in the art that this can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a computer apparatus according to the invention; FIG. 2 is a block diagram of an embodiment of the invention that enables DkIA access and display of stored video; and FIG. 1 is a schematic diagram illustrating the use of the DMA controller of the present invention to transfer the data making up the images being displayed and display them in an animated form. FIG. 4 is a flowchart showing a series of operations of the present invention for displaying images stored in memory. 10...Central processing unit, 14...CRT display device, 15...Memory, 18...Frame back 7.20...DMAfitlJ control, 26...
・Graph ink controller, 30・・Fist・Base counter,
32...-II register, 34...12-bit kakunta, 36...e@limit counter, 38φ...No. 20
bit counter.

Claims (29)

[Claims] (1) In a computer display device including a display means having a display having a plurality of display elements selectively enabled, the data to be displayed is defined by a unique address location and organized into frames in a storage device. and reading a frame of data from said storage device and transferring said data to a selected location in a frame buffer coupled to said display means, said frame buffer containing data bits. at least one bitmap, the bits representing a state of a display element on the display, the location in the frame buffer defined by a width value and an origin, and wherein data is read from the frame buffer for display. A method for transferring data from a storage device to a display device, wherein the frames are sequentially read from a base address so that the data is transferred in the order in which the data is transferred from a storage device to the display device. 2. The method of claim 1, wherein the display elements are arranged in scan lines, and the data in the storage device is read out by the controller means one scan line at a time. A method characterized by: 3. The method of claim 2, wherein the selected locations in the frame buffer comprise a rectangular array, and the array locations are a subset of the bitmap. how to. 4. The method of claim 3, wherein the locations defining the rectangular array are read by the controller means in the order in which the data is read from the storage device. how to. 5. A method as claimed in claim 4, characterized in that the data is read in successive frames and transferred to the frame buffer separated by a time "T". (6) A method according to claim 5. The method characterized in that the width value is defined by a user. (7) A method according to claim 6. A method characterized in that it includes a buffer for temporarily storing each said frame before transferring said frame to said frame buffer means. (8) The method according to claim 7, wherein the data to be displayed includes digital video. (9) The method according to claim 4, wherein the reading step comprises: base counting means receiving the base value; counting up to a holding limit value; and then the base counting means does not count any more. limit counting means coupled to said base counting means for determining said unique address in said storage device; width counting means coupled to said base counting means and said width counting means for receiving said width value; address output counting means for providing RAS and CAS output signals to define a location; system clock means coupled to said base counting means for incrementing the counts of said base counting means and said limit counting means; and memory cycles. and memory cycle signal generation means coupled to said width counting means to increase said RAS output signal by providing a signal to increase the count value of said width counting means. How to characterize it. (10) The method according to claim 9, wherein the width counting means outputs a count end (TC) signal when the width value is reached, and the TC signal converts the width value into the width count. A method comprising: reloading the base counting means; resetting the limit counter; and providing a new memory base address to the base counting means. (11) The method according to claim 10,
The method characterized in that the base counting means includes a 20-bit counter. (12) The method according to claim 11, comprising:
The method characterized in that the width counting means includes a 12-bit counter coupled to a width register. (13) The method according to claim 12,
The method characterized in that the address output counting means includes a 20-bit counter. (14) The method according to claim 13,
A method characterized in that said controller means, said storage device and said frame buffer means are coupled to each other along a bus. (15) The method according to claim 14,
the frame buffer includes a plurality of bitmaps such that the contents of each bitmap are displayed in an alternating manner;
The method characterized in that the contents of another bitmap are updated. (16) a display means for displaying data, comprising a display having a plurality of display elements selectively enabled; and at least one bitmap containing a plurality of data bits representative of the state of the display elements of the display. frame buffer means coupled to said display means for storing data to be displayed; a storage device for storing data to be displayed as frames at unique address locations; and frame buffer means for storing said frames of data from said storage device. controller means coupled to said storage device and said frame buffer means for reading and transferring the read data to a selected location within said frame buffer means, said location being defined by a width value and an origin. The controller means reads the data sequentially starting from the base address so that the data is transferred at a high speed so that the data is transferred in the order in which it is read from the frame buffer means for displaying the data. A device for transferring data from a storage device to a display device, characterized in that the data is transferred to a display device. (17) The device according to claim 16,
Apparatus according to claim 1, wherein said display element is arranged in scan lines and said data in said storage device is read out by said controller means one scan line at a time. (18) The device according to claim 17,
The apparatus wherein the selected locations in the frame buffer comprise a rectangular array, the array locations being a subset of the bitmap. (19) The device according to claim 18,
Apparatus characterized in that the locations defining the rectangular array are read by the controller means in the order in which the data is read from the storage device. (20) The device according to claim 19,
Apparatus according to claim 1, wherein said controller means reads successive frames of said stored video and transfers each said frame of data to said rectangular array separated by a time "T". (21) The device according to claim 19,
The apparatus according to claim 1, wherein the width value and the base address are defined by a user. (22) The device according to claim 17,
Apparatus according to claim 1, wherein said controller means includes a buffer for temporarily storing each said frame before transferring said frame to said frame buffer means. (23) The device according to claim 16,
An apparatus characterized in that the data to be displayed includes digital video. (24) The device according to claim 19,
The controller means includes base counting means for receiving the base value and limit counting means coupled to the base counting means for counting up to a holding limit value and then preventing the base counting means from counting any further. , width counting means for receiving said width value; and address output counting means coupled to said base counting means and said width counting means for providing RAS and CAS output signals defining said unique address location within said storage device. , system clock means coupled to said base counting means for increasing the counts of said base counting means and said limit counting means; memory cycle signal generation means coupled to said width counting means for increasing the RAS output signal. (25) The device according to claim 24,
The width counting means outputs a end-of-count (TC) signal when the width value is reached, which TC signal reloads the width value into the width counting means, resets the limit counter, and sets a new memory base address. to the base counting means. (26) The device according to claim 25,
Apparatus according to claim 1, wherein said base counting means includes a 20-bit counter. (27) The device according to claim 26,
Apparatus according to claim 1, wherein said width counting means includes a 12-bit counter coupled to a width register. (28) The device according to claim 27,
An apparatus characterized in that said address output counting means includes a 20-bit counter. (29) The device according to claim 28,
Apparatus characterized in that said controller means, said storage device and said frame buffer means are coupled to each other along a bus.