KR0158483B1 - Selecting circuit for byte writing - Google Patents

Abstract

1. FIELD OF THE INVENTION The invention described in the claims belongs to: A write selection value generation circuit of a two-dimensional graphics accelerator.

2. A technical problem to be solved by the present invention is to provide a selection value generation circuit that obtains selective memory information in units of bytes for a predetermined frame buffer memory bus width from coordinate values of a drawing instruction.

3. Summary of the Invention The circuit of the invention comprises a drawing control section for generating span values of a grill span; First and second barrel shifters coupled to the drawing control unit to generate first and second byte write selection values; And a gating part configured to generate a byte write selection value by gating the selection value of the first and second barrel shifters.

4. Important use of the invention: It is used as a selection value generating circuit which obtains the selective memory information in bytes for a predetermined frame buffer memory bus width from the coordinate values of a drawing instruction.

Description

Byte write selection value generation circuit

1 is a byte write selection value generation circuit diagram of the present invention.

The present invention relates to a two-dimensional graphics accelerator using a frame buffer memory having a bus width of 32 * N (where N is 1, 2, 4, 8 ...) size, in particular byte writes suitable for extended data widths. It relates to a selection value generating circuit.

In general, the interface data width of the frame buffer memory is 32 * N (N = 1, 2, 4, 8) to improve the performance of the two-dimensional graphics accelerator (an integrated circuit chip that improves performance by drawing hardware). When extended to a bit, ..., a drawing engine that can draw a plurality of pixels in each memory write cycle to take full advantage of the extended data width is required.

Such a drawing engine can improve performance only by increasing the number of pixels drawn per memory write cycle.

Conventionally, since the byte write selection value generation circuit suitable for the extended data width in the drawing engine is not employed, there is a problem in that optimal performance cannot be expected.

Accordingly, an object of the present invention is to provide a selection value generation circuit for obtaining selective memory information in units of bytes for a predetermined frame buffer memory bus width from coordinate values of a drawing command.

According to the present invention for achieving the above object, a two-dimensional graphics accelerator using a frame buffer memory having a 3 * (multiply) N (N = 1, 2, 4, 8, ...) bit bus width A byte write selection value generation circuit comprising: a drawing control section for generating span values of a grill span; First and second barrel shifters coupled to the drawing control unit to generate first and second byte write selection values; And a gating unit configured to generate a byte write selection value by gating the selection value of the first and second barrel shifters.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Currently, the personal computer graphic display device is used from mono color (B / W) to 16, 256, 64K, 16M colors, the circuit of the present invention is applicable to 256, 64K, 16M colors.

Figure 1 is a suitable circuit when a 32 * N (N = 1, 2, 4, 8, ...) bit memory bus structure. In FIG. 1, the byte write selection value generation circuit of a two-dimensional graphics accelerator using a frame buffer memory having a 32 * N (N = 1, 2, 4, 8, .....) bit bus width is drawn. A drawing control unit 10 for generating span values of a span, a first barrel shifter 20, 21, 22 connected to the drawing control unit 10 to generate a first byte write selection value, and a second byte write selection connected to the drawing control unit 10; Second barrel shifters 30, 31, 32 for generating a value, and a gate portion 40 for generating a byte write selection value by gating the selection values of the first and second barrel shifters. The first barrel shifter includes a first shifter 20, a first comparator 21, and a multiplexer 22, and the second barrel shifter includes a second shifter 30, a second comparator 31, and a multiplexer 32.

According to the above configuration, Xs and Aws, Awe, Bms, and Bme of the grill span are obtained. In the upper barrel shifter, byte write selection is performed using the relationship between Bms, Awc, and Aws. Similarly, the lower barrel shifter uses the relationship between Bme, Awc, and Awe to select byte writes. The AND of these two results is the final byte write selection.

The drawing engine performs a drawing operation by obtaining a coordinate value of a green position and writing a color value to a corresponding address of a frame buffer from the drawing engine. In this case, the relationship between the contents of the frame buffer and the pixels displayed on the screen is shown in Table 1 below.

bpp: Bits per pixel

When the width of the frame buffer interface data bus is 32 * N bits, in order to improve the performance as the bus width is extended, as many pixels as possible from the information of the coordinate values are written to each memory write cycle. In order to implement this, a byte enable for each byte of the memory bus width must be obtained from the coordinate value. In this case, only the X coordinate value is involved in the write selection of the byte unit. If the X coordinate displacement is Xs to Xe for the same Y coordinate value, the memory width is defined as 32 * N bits (or 4 * bytes) (N = 1, 2, 4, 8, ...). The choice of writing the data can be obtained from the relation shown in Table 2 for the X coordinate value.

If the Aw value for the Xs value (see Table 2) is Aws and the Aw value for Xe is Awe, drawing from Xs to Xe is equivalent to writing a byte write selection from Aws to Awe into memory. The circuit for obtaining the byte write selection value at this time is the circuit of the present invention. The displacement from Xs to Xe is called the span, and filling it with Awe = Aws ,,, Awe, ie Awc (the current memory write unit address) from Aws to Awe. The byte write selection values are shown in Table 3 below.

As described above, when the byte write selection circuit according to the present invention is used, drawing performance can be improved by maximizing the advantage of the increase in the memory bus width when performing a line, polygon fill, or other two-dimensional graphic drawing. It has an effect.

Claims (1)

A byte write selection value generating circuit of a two-dimensional graphics accelerator using a frame buffer memory having a 32 * N (N = 1, 2, 4, 8, .....) bit bus width; A drawing controller for generating span values of the grill span; First and second barrel shifters coupled to the drawing control unit to generate first and second byte write selection values; And a gate for generating a byte write selection by end gating the selection of the first and second barrel shifters.