JPS60147785A - Controller for data movement between logical areas - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field 1 The present invention relates to improvements in computer display control.

[Background Art] FIG. 1 shows a block diagram of a conventional color graphics display device.

In the figure, a CPU (microprocessor) 1 is provided which controls the entire device, and a main memory 2 and a display control circuit 3 are connected to this CPU. The main memory 2 holds programs and data, and the display control circuit 3 controls color graphics display.

Note that numeral 4 is a VRAM that holds CR1 display data.
(video memory), symbol @5 is a CRT color display unit.

FIG. 2 shows a block diagram of an example of the display control circuit 3 shown in FIG. 1. In FIG.

A clock signal generated by the timing controller 11 is input to a counter 12 having a digit counter, a line counter, and a row counter. A CRT display synchronization signal □ is generated from this counter 12 via a display timing circuit 13. On the other hand, counter 12r: A display address is created and output as a VRAM address via multiplexer 15.

Read data for display access from VRAM 4 is sent to the video A output controller 1-0-ra 20 via the buffer 19.
The CRT video input signal is input into the CRT video inverter.

On the other hand, CPLll stores VRAM4 at 7'/L st? li
If so, the address of VRAM4 is set in VRAM address register 14. Then, when the light smilling lobe is input to the CPU interface controller I/roller 18, it is sent to the multiplex controller 15 (the V
The output of the RAM address register 14 is selected as the VRAM address, and the write data from the CPU 1 is rq loaded into the VRAMd via the buffers 16 and 17.

FIG. 3(A) is a diagram showing the logical memory space.
sQKRIn%rk & Seal J111all116-+
There are 7 NiI. As shown in FIG. 3(A), the logical memory space includes a performance table area, a display area, and a matrix area, and these three areas start with different base values. Completely separated. Then, as a screen display, the application software may request the display of several different window frames, such as the one display area shown in FIG. 3(A). In such a case, a request arises to transfer data between those areas.

X on the logical memory space shown in FIG. 3(A).

Consider an example of operation in which block data in a source area S in VRAMJ is transferred to a destination area based on the Y coordinate. In this case, the source area S is a predetermined area (the area marked with diagonal lines downward to the left) that corresponds to the display area, and the destination area is a predetermined area ( (area marked with diagonal lines slanting downward to the left).

The CPU 1 calculates the value of the base address of the source area S (hereinafter referred to as "base SBJ") and the start coordinate (
SX, 5Y) G: Calculate the physical address SA of the VRAM 4 and set it in the VRAM address register 14 in the display control circuit 3.

The CPU then outputs a read command and reads the color data in the VRAM 4 corresponding to the star 1 to coordinates (SX, SY).

Next, the base SB of the destination area, which is the transfer destination, and its star 1 to coordinates (DX).

DY), a physical address DΔ corresponding to V RAM /I is outputted and set in the VRAM address register 14 in the display control circuit 3. Then, 0PU1 outputs the color data and the lie I command, and the starting position 1m (DX, DY) in the destination area.
) CF in VRAMn corresponding to Ic! Get into it.

Then, repeat the above read/write procedure NX times in the horizontal direction and NY times in the vertical direction (NX*NY)
By repeating this process, the block data in the source flfl area S can finally be transferred to the destination area. In addition, in FIG. 3(A), the symbol s
d is the data display area, SA is the start coordinate of the support message area, and SB is the base value of the support message area.

Of course, the same applies when data is transferred in the opposite direction to the above, and the same applies when data is transferred from the support message area to the display area.

The performance table area shown in FIG. 3 is variable depending on the application software, but there are cases where a very large area is required, and there are cases where a small area is required. The same applies to the support message area. On the other hand, the display area has a fixed size determined by the hardware of the CRT display. In such cases, a certain window frame is imaginary within the display area, and the part that needs to be displayed at that time is brought into this frame and displayed, and the window frame is adjusted according to the situation. is required to move. In this way, the width of each area takes a logically reasonable value. Therefore, the data is divided into several blocks, and it is necessary to transfer data between data areas with different intervals between blocks, so it is necessary to transfer data between continuous areas that can be handled by conventional hardware. Transfer alone cannot be used.

Therefore, for this purpose, it is necessary to perform the above processing using software.

Conventional display control circuits for personal computers have been designed to reduce the hardware size, e.g., the number of gates, 1c elements, etc. related to the internal structure and interface of the display device, in response to the desire to reduce the size and cost of the computer. The software is designed to reduce the number of software components, and the burden of software increases accordingly.

[Problems with Background Art] As shown in the above example of block data transfer, all of the processing places a burden on the CPU, and the transfer takes a very long time.

On the other hand, normally, the CPUI and the display control circuit 3 operate independently of each other, and the display control circuit f! Since the display timing of No. 3 is given priority over the VRAM access timing of the CPU 1, there is a problem that a delay time occurs for the access from the CPU 1 to the VRAM 4, and the efficiency of data transfer is extremely deteriorated.

In other words, in the above-mentioned conventional technology, there is a problem in that the burden on the software is large when controlling the display, and the time required to execute the operation is extremely long. Furthermore, as computers become more advanced, display specifications increase, and a plurality of display modes are provided, the address Itn becomes even more complex, and the time required to execute the operation becomes noticeably longer.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned conventional 11fla, and it is possible to shorten the execution time of the data transfer operation from the source area in the logical memory space to the destination area. The object of the present invention is to provide an inter-logical area data movement control device that is capable of controlling data movement between logical areas.

[Summary of the Invention j In order to achieve the above object, the present invention provides a display control device with an area move function, and also provides a display control device with an area move function.
There is a system in which the logical width of the destination area and the logical width of the destination area are given separately. The interface procedure at this time is determined by soft orientation.

[Embodiment of the Invention] FIG. 4 is a block diagram showing an embodiment of the present invention.

Clock optical generator 31 that generates a display timing clock
GJ is set, and according to the displayed timing clock,
A counter 32 is provided having a digit counter, a line counter, and a row counter for generating the cR-r duplex display timing and VRAM address.

A data bus 41 from CeO2 is connected to a register data bus 43 via a buffer 42. cpui
A register pointer/counter 44 holds the number of the register in the display control circuit 3 that is accessed by the register pointer/counter 44, and a register selector decoder 45 decodes the output of the register pointer/counter 44 to designate each register. This register pointer/counter 44 is
In addition to the register function, it also has a count-up function. For each register parameterlet, count up by one after completion. Therefore, it is possible to automatically specify registers one after another.

Further, the command register 46 holds command information from CPtJl, and the video CPU 47 can perform processing related to display data according to commands from the CPUI. The SR register 48 holds the status from the video 7j CPU 47 to the CPLll. cpui is V
When specifying the physical address of RAM 4 and accessing the VRAM 4, the VRAM address register/counter 37 holds the VRAM address. The color code register 33 holds write data to the VRAM 4 and read data from the VRAM 4.

The constituent elements described below are the features of the present invention.

That is, first, an SA register 71 that sets the value of the start physical address of the source area S to 1'', an SW register 72 that holds the logical width SW of the operation table area,
A [)A register 73 for setting the value of the start physical address of the destination area, and a DW register 74 for holding the logical width DW of the display area are provided.

Further, a basic selector 75 for selecting either the value of the S△ register 71 or the value of the OA register 73 is staged,
A change value U-rector 76 for selecting one of the value of the SW relenter 72, the value of the DW register 74, and the value of the NX counter 64 is provided in stages.

Further, the output of the basic value selector 75 is connected to one input of an adder 80, and the output of the change value selector 76 is connected to the other input of the adder 80 through a two's complement arithmetic circuit 81. Construct an executable circuit by adding or reducing values.

The two's complement I/I calculation @path 81 is controlled by the value of the horizontal or vertical direction flag 60.62, and is connected to the adder 80 to perform addition or subtraction depending on the data transfer direction. be.・□ The SA and DA registers 71 and 73 are set with data from the register data bus 43, and in addition to
It also has the function of loading data from the AM address buzz 36.

Next, the NX register 61 holds the number of transferred data in the horizontal direction (X coordinate direction), and the NY register 63 holds the number of transferred data in the vertical direction (Y' coordinate direction). The horizontal direction flag 60 indicates that it is “0”.
'' indicates a positive direction (rightward), and NJ indicates a negative direction (leftward). The direction 7 lug 62 in the m-direction indicates a positive direction (downward) when it is rOJ, and indicates a negative direction (upward) when it is "1".

In addition, the VRAM address bus 36 in the display control circuit 3 is
4(F) address line 56. The VRAM data bus 35 in the display control circuit 3 is connected to a buffer 53.
is connected to the VRAM data line 54 via the VRAM data line 54.

The S register 34 holds read data from the source area S, and the D register 52 holds read data from the destination area.

ALU (if-L knit) 51 Ha, biy”oc
According to the control from the PU 47, the logical performance of the output of the S register 34, the output of the color code register 33, and the output of the D register 52, for example, IMP, AND.

Perform the OR, EOR, and NOT sections.

The above are the characteristic components of the present invention, but there are other components in the display control circuit 3. but,
Descriptions of components that are not particularly necessary for explaining the operation of the present invention will be omitted.

Next, the operation of the above embodiment will be explained.

In the case where the logical width of the source area S and the logical width of the destination area are responsible, X, Y
The operation of the display control circuit 3 will be explained by taking as an example the transfer of block data based on coordinates.

The cpui stores the information necessary for transferring block data in each register in advance.
When accessing each register, it sets the register number of the register to be accessed first in the register pointer/counter 44, and then writes a series of data.

When transferring block data as shown in FIG. 3, the physical address SA at the starting point of the source area S is
is set in the SA register 71, and the physical address DA at the start point of the destination wA area is set as follows.
Sera 1 is set in the D△ register 73. Here, the SA register 71 is composed of 5AL (register #30), S to M (register #31), and SAH (register #32), and the OA register 73 is composed of DAL (register #35).
, DAM (register #36), and DAHC register number 7).

Therefore, the CPU 1 hits a 6-byte parameter with respect to the physical addresses SA and 'DA at the start point of the transfer, the source area S, and the destination area, respectively.

At the same time, the source side 1 rear width SW is set in the SW register 72, and the destination side area width D is set.
W is stored in the I)W register 74.

Here, SW register 72 is SWL<register #33
) and 5WH (register #34).
W register 74 is connected to DWL (register #38) and DW.
It is composed of H (register #39) and J:.

Note that FIG. 5 shows the contents of registers #30-39, and FIG. 6 shows the contents of registers #40-46 and register #2.

Then, set the number of data to be transferred in the horizontal direction (x coordinate direction) in the NXfNX register 61, and! [! Orthogonal direction (
The number NY of data to be transferred in the Y coordinate direction) is set in the NY register 63. NX Regis j61t, t, NXL
(Lz register #40) and NX1l (register #41
), and the NY register 63 is composed of NYL
(Register #42) and NY! ” (register #43).

Since the block data to be magnetized is in the positive direction in both the x and Y directions when viewed from the start point SA, rO is set in the direction flag 60 and the direction Y flag 62.
Set J. The direction flag 60 is bit 2+C of argument register ARGR- (register #45), and the direction Y flag 62 is bit 1-C of argument register ARGR- (register #45).
Corresponds to 3.

By performing Mogamitsu 1-, the setting of the parameters necessary for transferring block data is completed.The above parameter settings are continuous from register #30 to #45.First, register pointer /Counter 44 [
Set 30J.

Then, by simply writing parameter data continuously, the corresponding registers can be set in sequence. In this case, the register pointer/counter 44 points to #46 and is in a state where the command code is set.

FIG. 7 is a diagram showing the =1 cloak code.

In this figure, rVDcJ exceeds the display control circuit 3.

FIG. 8 shows a diagram of logical operations. In this figure, SC indicates the source color code, and DC indicates the destination color code.

The cpui executes a command code such as rl according to the above command code and logical operation code.
Create ooloooooJ and write it to the command register 46 (register #46).

The -L position 4 bits of the above command food are the source area S
If there is dust in V RAM 4 and in the destination area D t + V RAM J, then that V
This is an instruction to transfer block data in RAM4.

Furthermore, the lower 4 bits in the above example include a logical operation code C, and r 0000 J is a code that directly converts the source color code data into the destination color code data.

When the bidet JCPU 47 receives the command code from the CPU 1, it sets command executing (C[) in bit 7 of the SR register 48, and starts executing the 21st command.

First, a case will be described in which color code data is read from the source area S in the VRAMd.

First, the physical address SA of the start point is SB, the coordinates of the start point are (SX, SY).
Then, the following formula is given and set in the SA register 71.

5A-8B + SX + 5 Y Similarly, the change value selector 76 is activated, and the NX counter 64 is selected and sent to the adder 80.

If the first source address in this case is SA(i, 0), then this source address 5A(i
, o) are given by the following formula.

SA (i, 0) = SA1i ■ This i increases from 0 to (N, X-1>).

7 rope also shows 49 on the NX counter in the trace of 1 dot transfer.
When i is incremented by 1 and the transfer of one line of the source area S is completed, : becomes NX, and in this state, the NX input is cleared.

Then, the value of the SA register 71 is updated as follows. First, the base value selector 75 selects the chain of SA registers 71, the change value selector 76 selects the value of the DW register 74, these values are added to by the adder 80 and output to the VRAM address bus 36. Further, the bidet tcPU 47 is controlled so as to load this value into the SA register 71. This allows the next source address SA (
0°1) is given by the following equation.

SA (0,1)-8A+SW Then, each time one dot is transferred again, NX is counted, and if that value is i, the source address SA (+, 1) is given by the following equation.

5A(i, 1)=SΔ-1-1*SW+i i in formula 90 is above &! It is the same as I, and 1 in the 0 formula indicates that the row in the source area S has advanced by one, and generally,
It is expressed by the following formula.

5A(i,j)=SA+j*SW+i 00 In the equation, j is determined by calculating the displacement amount in the vertical direction from the coordinates of the starting point.

In other words, the address at the start point is given by the 0 formula, and the next line is given by the 0 formula, and when the transfer of that - row is completed, the NX counter 64 is cleared, and the addresses of the second and subsequent rows are Generally, it is given by the formula 0, and each time the transfer of that row is completed, j is counted, execution is moved to the row below 1°, and these processes are repeated.

Based on the address determined above, the VRA
Data is read from the performance table area in M4.

This read data is stored on the data line 54 and the buffer 153.
, via the VRAM data bus 35, the S register 34
is set to

On the other hand, the color code data read from the source side and held in the S register 34 is output onto the VRAM data line 54 via the Yashi U51, the VRAM data bus 35, and the buffer 153, The procedure for creating the incorporation address in this case is the same as the procedure for creating the address when reading from the source fRIgS described in 1-.

However, instead of SA register 71, DA register 73
and DW register 74 instead of SW register 72.
and also the base 8 of the starting point of the source region S
The procedure is the same as setting the base DBtj and coordinates (DX, DY) instead of B and the coordinates (SX, SY) of the start point, and calculating the 0 formula from the 0 formula described above.

Of the above operations, when reading one bit from the source area S and polishing one bit to the destination area are completed, the data transfer of one dot information is completed.

In the above explanation, the direction flag 60 a
3 and the direction Y flag 62 are set to "0", the two's complement enrichment circuit 81 is instructed to pass through in the horizontal and vertical processing, and the direction Y flag 62 is set to "0".
Addition is being performed in the reader 80.

In this manner, when the transfer of one dot of information is completed, the video CPU 47 presses the NX counter 64. When the transfer of one line of information is completed, the video CPU 47
7 counts up the NY counter 65. if,
If the direction execute the calculation.

Then, each time a one-dot signal is transferred, the contents of the C, NX counter 64 and the NX register 61 are compared by the conveyor circuit 66, and if they do not match, the data transfer is repeated according to the same procedure as described above.

Further, if the contents of the NX register 61 and the NX counter 64 match, the NX counter 64 is cleared.

The contents of the NX register 61 and the N (NXX
NY) @'s o y 9 y'-ta has been transferred.

Bidet AcPU47Lt, NX cash register 2') 61! = When a match is detected with the NX counter 64 and a match between the NY register 63 and the NY counter 65, it is determined that the block data transfer has been completed, the command executing (CE) pit of the SR register 48 is cleared, and the block Inform P LJ 1 of the end of data transfer.

In the above explanation, the command code is [100iooo
o1 is set in the command register 46&:, but the lower 4 bits LO3 to L00 [If the logical operation shown in FIG.
The S register 34 and the D register 52 can perform a logical operation r1'.

In the above explanation, the X coordinate in VRAMJ.

It also covers block data transfer by Y coordinate, but from CPU to VRAM4, VRAM4 color cPU
1, Display control circuit 3 h' 13 V RAM 4
Block data transfer to is also possible in the same way as above. These cases will be explained below.

N] When transferring near-out data to CPUI or 13VRAM4 (command codes CM3 to CMO are rl
ollJ) In this case, the source is CPUI, so register 7 is sent to S.
1. The SW register 72 and the S register 34 are not used, and the color hood register 33 is used instead.

CPU1 sets the color code register 33 and DΔ
According to the register 73 and the DW register 74, the bidet 7t
When the CP'u 47 loads the transfer router of the color code register 33 by -1 into the VRAM 4, it lets the transfer ready (TR) bit of the SR register 48, and the CPU
1, it is notified that one data transfer has been completed and it is now possible to accept the next data.

The CPU 1 confirms that this TR bit is "1" and then sets the next transfer data in the color code [/raster 33 from -[. After this, the 1R bit is reset (returns to the original state. Other operations are as follows)
Same r as block data transfer in VRAMn [2] When transferring cPLIIK7Dy'l data from VRAM4 (command code CM3-CMO is rl
(For oloJ) In this case, since the destination is CPU1, the DA register 73, DW register 74, and S register 34 are used. Instead of this, the h code register 33 is used.

t'Deo cPU47 is V RAM 4 Ka'3, S
According to the A register 71 and the SW register 72, the transferred data is read and set in the color code register 33, and the IR bit of the SR register 48 is set to "1". CPU1 examines this TR bit and determines “1.
”, the transfer data is read from the normal code register 33. This resets the TR bit and returns it to its original state. Other operations are the same as data transfer within VRAM4.

[3] When transferring block data from display control circuit 3 to VRAM 4 (command codes CM3 to CMO
is rloooJ) In this case, the data written into the color code register 33 is transferred to the destination area of the VRAM 4, and there is a method T'' that is effective when writing the same data. The operating procedure is from CPU1 to VRA
This is the same as block data transfer to M4. However, C
The PU 1 may be a unit that writes the first skin data into the color code register 33, and the data is transferred under the control of the video CPU 47. - Although the above explanation deals with color food or color data, it can also be handled as a monochrome system, in which case it is possible to imitate byte data.

Mizumoto 011; L, 135- OR'I' k: Q4.
L/ [It is effective not only for display ti(Iol), but also for other display SI+ locations such as monochrome OCR, LCD, plasma, and EL. ... [Effect for light] .

” - As mentioned above, even when the logical width of the source area and the logical width of the destination area are responsible, the present invention can reduce the processing time of software related to display operations. Most of it is handled by hardware]! ! !
This speeds up display menu access.
In addition, the increase in hardware required in this case is relatively small. The present invention is also effective in systems where the display memory is not separated from the main memory. Furthermore, it is clear that this effect can also be applied to data transfer on main memory.

[Brief explanation of the drawing]

Figure 1 shows a conventional general color display setup1
Block diagram: Figure 2 is a block diagram showing the display control circuit in Figure m1; Figures 3 (Δ) and (13) are respectively logical memory spaces; physical memory spaces; 4
The figure is a block diagram showing one embodiment of the present invention, fifth factor, m6
The figure is on 1F [! FIG. 7 is a diagram showing the contents of each register in the embodiment, FIG. 7 is a diagram showing command codes, and FIG. 8 is a diagram showing logical operations. 1...CPU, 2...Main memory, 3...Display system n
Circuit, 4...VRAM (video memory), 33...
・Color food register, 34...S register, 35
...VRAM address bus, 61...NX register, 63...NY register, 71...SA register,
72-3W register, 73...OA register, 74.
・・DW register, 75・・Basic value selector, 76・
...Change value selector, 80...Adder, 81...2
Complement concentration circuit, S...source region; spout, D...destination region. Fig. 5 #30 [Multi-mouth 2 go] 11 guns) 1 tool N♀ko I; 〼■≦
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Claims (8)

[Claims] (1)741. It! In a storage device that constitutes a display plane horizontally, means for specifying a transfer start point of a source area, means for specifying a transfer start point of a destination area, and means for holding a horizontal transfer data register. : means for holding vertical transfer data m; means for separately providing the logical width of the source area and the logical width of the destination area; The logic FJ! is characterized in that data is moved between FFI areas by reading data in a specified source area from the storage device and sequentially writing it into the destination area. Interregion data movement system m Sooka. (2) Special! The inter-logical area data movement control device according to claim 1, wherein the storage device is a display memory. (3) The inter-logical area data movement control device according to claim 1, wherein the source area or the destination area is a main memory via a single data register. (4) The inter-logical area data movement control device 11 according to claim 1, wherein the source area is a data register in the data movement control device d. (5) The inter-logical area data movement control device according to claim 1, wherein the register pointer for setting command parameters has a counting function and can be set continuously. (6) In claim 1, there is provided means for maintaining the moving direction of each horizontal and vertical transfer point, and the moving direction of the transfer point is determined between the f isdination area and the source cape area. An inter-logical area data movement control device characterized in that when data in the source area overlaps, data transfer is performed in an order in which the data in the source area is not changed by 1 before being transferred. (7) In claim 1, data movement between the areas refers to data in the source area and data in the depletion area! 1. A data movement control device between logical areas, characterized in that the data movement is performed by a logical vJ transfer means. (8) In a storage device that logically constitutes a display plane, means for specifying the transfer start point of the source area; means for specifying the transfer start point of the destination area; and means for holding horizontally transferred data. and means for maintaining data transfer in the square orthogonal direction; the data in the source area specified by the means is read from the device and sequentially written to the destination area, thereby transferring data between the areas. Inter-logical area data movement control side L characterized by movement.