EP0150453A3 - Inter-logical-area data transfer control system - Google Patents

Inter-logical-area data transfer control system Download PDF

Info

Publication number
EP0150453A3
EP0150453A3 EP84115899A EP84115899A EP0150453A3 EP 0150453 A3 EP0150453 A3 EP 0150453A3 EP 84115899 A EP84115899 A EP 84115899A EP 84115899 A EP84115899 A EP 84115899A EP 0150453 A3 EP0150453 A3 EP 0150453A3
Authority
EP
European Patent Office
Prior art keywords
area
data
destination
logical
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84115899A
Other languages
German (de)
French (fr)
Other versions
EP0150453A2 (en
Inventor
Takatoshi Ishii
Ryozo Yamashita
Kazuhiko Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASCII Corp
Original Assignee
ASCII Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASCII Corp filed Critical ASCII Corp
Publication of EP0150453A2 publication Critical patent/EP0150453A2/en
Publication of EP0150453A3 publication Critical patent/EP0150453A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Abstract

An improved inter-area-data transfer control system is disclosed which includes a display control device provided with an area movement function and is capable of providing the logical transverse widths of source (SW) and destination (DW) areas (registers 72 and 74) in a logical memory space separately from each other so as to reduce time required to execute the transfer of data from the source area to the destination area. The system comprises: means (71) for specifying a transfer start point of a source area (S); means (73) for specifying a transfer start point of a destination area (D); means (61) for holding amounts of data to be transferred in a horizontal direction; means (63) for holding amounts of data to be transferred in a vertical direction; and, means (72, 74) for providing the logical transverse width of said source area (S) and the logical transverse width of said destination area (D) separately, characterized in that a plurality of data of said source area specified by said means are read out from said memory unit (4) and are sequentially written into said destination area (D) so as to achieve transfer of said data between said source and destination areas (S, D).
EP84115899A 1984-01-12 1984-12-20 Inter-logical-area data transfer control system Withdrawn EP0150453A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59002710A JPS60147785A (en) 1984-01-12 1984-01-12 Controller for data movement between logical areas
JP2710/84 1984-01-12

Publications (2)

Publication Number Publication Date
EP0150453A2 EP0150453A2 (en) 1985-08-07
EP0150453A3 true EP0150453A3 (en) 1987-09-16

Family

ID=11536852

Family Applications (1)

Application Number Title Priority Date Filing Date
EP84115899A Withdrawn EP0150453A3 (en) 1984-01-12 1984-12-20 Inter-logical-area data transfer control system

Country Status (3)

Country Link
EP (1) EP0150453A3 (en)
JP (1) JPS60147785A (en)
CA (1) CA1224574A (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2180729B (en) * 1985-09-13 1989-10-11 Sun Microsystems Inc Method and apparatus for dma window display
US4777485A (en) * 1985-09-13 1988-10-11 Sun Microsystems, Inc. Method and apparatus for DMA window display
US4806921A (en) * 1985-10-04 1989-02-21 Ateq Corporation Rasterizer for pattern generator
EP0228745A3 (en) * 1985-12-30 1990-03-28 Koninklijke Philips Electronics N.V. Raster scan video controller provided with an update cache, update cache for use in such video controller, and crt display station comprising such controller
US4884069A (en) * 1987-03-19 1989-11-28 Apple Computer, Inc. Video apparatus employing VRAMs
US5113180A (en) * 1988-04-20 1992-05-12 International Business Machines Corporation Virtual display adapter
AU617006B2 (en) * 1988-09-29 1991-11-14 Canon Kabushiki Kaisha Data processing system and apparatus
KR100219758B1 (en) * 1992-06-29 1999-09-01 구라우치 노리타카 Oil pump made by al-alloy
JP2729151B2 (en) * 1994-10-19 1998-03-18 日本電気アイシーマイコンシステム株式会社 Storage controller
TW335472B (en) * 1996-06-20 1998-07-01 Cirus Logic Inc Method and apparatus for transferring pixel data stored in a memory circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5596988A (en) * 1979-01-19 1980-07-23 Tokyo Shibaura Electric Co Crt display unit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
HEWLETT-PACKARD JOURNAL, vol. 31, no. 12, December 1980, pages 25-32, Amstelveen, NL; H.L. BAEVERSTAD et al.: "Display system designed for color graphics" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 3A, August 1982, pages 1270-1273, New York, US; C.J. EVANGELISTI et al.: "Generalized pattern transfer from storage to storage bit buffer" *

Also Published As

Publication number Publication date
CA1224574A (en) 1987-07-21
JPS60147785A (en) 1985-08-03
EP0150453A2 (en) 1985-08-07

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Effective date: 19911009

RIN1 Information on inventor provided before grant (corrected)

Inventor name: ISHII, TAKATOSHI

Inventor name: YAMASHITA, RYOZO

Inventor name: NISHI, KAZUHIKO