CA1224574A - Inter-logical-area data transfer control system - Google Patents

Abstract

ABSTRACT
An improved inter-logical-area data transfer control system is disclosed. The new system is capable of reducing the time necessary for execution of its data transfer from a source area to a destination area in its logical memory space. This is archived by providing an "area movement" function and also arranging that the source area and the destination area are given separately from each other.

Description

'7 The present invention relates to an improved display control system for use in a computer.
The background of the invention and the invention itself will now be described in greater detail with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a commonly-used convention-at color display system;
Figure 2 is a block diagram of a display control circuit employed in the above conventional system in Figure l;
Figure I is a schematic view of a logical memory space;
Figure I is a schematic view of a physical memory space;
Figure 4 is a block diagram of an embodiment of the invention;
Figures 5 and 6 are schematic views respectively illustrating the contents of registers employed in the above embodiment;
Figure 7 is a table of command codes employed in the present invention; and Figure 8 is a table of logical operations employed in the present invention.
In Figure 1, there is illustrated a block diagram of a conventional color graphics display system.
In the illustrated prior art system, there is provided a CPU (microprocessor) 1 for controlling the whole system, to which are connected a main memory 2 and a display control circuit 3. Main Memory 2 is used to hold programs or data, while Display Control Circuit 3 is dedicated to controlling the display of color graphics. Reference character 4 denotes a TRAM (video memory) for holding CRT display data and 5 designates a CRT color display unit.
Figure 2 illustrates a block diagram of an embodiment of the display control circuit 3 shown in Figure 1.
In this embodiment, clock signals generated by a timing controller 11 are input to a counter 12 which comprises a column counter, a line counter and a row counter. Counter 12 generates synchronizing signals for CRT display via a display timing circuit 13, while Counter 12 creates display addresses which are output as TRAM addresses by means of a multiplexer 15.
Read data for display access coming from TRAM 4 is input to a video output controller 20 via a buffer 19 so as to create CRT video signals.
On the other hand, when TRAM 4 is accessed by CPU 1, the addresses of TRAM 4 are set in a TRAM address register 14.
And, if a write strobe is input to a CPU interface controller 18, the multiplexer 15 selects as TRAM addresses -the outputs of the TRAM address register 14 specified by CPU 1 and then the write data from CPU 1 is written via Buffers 16, 17 into TRAM 4.
Figure I illustrates a logical memory space and Figure I illustrates a physical memory space. As shown in Figure I, in the logical memory space there are present an ' to 'it I, - pa -operation table area, a display area and a support message area, and these three areas are started by separate values respectively and are definitely separated from one another. Also, for screen display, as can be seen from the display area shown in Figure I, there happen some cases where a display including a plurality of superposed window frames is requested from an application software.
In these cases, there arises a demand to perform data transfer between these areas.
Let us take an example in which in the logical memory space shown in Fig. I the block data of a source area S
within VRAM4 is transferred to a destination area D based on the X, Y coordinates. In this case, the above-mentioned source area S is considered as a predetermined area (area covered by leftward-falling oblique lines) in the operation table area, while the above destination area D is considered as a predetermined aurora covered by leftward-falling oblique lines) in the display area.
CPUl calculates a physical address SPA of VRAM4 based on the value of a base address (-this is referred to as "Base SUB"
hereinafter) in the source area S and the start coordinates (SO, STY) and then sets it in TRAM Address Register 14 within Display Control Circuit 3. And, CPUl outputs a read command and reads out the color data within VRAM4 that corresponds to the above-rnen-tioned start coordinates (SO, STY).
Next, CPUl, based on the Base SUB Or the destination area to which the block data is to be transferred and its start coordinates (DO, IVY), calculates a physical address DA
in TRAM 4, and then sets it in TRAM Address Register 14 within Display Control Circuit 3. And, CPUl outputs the color data and a write command to write them into the locations of VRAM4 that correspond to the start coordinates (DO, DYE of the desk Tunisian area D.

'7 With the above prior art system, it is necessary to repeat the above-mentioned read/write operations NO times regarding the horizontal direction and NY times regarding the vertical direction, -that is, a total of NO x NY times before the bloclc data of the source area S can be transferred to the destination area D. In Fig. I, reference character so designates a status display area, spa represents the start coordinates of a support message area, and sub expresses the base value of the support message area.
The above-mentioned principles, of course, can apply similarly when data is to be transferred in the opposite dip reaction, or when the data is transferred from the support message area to the display area.
The operation table area shown in Fig. 3 can be changed according to the Lund of application software. That is, a very large area may be requested for it or, on -the contrary, a small area may be requested. This is so with the support message area. On the other hand, -the display area has a fixed size that is determined by way of hardware by CRT Display.
In this case, a predetermined window frame is assumed within the display area and a portion to be operated at that time and requiring display is brought into this window frame, while the assumed window frame is requested for displacement according '7 to the conditions. Accordingly, the transverse width of each of the above areas can take on various values logically. Thus, the data to be transferred comprises several divided blocks and the data is also to be transferred between data areas which are dill-event from each other with respect to the distance between the blocks. Such operation cannot be processed completely only by the conventional data transfer technique using successive areas which can be dealt with by hardware.
For this reason, it is necessary to perform the above-mentioned processing by means of software.
To make a portable size a personal computer and reduce the cost thereof, a conventional display control system for a personal computer is designed such that amounts of hardware, e.g., the number of gates and the number of IT elements regarding the internal structure of a display unit and interfaces are reduced considerably. As a result of this, the loads of the software are increased accordingly in such conventional system.
With the above-mentioned prior art system, as can be seen from the above example of the block data transfer mentioned I above, all of the necessary processing must be performed by CPU 1, requiring a very long time for the data transfer.
On the other hand, normally, CPU 1 and Display Control I

Circuit 3 are operating independently of each other and also the display timing of Display Control Circuit 3 has a priority over the TRAM access timing of CPU 1. As a result of this, in access from CPU 1 to TRAM 4, a wait time is produced, which extremely decreases the efficiency of the data transfer.
In other words, in the above-mentioned prior art system, since the software must share a greater load in display control, there is a problem that it takes a very long time for the prior art system to execute its operation. Also, in case of a high-grade computer that has increased display specifications and plurality of display modes, the address calculations in the prior art system become more complicated so that the time necessary for execution of its operation is greatly extended.
The present invention aims at eliminating the drawbacks found in the above-mentioned conventional system.
Accordingly, it is a primary object of the invention to provide an improved inter-logical-area data transfer control system which is capable of reducing the -time necessary for execution of its data transfer from a source area to a destination area in its logical memory space.
In attaining the above object, according to the invent 5'74 lion, a display control system is provided with an "area movement"
function, and, at the same time, the logical transverse widths of the source area S and destination area D are given separately from each other. Interfacing procedures required for this purpose are to be determined and oriented by software.
The invention may be summarized as an inter-logical-area data transfer control system in a memory unit comprising a display plane logically comprising: first means for specifying a transfer start point of a source area; second means for specifying a transfer start point of a destination area; third means for holding amounts of data to be transferred in a horizontal direct lion; and, fourth means for holding amounts of data to be trays-furred in a vertical direction, characterized in that a plurality of data of said source area specified by said first, third and fourth means are read out of said memory unit and are sequentially written into said destination area so as to achieve inter-area data transfer.
The above and further objects and novel features of the invention will more fully appear from the following detailed desk Croatian when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for purpose of illustration only and are not intended as a definition of the limits of the invention.
The invention will now be described in greater detail with reference to Figures 4 - 8 of the accompanying drawings.
Figure 4 illustrates a block diagram of an embodiment of the present invention.

}5'7~

-pa- 27586-3 In the illustrated embodiment, there is provided a clock generator 31 for generating a display timing clock, and there is also provided a counter 32 having a column counter, a line counter and a row counter for generating a CRT screen display timing and a TRAM address in accordance with the display timing clock.
A data bus 41 from CPU 1 is connected via a buffer 42 to a register data bus 43. The number of registers included in Display Control Circuit 3 to be accessed by CPU 1 is held by a register pointer/counter 44 and the outputs of this register pointer/counter 44 are decoded by a register selector decoder t 45, so that the respective registers can be specified. This register pointer/counter 44 has a count-up function in addition to a register function. Namely, when a parameter is set for each register, Register Pointer/Counter 44 counts up 1 ~45'~'~

after completion of each setting. Therefore, it can specify the registers one by one automatically and successively.
Also, the command information from CPU 1 is held by a command register 46, and a video CPU 47 is able to perform processing on the display data in accordance with the commands from CPU 1. Status from Video CPU 47 to CPU 1 is to be held by an So register 48. When CPU 1 specifies the pays-teal address of TRAM 4 to access TRAM 4, the TRAM address is held by a TRAM address register/counter 37. The write data to TRAM 4 and the read data from TRAM 4 are held by a color code register 33.
The following components are the characteristics of the invention.
First, there are included an SPA register 71 for setting up the value of a start physical address of a source area S, an SW register 72 for holding the logical width SW of an open ration table area, a DA register 73 for setting up the value of a start physical address of a destination area D, and a DO
register 74 for holding the logical width DO of a display area.
Also, there are provided a base value selector 75 which selects either a value of SPA Register 71 or a value of DA
Register 73, and a variation value selector 76 which selects I

one of a value of SW Register 72, a value of DO Register 74, and a value of an NO counter 64.
Further, the output of Base Value Selector 75 is connect ted to one of inputs of an adder 80 and the output of vane-lion Value Selector 76 is connected via a 2's complement operation circuit 81 to the other input of Adder 80, whereby a variation value with respect to a memory address base value is added or subtracted to complete a practical circuit,

2's Complement Operation Circuit 81 is controlled by the value of either a horizontal direction flag 60 or a Yen-tidal direction flag 62 and is operable in cooperation with Adder 80 to perform addition or subtraction depending on the direction of transfer of the data.
The above-mentioned SAY DA registers 71, 73 are respect lively provided with not only a function to receive the data established by Register Data Bus 43 therefrom but also a function to load the data from TRAM Address Bus 36 therein.
Next, an NO register 61 is used to hold the number of the transfer data in a horizontal direction (an X coordinate direction), and an NY register 63 is dedicated to holding the number of the transfer data in a vertical direction (a Y
coordinate direction). Horizontal Direction Flag 60 point out a positive direction (a right direction) when it is "O", aye while it indicates a negative direction (a left direction) when it is "1". Vertical Direction Flag 62 points out a positive direction (a downward direction) when i-t is "O", while it indicates a negative direction (an upward direction) when it is "1".
The above-mentioned TRAM address bus 36, which is include Ed in Display Control Circuit 3, is connected via a buffer 55 to an address line 56 of VRAM4. A TRAM data bus 35 also in Display Control Circuit 3 is connected via a buffer 53 to a TRAM data line 54.
An S register 34 is used to hold the read data from the source area S, while a D register 52 is dedicated to holding the read data from the destination area D. An ALUM (arrhythmia-tic and logic unit) 51 is adapted to preform logical opera-lions, such as IMP, AND, OR, ERR, NOT operations, on the out-puts of S Register 34, Color Code Register 34 and D Register 52 in accordance with the control from Video CPU47.
The foregoing components constitute the characteristics of the invention, although other components are still present in Display Control Circuit 3. Ivory, such components as not necessary in explaining the operation of -the invention are not described in this specification.
reactuate, we will describe the operation of the above-men-1 }

toned embodiment of the invention.
The operation of Display Control Circuit 3 will be disk cussed here by talking as an example the transfer of a block data using the X, Y coordinates in case where the logical transverse widths of the source area S and destination area D are different from each other.
It is necessary for CPUl to have previously set inform motion necessary for transfer of the block data in the rest pective registers. When accessing each of the registers, CPUl first sets the register number of a register to be act cessecl in Register Pointer/Counter 44, and thereafter per-forms its write operations on a series of data.
When such block data as shown in Fig. 3 is to be trays-furred, a physical address SPA at a start point of the source area S is set in SPA Register 71 and a physical address DA at a start point of the destination area D is set in DA Register 73. Here, SPA Register 71 is composed of SAL (register #30), SAM (register ~31) anal SARI (register #32), while DA Register 73 is composed of DUAL (register #35), DAM (register ~36) end DAIS (register ~37).
In other words, CPUl sets 6-byte parameters regarding the physical addresses SAY DA at the start points of transfer, that is, at the respective start points of the source area S

and the destination area D.
At the same time, the source-side area width SW is set in SW Register 72 and the destination-side area width DO is set in DO Register 74. Here, SW Register 72 is composed of SOL (register #33) and SUE (register #34), while DO Register 74 is composed of OWL (register #38) and DOW (register #39).
Now, Fig. 5 illustrates the contents of the registers #30 - 39, and Fig. 6 illustrates the con-tents of the aegis-lens #40 - 46.
Then, the number of the data to be transferred in a horizontal direction (an X coordinate direction), NO, is set in NO Register 61 and the number of the data to be transfer-red in a vertical direction (a Y coordinate direction), NY, is set in NY Register 63. NO Register 61 is composed of NIL (register #40) and NXE-I (register #41) and NY Register 63 is composed of EIYL (register #42) and NOAH (register #43).
Since the block data to be transferred is in -the positive direction with respect -to both of the X, Y directions when viewed from the start point SAY "0" is set in both Direction X Flag 60 and Direction Y Flag 62. Direction X Flag 60 eon-responds to the bit 2 of an argument register ARGO (register #45), while Direction Y Flag 62 corresponds to the bit 3 of an argument register AGREE (register #45).

1~4571.~

The above-mentioned setting operations complete the setting of parameters necessary to transfer the bloclc data.
These parameter settings are performed successively from Register #30 to Register #45. First, "30" is set in the register pointer/counter 44. Then, simply by writing the parameter data successively, the associated registers can be set sequentially. Thereafter, Register Pointer/Counter 44 points out #46 and waits for the setting of a command code.
Fig. 7 illustrates a table of command codes. In this figure, "VDC" stands for the display control circuit 3.
Fig. illustrates a table of logical operations. In this figure, SC designates a source color code, while DC
represents a destination color code.
CPUl creates a command code such as "Lowe" in accordance with the above-mentioned command codes and logic eel operation codes, and then sets it in Command Register 46 (register #46).
The higher 4 bits of the above-mentioned command code are a command to transfer a bloclc data within VRAM4 when the source area S and the destination area D are both present within VRA1l4. The lower 4 bits of the same command code are a logical operation code and then "0000" is a code indicating lZ2'~57 that the source color code data as it is provides the desk Tunisian color code data.
On receiving a command code from CPU 1, Video CPU 47 sets the command executing (Of) of the bit 7 of SO Register 48 and initiates an executing processing of the command.
We, first, describe a case where a color code data is read out from the source area S within VRA~l4.
The physical address SPA at the above-mentioned start point is found by the following equation and is set in SPA
Register 71:
SPA = SUB + SO + STY x SW (1) , where SUB expresses the base of the start point and (SX,SY) expresses the coordinates of the start point.
Next, under control of Video CPU 47, Base Value Selector 75 is operated, SPA register 71 holding the physical address SPA of the start; point of the source area S is selected, and the physical address SPA is forwarded to Adder JO. Similarly, Valuation Value Selector 76 is operated, IT Counter 64 is selected, and the value of NO Counter 64 is forwarded to Adder JO.
In this case, if the it source address is expressed as Sue), then this source address Sue) can be obtained by the following equation:

~4574 SPA it = SPA + i (Z) , where i is a value that can be increased from 0 up to Nil or the value i of NO Counter is increased one by one for each 1 dot transfer, and when a line of transfers in the source area S have been completed, i becomes NO to clear NO Counter.
Then, the value of SPA Register 71 is updated in the lot-lowing manner. Namely, Base Value Selector 75 selects the value of SPA register 71, Variation Value Selector 76 selects the value of Do Register 74 and Adder 80 adds these values, and outputs them to VRAr~ Address Bus 36. Further, Video CPU
47 controls the added value so that it can be loaded into SPA
Register 71. Accordingly, the next source address SPA (0, 1) can be obtained in the following equation:
SPA (0, 1) = SPA + SW
here again, NO Counter 64 is counted by 1 each time 1 dot is transferred, and, if its value is expressed as i, then the source address SPA (i, 1) can be found from the following equation:
SPA (i, 1) = SPA + 1 x So + i (3) The value i in the equation (3) is identical with the above-mentioned i, and 1 in the equation (3) indicates that 1 line has been advanced in the source area S, which can be expressed generally by the following equation:

1~4S~

SPA (i, j) = SPA + j x SW + i (4) The value j in the above equation (4) can be found from the amount of displacement off from the coordinates of the start point in the vertical direction.
In other words, the address at the start point is found from the above equation (l); the following addresses in the first line can be respectively given by the equation (2);
when all of the addresses present in the first line have been completely transferred, then NO Counter 64 is cleared; address-en stored in the second and its following lines are generally given by the equation (4); and, each time the transfer of each of the lines is completed, the value i is counted 1 and the execution is handed over to the lower or following line.
The above processing are then repeated.
In accordance with the respective addresses obtained in the above manner, data is read out from the operation table area within VRAM4. The reedit data is set via Data Line 54, Buffer 53 and TRAM Data Bus 35 into S Register 34.
On the other hand, the color code data that is held in S Register 34 and is read out from the source area side is outputted via ALUM 51, TRAM Data Bus 35 and Buffer 53 onto VRAr~l Data Line 54 and is then written into the display area within VRAM4. Procedures for creating the write address in 2.;245~4 this case are similar to those for creating the address read out from the above-mentioned source area.
In other words, here, DA Register 73 is used instead of SPA Register 71, DO Register 74 is employed in place of SW
Register 72, and a base Do and coordinates (DO, DYE are set up instead of the base SUB of the start point of the source area S and the coordinates of the start point (DO, DYE); however, the procedures for deducing the above-mentioned equation (4) from the above-mentioned equation (1) are the same as above.
In the foregoing operations, termination of both of reading of 1 dot from the source area S and writing of 1 dot into the destination area D completes the data transfer of 1 dot information.
In the above discussion, since "O" is set in Direction X Flag 60 and Direction Y Flag 62, in horizontal-direction and vertical-direction processing, 2's Complement Operation Circuit 81 is requested to perform no operation and an addition is executed in Adder 80.
Accordingly, on completion of transfer of the 1 dot information, Video CPU 47 counts up NO Counter 64. And, when all of the information contained in a line is completely transferred, NY Counter 65 is counted up by Video CPU 47.

' r ' r -14 If "1" is set in Direction X Flag 60 and Direction Y Flag 62, then in the horizontal-/vertical-direction processing 2's Complement Operation Circuit 81 is requested to execute a complement operation and the resultant values are added in Adder 80, that is, a subtraction is executed.
For each transfer of the 1 dot information, the contents of NO Counter 64 and NO Register 61 are compared by Comparison Circuit 66, and, if they are not identical with each other, then the data transfer can be repeated in a procedure similar to the above-mentioned one. When the contents of NO
Register 61 and NO Counter 64 are identical, then NO Counter 64 is to be cleared.
hen the contents of NO Register 61 and NO Counter 64 are identical with each other and when the contents of NY
Register 63 and NY Counter 65 are compared by Comparison Circuit 67 and found identical with each other, then a total of (NO x NY) pieces of block data have been transferred, where NO expresses the number of the X coordinate-direction block data and NY expresses the number of the Y coordinate-direction block data.
On detecting the coincidence of the contents of NO
Register 61 with NO Counter 64 and the coincidence of the contents of NY Register 63 with NY Counter 65, Video CPU 47 12~ ~5'7~

decides that the bloclc data transfer has been completed, clears the command executing (Of) bit of SO Register 48 and notifies CPUl of the completion of the block data transfer.
Although in the above description the command code was set in Command Register 46 as "10010000", if the lower 4 bits L03 - L00 are used to specify the logical operations illustrated in Fig. 8, then ALUM 51 can function to execute the logical operations between S Register 34 and D Register 52.
In the above-mentioned description, although the block data transfer employing the X, Y coordinates within TRAM 4 was referred to, block data transfer from CPUl to TRAM 4, from VRAM4 to CPUl, and from Display Control Circuit 3 to VRAM4 can also be executed in a similar manner to the above.
Accordingly, such block data transfer will be discussed here-in below.
(1) When the block data is to be transferred from CPUl to TRAM 4, that is, when the command codes CM3 - CM 0 are "1011" :
In this case, the source is CPU 1, SPA Register 71, SW
Register 72 and S Register 34 are not used, but Color Code Register 33 is used instead of them.

Specifically, when CPU 1 sets a block of data to be transferred in Color Code Register 33, then Video CPU 47 writes the block data to be transferred in Color Code Register 33 into TRAM 4 in accordance with DA Register 73 and DO
Register 74. After then, Video CPU 47 sets the transfer ready (TRY) bit of SO Register 48 and notifies CPU 1 that the transfer of 1 piece of block data is completed and that the next block data can be accepted.
On confirming that the TRY bit is "1", CPU l sets the next transfer data in Color Code Register 33. This resets the TRY bit to return to its original status. Other operations to be performed in this case are similar to those mentioned above in the case when the block data within TRAM 4 is transferred.
(2) When the block data is to be transferred from TRAM 4 to CPU 1, that is, when the command codes CM3 - COO
are "1010":
In this instance, since the destination is CPU 1, DA
Register 73, DO Register 74 and S Register 34 are not used, but Color Code Register 33 is used instead of them.
Video CPU 47 reads out the transfer data from TRAM 4 in accordance with SPA Register 71 and SW Register 72, sets it in Color Code Register 33, and also sets the TRY bit of SO

I

~egister48 for "l". CPUl checks the status of the TRY
bit and, if it is found "l", then it reads out a piece of bloclc data from Color Code register 33. This resets the status of the TRY bit to return to its original status.
Other operations required in this case are similar to those mentioned above in the case in which the block data within VRAM4 is transferred.

(3) When the block data is to be transferred from Display Control Circuit to TRAM 4, that is, when command codes CM 3 - COO are "loo":
In this case, the data written into Color Code Register 33 is transferred to the destination area of VRAM4. This way is effective in writing the same data. The procedure necessary in this case is similar to those in the above-men-toned transfer of the block data from CPU l to VRAM4. How-ever, CPU l needs writing the block data in-to Color Code Register 33 only once, while the transfer of the block data is executed under control of Video CPU47.
Although the foregoing description has been made on condition that the color code or color data is to be treated, the invention can also apply to a monochromatic system and in this case the above-mentioned color code or color data can be replaced with the byte data.

Sue The present invention can be effectively used to per-form a display control operation for not only the color CUT
but also other display units such as a monochromatic CUT, ID plasma, EL and the like.
As disclosed herein before, according to the invention, since even when the logical transverse width of -the destine-lion area is different from that of the source area most of the display operations to be processed by the software can be processed by -the hardware in terms of time, the display memory access can be speeded up with smaller amounts of the necessary hardware increased for this purpose. The invention is also effectively used in a system in which a display memo-rye is not separated from a main memory. Further, it is quite clear that the above-mentione(l effect of the invention can also be applied to data transfer in -the main memory.

Claims (8)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An inter-logical-area data transfer control system in a memory unit comprising a display plane logically comprising:
first means for specifying a transfer start point of a source area; second means for specifying a transfer start point of a destination area; third means for holding amounts of data to be transferred in a horizontal direction; fourth means for holding amounts of data to be transferred in a vertical direction; and, fifth means for providing the logical transverse width of said source area and the logical transverse width of said destination area separately, characterized in that a plurality of data of said source area specified by said first, third and fourth means are read out from said memory unit and are sequentially written into said destination area so as to achieve transfer of said data be-tween said source and destination areas.

2. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that said memory unit is a display memory.

3. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that said source area or said destination area is a main memory and said reading and writ-ing of said data is performed in response to read and write data held in a single data register.

4. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that said source area is a data register included in said data transfer control system.

5. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that a register pointer for setting up command parameters is provided with a count function for counting the content in said register pointer one by one and is capable of successive settings for setting up the contents of said command parameters.

6. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that there is provided means for holding each of horizontal and vertical transfer directions of transfer points, and that said transfer directions comprise direc-tions in which, when said destination and source areas are super-posed on each other, said data is to be transferred in the order that said data within said source area is not rewritten before the transfer of said data.

7. The inter-logical-area data transfer control system as defined in Claim 1, characterized in that said inter-area data transfer is performed by means of logical operation means which logically operates on said data of said source area and said data of said destination area.

8. An inter-logical-area data transfer control system in a memory unit comprising a display plane logically comprising:
first means for specifying a transfer start point of a source area;

second means for specifying a transfer start point of a destination area; third means for holding amounts of data to be transferred in a horizontal direction; and, fourth means for holding amounts of data to be transferred in a vertical direction, characterized in that a plurality of data of said source area specified by said first, third and fourth means are read out of said memory unit and are sequentially written into said destination area so as to achieve inter-area data transfer.