WO1995001629A1

WO1995001629A1 - Image processing device and method therefor, and game machine having image processing part

Info

Publication number: WO1995001629A1
Application number: PCT/JP1994/001066
Authority: WO
Inventors: Seiichi Kajiwara
Original assignee: Sega Enterprises, Ltd.
Priority date: 1993-06-30
Filing date: 1994-06-30
Publication date: 1995-01-12
Also published as: EP0660298A4; KR950703188A; CN1111463A; EP0660298A1; BR9405494A

Abstract

In an access circuit (31) of a background picture generating part (22), cycle patterns are stored in an access register (40). Access commands read out are converted into control signals by a decoder (41). Addresses on a VRAM (12) which are assigned to necessary image data are generated by an address selector (42), and are fed to the VRAM (12). The image data are read from the VRAM (12) according to the control signals and the addresses, and they are stored in registers (33-36). Image data are read from the registers (33-36) by output circuits (37, 38), and picture element data are generated and outputted from the output circuits (37, 38). Thereby, alteration of the cycle patterns of the VRAM access can be treated flexibly which are resulted from alteration of display setting such as of the number of colors of the image data, the reduction ratios and the access frequencies. Further, according to the quantities of the image data and the access frequencies of the respective background pictures, the storages of the image data can be adjusted between a plurality of the VRAMs.

Description

Specification

TECHNICAL FIELD The present invention relates to an image processing apparatus and method, and a game machine having an image processing unit.

The present invention relates to an image processing circuit for generating a background screen in an image processing apparatus.

[Background Art]

2. Description of the Related Art Conventionally, images displayed on a raster scan type monitor in a video game or the like generally include a background image (moving image) composed of characters and the like appearing in the game, usually over a plurality of background images (still images) displaying the background. It has a combined configuration. Each of these background and foreground images has a priority set for output (hereinafter, priority). If they overlap, only the image with the highest priority is displayed. The priority is usually determined by a predetermined number, and an image with a larger number is displayed closer to the image. The pick-up is normally specified in units of planes in the background image, and is specified in units of characters in the foreground image.

For example, in FIG. 10 (a), there are a foreground picture FG, two background pictures BG0 and a background picture BG1, and the number indicating priority is “6” in the character CHR of the foreground picture FG, and “2” in the background picture BGO. , BG 1 is "4". When these are superimposed, it appears that the character CHR, the background image BG1, and the background image BGO are in the foreground. As described above, the background image forming the background image and the foreground image forming the foreground image are superimposed in a predetermined order at the same timing, so that the image is viewed on the monitor screen as shown in FIG. 10 (b). The whole image is output.

[Conventional image processing device]

As an image processing apparatus for outputting a background image and a foreground image as described above, an image processing apparatus shown in FIG. 11 is conventionally known. In FIG. 11, a video processor 2 is connected to a CPU 1 via a CPU interface 5, and a video processor 2 is connected to the CPU 1. The CRT 2 is connected to a CRT display 16. The CPU 1 is connected to a storage device 3 typified by a CD-ROM or a ROM cartridge, and a RAM 4 serving as a workspace of the CPU 1.

The storage device 3 contains a program for executing a game and image data for displaying a game screen. This image data is composed of the smallest unit called a picture (Vixel), and a color code of a predetermined number of bits that specifies the color at the time of output as information and a priority code that indicates the priority of the output Contains. The storage device 3 further includes data for designating when and at which coordinate position on the screen audio data and image data are to be displayed, data for designating rotation, movement, enlargement and reduction processing, and the like. I have. The CPU 1 reads these data from the storage device 3 to the RAM 4 and transfers the data to the video processor 2 via the CPU interface 5.

The video processor 2 includes a synchronization circuit 11. The synchronizing circuit 11 generates a synchronizing signal synchronized with the scanning of the CRT display 16 and supplies the synchronizing signal to each component in the video processor 2 in order to synchronize the output of the foreground image and the background image. Can be Along with the synchronization signal, the foreground image data is transferred to the foreground image processing unit 6 and the background image data is transferred to the background image processing unit 7 under the control of the CPU 1.

A command RAM 8 and a frame buffer 9 are connected to the foreground image processing unit 6. The command RAM 8 temporarily stores the foreground pattern image data of the transferred characters and the like. Further, the command RAM 8 stores commands issued from the CPU 1 when the game program is executed, for example, in a table format. The foreground image processing unit 6 reads these commands from the command RAM and registers them in an internal register for execution. Further, image data is read out from the command RAM8, subjected to image processing such as coordinate calculation, enlargement / reduction, color calculation, etc., and written into a predetermined address of the frame buffer 9. The foreground image data developed on the frame buffer 9 is sequentially output to the priority circuit 12 for each frame.

The image data of the background image transferred to the background image processing unit 7 is stored in a video RAM (hereinafter, referred to as a video RAM).

VRAM) is stored in 10. The background image data includes pattern data And pattern name data. As shown in Fig. 12 (a2), the pattern data is based on a cell as shown in Fig. 12 (a1) consisting of, for example, eight pixels in the horizontal and vertical directions. It is a collection of the color codes of each pixel in the box. The pattern name data is data including an address of the pattern data on the background image. As shown in FIG. 12 (b), the background image is composed of a set of predetermined cells, and the pattern name data indicates the positions of the cells on the background image stored in the VRAM 10 by the cells. It is specified by the start address on VRAM.

Referring back to FIG. 11, if necessary, the background image processing unit 7 performs coordinate calculation based on an instruction from the CPU 1, performs image processing such as up / down / left / right movement and rotation, and then performs the above-described image processing. Data is read from VRAM10 and transferred to priority circuit 12 for each background image.

The priority circuit 12 determines the priority of the output of the image data of the sprite and the background image transferred from the foreground image processing unit 6 and the background image processing unit 7, and outputs the image data having the higher priority. The foreground image and the background image are combined and transferred to the colorization circuit 13.

The color RAM 13 is connected to the colorization circuit 13. The color code of the image data transferred from the priority circuit 12 designates a specific address, and specific color data is read from the color RAM 14 based on the address. This color data is converted to RGB data indicating the mixing ratio of the three primary colors (red, yellow, and blue), and transferred to the video signal creation circuit 15, where the digital signal is converted to an analog signal by a DZA converter. The video signal is converted into a video signal and output on a CRT display 16 typified by a standard TV monitor.

[Access circuit and VRAM access in background image processing unit]

In the video processor 2 described above, the background image processing unit 7 performs a process of reading image data of a background image from the VRAM 10. Also, a process of writing the image data of the background image to the VRAM 10 is performed. These operations are called VRAM access, and are usually controlled by an access circuit 17 included in the background image processing unit 7. Hereinafter, this VRAM access will be described. Specifically, VRAM access is performed when image data is read from VRAM when displaying a background image, and when new image data supplied from the CPU is written to VRAM.

For VRAM access, "image data read access" to read image data stored in VRAM, "CPU access" to write new image data from CPU to VRAM, and parameters required for image display stored in VRAM There are "parameter overnight read access" and so on.

“Image data read access” is performed during the display period, and reads image data from the VRAM by designating a predetermined access operation. These access operations specify the reading of pattern name data in VRAM.

There is a “pattern name read” and a “pattern data read” that specifies reading of pattern data.

These access operations and the number of “CPU accesses” performed during the display period can be set as the contents of VRAM access per unit time according to predetermined restrictions.

As shown in Fig. 13, the unit time of VRAM access is usually the time to output one column (8 pixels) in the horizontal direction of one cell, and this is one cycle. The access circuit sets one access for the output time of one pixel, and performs eight accesses to VRAM within one cycle. The contents of the VRAM access for eight times in one cycle are called a cycle pattern. The access circuit controls the access to the VRAM during the display period by selecting an address of the predetermined image data in the VRAM based on the cycle pattern and supplying the selected address to the VRAM. For CPU access set during the display period, the specified number of write access times is secured. Hereinafter, an example of VRAM access based on such a cycle pattern will be specifically described with reference to FIG. 14 in a case where two background images BG0 and BG1 are used.

[Conventional example of VRAM access]

FIG. 14A shows the cycle pattern of the access circuit 17 in the background image processing unit 7 in FIG. 11 in the form of a table. In Fig. 14 (b), It shows the data structure stored in the VRAM 10 connected to the VRAM. Here, a cycle pattern for reading image data is set in advance in the hardware. During the display period, the access circuit 17 reads the pattern name data (PND) of the background image BG0 in the first access according to the cycle pattern. Conventionally, the access circuit 17 designates to the VRAM 10 a selection signal indicating the address in the VRAM 10 of the pattern name data of the background image BG0 in accordance with the designation of the CPU. Then, the pattern name data for the background image BG0 is read from the VRAM 10 based on the address.

Normally, such access can read one word (16 bits) of image data at a time. As shown in Fig. 14 (c), the pattern name data has a 16-bit structure including the head address of the background screen of the pattern data (cell unit). Therefore, if the BGO pattern name data is read out by one access, the head address of the pattern data of one cell on the background image BG0 can be obtained.

Based on the head address of the pattern data obtained in this way, the access circuit

At the second and subsequent accesses, the pattern data (PTD) of the background image BG is read according to the cycle pattern. That is, the pattern data specified by the head address is read for a horizontal column (8 pixels) of cells. Now, assuming that the background images BG0 and BG1 each have one word of pattern data that is read in one access, and that they contain a color code for four pixels, the same pattern data is required to read eight pixels. Two accesses are required. Therefore, at the second and third accesses, the pattern data of the background image BG0 is read for two words.

Next, for the background image BG1, the pattern name data (PND) is similarly read at the fourth access to obtain the leading address of the pattern data of the background image BG1. In the subsequent fifth and sixth accesses, pattern data (PTD) for 2 bytes is read from VRAM based on the start address. By repeating the first access to the sixth access, the image data of the background images BG0 and BG1 are sequentially read in the horizontal direction at the cell level according to the cycle pattern during the display period. Will be done. In the cycle pattern shown in Fig. 14, a new image data supplied from the CPU is sent to the VRAM during the display period as the 7th and 8th accesses of one cycle (8 times). CPU access for writing is set. In this case, the address of the image data to be written is supplied from the CPU to the VRAM 10. The image data written in the VRAM by the CPU access during the display period is read at an appropriate timing according to the above-described readout procedure of the image data in the cycle pattern. As a result, the background image can be rewritten during the progress of the game, and the background image can be changed.

As described above, the cycle pattern in the access circuit specifies (1) the timing and number of access operations specified during the display period, and (2) the CPU access during the display period as the contents of access within a unit time. I do. Conventionally, a method has been adopted in which this cycle pattern is set in advance in hardware. In other words, a plurality of cycle patterns are fixed as a model in the hardware in a predetermined data format, and according to the specification of the CPU, one set of optimal data is selected from these.

[Changes in image data volume and changes in the cycle pattern of VRAM access] In recent TV games, there is an increasing tendency to place greater emphasis on the visual effects during play as well as on the storylines of the game. Along with this trend, in order to stimulate the player's interest in the game, dynamic changes such as movement and rotation, and size changes such as enlargement / reduction are complicated in the background image display, and various colors are used. It is essential to devise ways to provide more beautiful images using colors. As a measure as described above, set more detailed display-related conditions, such as reducing the number of background images used and changing the number of colors and display magnification for each background image. Has been done. However, on the other hand, if the setting of these conditions becomes complicated, the amount of information held by the background image data may be significantly increased.

For example, as shown in Fig. 15 (a), in the two background images BG0 and BG1, the background image BG0 uses 16 colors and displays only the color characters such as the score, and the background image BG In 1, it is assumed that a gorgeous color background image is displayed using 256 colors. In this case, the color code per pixel of the pattern data is the color code in the color RAM. To specify data, 16-bit background image BG0 requires 4 bits, and 256-color background image BG requires 8 bits. As the number of colors used increases, the amount of data per pixel increases and the amount of information (number of bits) of pattern data also increases.

The increase or decrease of the information amount of image data as described above affects the setting of the VRAM access cycle pattern. In FIG. 15 (b), the color codes for each pixel in the pattern data are 4 bits and 8 bits for the background images BG0 and BG1, respectively. When 1-word pattern data is read out by one access in the cycle pattern, one word (16 bits) contains the color code of 4 pixels in the background image BGO, while the background image BGO contains the color code of 4 pixels. Image BG1 contains only two pixel color codes. Therefore, in order to read a predetermined amount of pattern data (for 8 pixels in the horizontal row of cells), in the cycle pattern, only two access times are required for the background image BGO, but for the background image BG1, four access times are required. Time setting is required, and more access time is required. As described above, when the information amount of the image data increases or decreases, it is necessary to change the setting of the cycle pattern accordingly.

[Increase image data amount and VRAM capacity setting]

As described above, when the amount of information of the image data is large, in addition to changing the cycle pattern, conventionally, the following measures have been taken. In other words, in VRAM access, multiple independent VRAMs are connected to the background image processing unit and each VRAM is assigned to each background image as a device to read as much image data from the VRAM as possible in one access. Therefore, there was a method to access all of these VR AM at the same time. There has also been a method in which a single VRAM is divided into portions called banks, and each portion is assigned to each background image, and these portions are simultaneously accessed.

However, the above-described conventional technology has the following problems. As described above, in order to improve the image representation of the background image, if various conditions for display such as the number of colors to be used are set in detail, changes such as the number of accesses in the VRAM access cycle pattern Occurs. In such a case, the conventional access method generally employs a method of selecting an optimal combination from a plurality of setting conditions assumed in advance. For example, a method was used in which a specific data format representing a cycle pattern to be a model was given a unique number and registered in a registry, and this number was designated by the CPU.

However, this has a problem in that the number of combinations increases as the number of scroll planes, the number of colors, and the types of settings, such as reduction, increases, which complicates the operation. In addition, instead of selecting from assembling, it was also possible to adopt a method in which the optimum pattern was determined by the door, but this would increase the circuit scale and put too much burden on the door There was a problem.

In addition, if the amount of information of the image data written from the CPU becomes large and the writing time is insufficient, the CPU is accessed as frequently as possible by making effective use of the free access time of the window during the display period. There is a need. However, in the conventional access circuit, since the determined access pattern is fixed, it has been difficult to flexibly increase or decrease the CPU access time as needed. As described above, in the conventional method of fixing the access pattern to hardware, there are many limitations in displaying a plurality of background images each having a unique display setting.

—On the other hand, VRAMs that store and read image data also have the following problems due to the fixed use of their capacity. In other words, when multiple VRAMs with the same capacity were installed, it was difficult to use all VRAMs efficiently. This example is shown using FIG. Two VRAMs, VRAM—A and VRAM—B, are assigned to background images BG◦ and BG1, respectively. Here, it is assumed that the background image BG1 is not displayed at all in the scene A of a certain game, but is displayed in a different scene B of the same game. In this case, in the scene A, the capacity of the VRAM-B for the background image BG1 is set in advance assuming that it becomes necessary, but is “necessary waste” that is not used. Also, if there is much image data of the background image BG0, VRAM-B cannot be used for the background image BG0. This was also the case when a single VRAM was divided into banks. Thus, in the conventional use of VRAM capacity, the image of each background There was no way to effectively adjust the VRAM capacity according to the amount of image data and the usage of the background image.

The present invention has been made in view of the above-described problems, and a first object of the present invention is to reduce the number of colors and the reduction ratio of image data and the frequency of access without reducing the burden on hardware. An object of the present invention is to provide an image processing method capable of flexibly changing an access operation within a unit time in VRAM access according to a change in display settings.

A second object of the present invention is to provide an image processing method capable of adjusting storage of the image data among a plurality of VRAMs according to the amount of image data of each background image and the access frequency.

A third object of the present invention is to provide an image processing method for realizing the second object not only between a plurality of VRAMs but also between banks of the same VRAM. A fourth object of the present invention is to make it possible to set and change the access operation within a unit time in VRAM access using the control of the CPU, and to output a background image having different display conditions differently. An image processing device is provided.

A fifth object of the present invention is to provide an image processing apparatus capable of sequentially and automatically executing access operations within a set unit time in VRAM access.

A sixth object of the present invention is to provide an image processing apparatus which generates and selects an address of image data on a VRAM by calculation in VRAM access, and gives the generated address to the VRAM.

A seventh object of the present invention is to provide an image processing apparatus having a mechanism for designating a predetermined operation in VRAM access and performing the operation quickly. An eighth object of the present invention is to provide an image processing apparatus which realizes the seventh object without imposing a burden on memory capacity.

A ninth object of the present invention is to provide an image processing apparatus having a specific mechanism capable of easily setting and changing the operation of VRAM access within a predetermined unit time.

A tenth object of the present invention is to provide an image processing apparatus having a specific mechanism for controlling the operation of VRAM access within a predetermined unit time by a CPU. A first object of the present invention is to provide an image processing apparatus having a specific mechanism for sequentially and automatically executing access to a VRAM.

A twelfth object of the present invention is to provide an image processing apparatus which easily realizes a mechanism for allocating VRAM capacity to image data and changing the same by controlling a CPU.

A thirteenth object of the present invention is to enable setting and changing of an access operation within a unit time in VRAM access using control of a CPU, and to output a background image having different display conditions differently. It is an object of the present invention to provide an image processing apparatus capable of performing the above.

A fourteenth object of the present invention is to provide a game machine capable of sequentially and automatically performing access operations within a set unit time in VRAM access.

A fifteenth object of the present invention is to provide a game machine which generates and selects an address of image data on a VRAM by calculation in VRAM access and gives the selected address to the VRAM.

A sixteenth object of the present invention is to provide a game machine having a mechanism for designating a predetermined operation in VRAM access and executing the operation quickly. A seventeenth object of the present invention is to provide a game machine which achieves the sixteenth object without imposing a burden on memory capacity.

An eighteenth object of the present invention is to provide a game machine having a specific mechanism capable of easily setting and changing the operation of VRAM access within a predetermined unit time. A nineteenth object of the present invention is to provide a game machine having a specific mechanism for controlling the operation of VRAM access within a predetermined unit time by CPU.

A twentieth object of the present invention is to provide a game machine having a specific mechanism for sequentially and automatically executing access to VRAM.

A twenty-first object of the present invention is to provide a game machine that easily realizes a mechanism for assigning VRAM capacity to image data and setting the change by controlling a CPU. DISCLOSURE OF THE INVENTION As means for solving the above problem, the invention according to claim 1 stores image data for forming a foreground image in a frame buffer and stores image data for forming a background image in a video RAM. By storing the image data for the foreground image from the video RAM in the background image processing unit while reading out the image data for the background image in synchronization with the reading of the image data for the foreground image from the frame buffer in the foreground image processing unit, In an image processing method of generating a picture and a background picture at the same timing, superimposing them, and outputting them as a composite image,

Specify the specific operation contents to be given to the video RAM for reading and writing the image data of the background image, set the specified operation contents for each predetermined unit time, and set this setting from the CPU. And accessing the video RAM based on the instruction from the CPU.

According to a second aspect of the present invention, there is provided an image processing method for installing at least one video RAM for storing image data of a background image, storing image data in each video RAM, and simultaneously accessing these video RAMs. ,

A video RAM; and a read content of image data stored in the video RAM.

It is characterized by being specified from the CPU.

According to the third aspect of the present invention, the video RAM according to the second aspect is divided into two banks, each of which is a plurality of RAM portions having the same capacity, and reading of each bank and image data stored in the bank is performed by C. It is specified from PU.

In the invention according to claim 4, the image processing device stores image data for forming a foreground image in a RAM, expands the image data in a frame buffer, and then uses the image data for a foreground image at a predetermined timing. Foreground image processing means for reading image data from the frame buffer; background image processing means for reading image data for forming a background image from a video RAM; and a foreground image image transferred from the foreground image processing means. Priority determining means for determining display priority between the data and the image data of the background image transferred from the background image processing means; and displaying the foreground image and the background image data according to the priority. Specifying means for performing an operation of reading or writing image data stored in a video RAM in an image processing apparatus having a display means for performing , The operations specified by the specifying means, when a predetermined unit Q First setting means for setting each operation, storage means for storing the content of the operation for each predetermined unit time set by the first setting means, and video based on the content stored in the storage means. Access control means for controlling access to RAM, and the number of bits for controlling output when the number of bits of predetermined data in the image data according to the amount of image data information that differs for each background image Output control means. In the invention according to claim 5, the access control means according to claim 4 includes: a conversion means for converting the designation by the designation means into a control signal; and an address of the image data read out from the VRAM on the VRAM, which is provided to the VRAM. Address selection means.

In the invention according to claim 6, the address selecting means according to claim 5 includes a first generating means for generating an address of the pattern data on the VRAM and a second generating means for generating an address of the pattern data on the VRAM. And a generation means.

According to a seventh aspect of the present invention, the image processing apparatus according to the fourth aspect includes, as image data of the background image, a pattern data including a predetermined number of pieces of pixel information and a background image of the pattern data constituting the image to be displayed. Access to the video RAM that stores the pattern name data indicating the position in the video RAM, and read out the image data. In the video RAM access, a designation that specifies the operation of reading or writing the pattern data or the pattern name data. As a means, an access command is used.

The invention according to claim 8 is characterized in that the access command according to claim 7 is a binary code having a predetermined number of bits.

According to a ninth aspect of the present invention, the image processing apparatus according to the seventh aspect is a video RAM access, wherein the operation specified by an access command is set in units of one cycle during a display period. It is characterized in that the cycle pattern is set in a form readable by the CPU.

According to a tenth aspect of the present invention, in the image processing apparatus according to the seventh aspect, in a video RAM access, a VRAM access register is used as storage means for storing the cycle pattern. In the invention according to claim 11, the image processing device according to claim 7 accesses the video RAM in a video RAM access according to an access command sequentially read from a cycle pattern stored in the access register. It is characterized by.

According to the twelfth aspect of the present invention, when there are a plurality of video RAMs storing image data or a plurality of video RAM banks, the image processing apparatus according to the fourth aspect determines whether or not the video RAMs are divided into banks. A second setting means for setting a plurality of storage means for each of the plurality of RAMs or the banks of the RAM, and an access means for simultaneously accessing the RAMs or the banks of the RAMs. It is characterized by having.

In the invention according to claim 13, the game machine stores image data for forming a foreground image in a RAM, expands the image data in a frame buffer, and then stores the image data for the foreground image at a predetermined timing. Foreground image processing means for reading from the frame buffer, background image processing means for reading image data for forming a background image from a video RAM, and image data of a foreground image transferred from the foreground image processing means. Priority determining means for determining the display priority between the background image data transferred from the background image processing means, and the foreground image and the background image data according to the priority. In an image processing apparatus having display means for displaying, specifying means for specifying an operation of reading or writing image data stored in the video RAM. First setting means for setting the operation specified by the specifying means for each predetermined unit time, and storage for storing the contents of the operation for each predetermined unit time set by the first setting means Means for controlling access to the video RAM based on the contents stored in the storage means; and bits of predetermined data in the image data according to the information amount of the image data which differs for each background image. Bit number output control means for performing control at the time of output according to the number of bits.

According to a fourteenth aspect of the present invention, the access control means according to the thirteenth aspect controls the designation by the designation means, a conversion means for converting into a symbol, and an image data read from the VRAM. Address selection means for supplying the address to the VRAM. In the invention according to claim 15, the address selecting means according to claim 14 includes: first generating means for generating an address of the pattern name data on the VRAM; and generating an address on the VRAM for the pattern data over time. And a second generation unit that performs the above. -In the invention according to claim 16, the game machine according to claim 13 includes, as image data of the background image, pattern data including a predetermined number of pieces of pixel information and a background image of pattern data constituting an image to be displayed. In the video RAM access for accessing the video RAM storing the pattern name data indicating the position of the image and reading the image data, the operation of reading or writing the pattern data or the pattern name data is performed. It is characterized in that an access command is used as a specifying means.

The invention according to claim 17 is characterized in that the access command according to claim 16 is a binary code consisting of a predetermined number of bits.

In the invention according to claim 18, the game machine according to claim 16 is characterized in that, in a video RAM access, the operation specified by an access command is set in units of one cycle during a display period. Is set in a form that can be read by the CPU.

According to a nineteenth aspect of the present invention, the game machine according to the sixteenth aspect is characterized in that, in the video RAM access, a VRAM access register is used as storage means for storing the cycle pattern.

According to an embodiment of the present invention, in the video RAM access, the game machine according to claim 16 accesses the video RAM according to an access command sequentially read from a cycle pattern stored in the access register. It is characterized by performing.

According to the invention described in claim 21, when there are a plurality of video RAMs storing image data or a plurality of video RAM banks, the game machine according to claim 13 determines whether or not the video RAMs are divided into banks. Specifying means 2 to specify

A plurality of storage means are allocated for each RAM or each bank of RAM, and access means for simultaneously accessing these RAMs or banks of RAM are provided. It is characterized by having.

The operation of the present invention having the above configuration will be described below.

To set the VRAM access cycle pattern, it is necessary to set the conditions for displaying image data for each background image. These conditions are, specifically, the number of colors used for each background image, enlargement / reduction setting, presence / absence of CPU access, setting of the storage location of image data required for each background image in VRAM, etc. is there.

Based on these conditions, the cycle pattern for accessing the VRAM for reading and writing image data is set for each installed VRAM. That is, the access commands required in one cycle, the number of accesses by these commands, and the access timing are determined.

According to the invention described in claim 1, a cycle pattern set in accordance with the above-described various conditions is prepared in software, a ROM, or the like, and the content is read into the CPU when the game is executed, and is designated and designated. Can be changed.

According to the second aspect of the present invention, it is possible to previously set predetermined image data to be stored in each VRAM, and to specify the reading of this image data by reading the image data into the CPU when the game is executed using the cycle pattern. it can.

The above processing can be set more freely by a programmer who is familiar with the contents of the game program, various data and various conditions used in the program, and the like. Therefore, appropriate conditions can be set, which is more efficient. Also, when changing these settings, it is only necessary to make changes to the software or ROM. Therefore, it is possible to easily change the access time and the use of the free space of the VRAM capacity. For this reason, unnecessary access time and unnecessary VRAM capacity, which are fixedly set in the window even if they are not used in some cases as in the past, can be saved.

As described above, according to the first and second aspects of the present invention, it is possible to flexibly cope with a change in the information amount of the image data and a change in the use state of the VRAM which change every scene during the progress of the game.

According to the third aspect of the present invention, the limited capacity of the VRAM can be more effectively used, and more image data can be read from the VRAM. First, image data Depending on the amount of information in the evening, you can choose to divide into banks or use one VRAM, so efficiency is high. Second, one VRAM is divided into multiple banks with the same capacity, and all of these banks are accessed simultaneously, so that a large amount of image data can be read. If the image data of each background image is assigned to each bank, the number of background images to be displayed simultaneously can be increased. Third, the use of settings based on the cycle pattern allows the number of banks or the number of banks to be allocated to image data to be freely adjusted, so that VRAM capacity can be reasonably allocated.

According to the invention described in claim 4, an image processing device that flexibly changes the cycle pattern in VRAM access as needed is realized. That is, the deciding means designates an access operation in the VRAM. Next, the first setting means sets the contents of the access operation performed within a predetermined unit time using the specifying means, and holds the set access contents in a form readable by the CPU. Let it. The read access content is stored in the storage means by the CPU. Further, the access control means controls VRAM access with reference to the stored access content. At this time, the output bit control means performs a sorting operation according to the number of bits of the image data in order to accurately output a plurality of background images having different information amounts of the image data. Thus, the image data of the same background image can be output collectively. According to the fifth aspect of the present invention, in the image processing apparatus, it is possible to obtain a mechanism for reading out the contents of the access operation from the storage means in the VRAM access and controlling the access according to the contents. That is, the information of the access content written in the storage means is divided into two types, designated image data type and designated read / write, and transmitted to VRAM synchronously from two different paths. . That is, the conversion means generates a read / write signal from the information of the access command, and instructs reading or writing of the designated image data. Then, the address selecting means selects the address of the designated image data in the VRAM, and supplies the selected address to the VRAM. The VRAM receives the address of the image data and the read / write signal, reads out the specified image data, and stores the image data in a predetermined data buffer. According to the invention of claim 6, in the image processing device, image data necessary for reading image data from VRAM or writing it to VRAM is provided.

Addresses in VRAM can be generated for each type of image data. That is, when the access command is “pattern name read”, the first generation means generates an address of the pattern name data on the VRAM, and supplies the address to the VRAM. When the access command is “pattern data read”, the second generation means generates an address of the pattern data read in the VRAM and supplies the address to the VRAM.

According to the invention described in claim 7, in the VRAM access of the image processing apparatus, a designation means representing each access operation such as reading or writing of pattern data and pattern name data as image data of a background image stored in the VRAM. And use a predetermined access command. As a result, each access operation can be represented simply, and setting and changing of these access operations can be easily specified.

According to the invention of claim 8, a code having a predetermined number of bits is used as an access command in the image processing device. Thereby, the memory capacity in the image processing apparatus can be saved. Further, since the command is read in the form of a binary code, the access operation can be executed more quickly.

According to the ninth aspect of the present invention, in the VRAM access in the image processing apparatus, a cycle pattern, which is a series of access operations set in units of one cycle during a display period, is used, for example, a CD-ROM or the like. Efficient batch settings can be made in a form that can be read by the CPU.

According to the tenth aspect of the present invention, since the cycle pattern in the image processing device is stored in the VRAM access register, reading and writing can be controlled by the CPU.

According to the invention of claim 11, in the image processing device, an automatic mechanism can be obtained in which the access circuit sequentially reads out access commands from the cycle pattern and smoothly executes the access commands.

According to the invention as set forth in claim 12, a specific image in which the VRAM capacity is used efficiently. An image processing device is realized. That is, the second setting means sets whether to divide the VRAM into banks. In this way, it is possible to determine whether to use the entire VRAM capacity or a part according to the amount of image data. In addition, the access means

Access VRAM or VRAM bank simultaneously. Specifically, for each installed VRAM or VRAM bank, a cycle pattern is set according to various display-related conditions, such as the amount of image data stored and the access frequency. This makes it possible to simultaneously display multiple background images, increase the amount of image data to be read, and achieve more efficient use of VRAM capacity.

According to the thirteenth aspect, a game machine that flexibly changes a cycle pattern in VRAM access as needed is realized. That is, the specifying means specifies an access operation in the VRAM. Next, the first setting means sets the content of the access operation performed within a predetermined unit time using the specified means, and reads the set access content into the CPU. To hold. The read access content is stored in the storage means by the CPU. Further, the access control means controls VRAM access with reference to the stored access content. At this time, the output bit control means performs a sorting operation according to the number of bits of the image data in order to accurately output a plurality of background images having different information amounts of the image data. Thus, the image data of the same background image can be output collectively.

According to the invention of claim 14, in the game machine, it is possible to obtain a mechanism for reading the contents of the access operation from the storage means in the VRAM access, and controlling the access according to the contents. That is, the information of the access content indicated by the access command written in the storage means is divided into two types, designated image data type and read / write designation, and synchronized from two different paths. Conveyed to VRAM. That is, the conversion means generates a read / write signal from the information of the access command, and instructs reading or writing of the designated image data. Then, the address selecting means selects an address on the VRAM of the designated image data, and gives this to the VRAM. The VRAM receives the address of the image data and the read / write signal, reads out the specified image data, and stores the image data in a predetermined data buffer. According to the invention of claim 15, in the game machine, an address on the VRAM for generating image data necessary for reading image data from the VRAM or writing the image data to the VRAM is generated for each type of image data. it can. That is, when the access command is “pattern name ♦ read”, the first generation means generates an address of the pattern name data on the VRAM and supplies it to the VRAM. When the access command is “pattern data read”, the second generation means generates an address of the pattern data read in VRAM and supplies it to the VRAM.

According to the invention of claim 16, in the VRAM access of the game machine, a designation indicating each access operation such as reading or writing of pattern data and pattern name data as background image data stored in the VRAM. As a means, use a predetermined access command. As a result, each access operation can be represented simply, and setting and changing of these access operations can be easily specified.

According to the seventeenth aspect, a code having a predetermined number of bits is used as an access command in the game machine. Thereby, the memory capacity in the image processing device can be saved. Further, since the command is read in a binary code format, the access operation can be performed more quickly.

According to the invention of claim 18, in the VRAM access in the game machine, a cycle pattern, which is a series of access operations set in units of one cycle during a display period, is read by a CPU, such as a CD-ROM. Can be set efficiently in a form that can be read.

According to the invention of claim 19, since the cycle pattern in the game machine is stored in the VRAM access register, the reading and writing can be controlled by the CPU.

According to the invention of claim 20, in the game machine, it is possible to obtain an automatic mechanism in which the access circuit sequentially reads out access commands from the cycle pattern and smoothly executes the access commands.

According to the twenty-first aspect of the present invention, the specific gain for efficiently using the VRAM capacity is provided. A one-time machine is realized. That is, the second setting unit sets whether to divide the VRAM into banks. With this, it is possible to determine whether to use the entire VRAM capacity or a part of the VRAM capacity according to the amount of image data. Further, the access means accesses the VRAM or VRAM bank simultaneously. Specifically, for each installed VRAM or VRAM bank, a cycle pattern is set according to various display-related conditions, such as the amount of image data stored and the access frequency. This makes it possible to simultaneously display multiple background images, increase the amount of image data to be read, and achieve more efficient use of VRAM capacity. [Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a background generation unit according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus according to the embodiment of the present invention. FIG. 4 is a block diagram illustrating a configuration of a scroll engine, FIG. 4 is a diagram illustrating a cycle pattern set in the present embodiment, FIG. 5 is a diagram illustrating a pattern name / address generation procedure in the embodiment of the present invention, FIG. 6 is a diagram showing a procedure for generating a pattern data address in the embodiment of the present invention, FIG. 7 is a diagram showing a procedure for generating pixel data in the output circuit of the present invention, and FIG. 8 is a reference example of the present invention FIG. 9 is a diagram showing the setting and setting of the access register and VRAM in FIG. 1, FIG. 9 is a diagram showing a change in VRAM capacity allocation in Reference Example 2 of the present invention, and FIG. 10 is a foreground image and background of the image processing device. FIG diagram showing the output procedure, FIG. 1 1, the conventional image processing apparatus O conceptual diagram, FIG. 12 (a 1) and (a 2) is representative of the configuration of the cell and the pattern data. Fig. 12 (b) is a diagram showing the cell position on the background image, Fig. 13 is a diagram showing the unit time (cycle) at the time of VRAM access, Fig. 14 is an explanatory diagram of VRAM access, and Fig. 15 is the color used FIG. 16 is a diagram showing a relationship between the number and the number of bits of a color code per pixel. FIG. 16 is a diagram showing a procedure for changing the allocation of VRAM capacity to image data. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of an image processing apparatus according to the present invention will be described with reference to the drawings. This embodiment is configured according to the table of contents shown below. Example of this Example Table of Contents>

1. Overall configuration of the present embodiment

1-1 Overall configuration of the image processing apparatus of the present embodiment

1-2 Configuration of background image processing unit in this embodiment

2. Function and effect of this embodiment

2-1 Setting display conditions

2-2 Cycle pattern setting

2-3 Function of this embodiment

2- 4 Effects of this embodiment

3. Other embodiments

3- 1 Reference Example 11

Access registerAddition of used VRAM

3-2 Reference example 2-Effective use of VRAM capacity

3-3 Action and effect

1. Overall configuration of the present embodiment

First, a configuration of an image processing apparatus including a background image processing unit of the present invention will be described below with reference to FIG. In the present embodiment, a display screen for a foreground image and a display screen for a background image for displaying an image formed from image data are assumed. Of these display screens, the screen for the foreground picture is called the split screen, and the screen for the background picture is called the scroll screen.

1-1 Overall configuration of the cool image processing device

FIG. 2 is a block diagram showing an embodiment of the image processing apparatus according to the present invention. In FIG. 2, a CPU 1, a RAM 2, and a video processor 3 are connected to a bus 14 whose usage right is controlled by a bus controller 13. Video processor 3 is composed of a split, engine 5, scroll engine 6, and DZA converter 7. The command engine 8 and the frame buffer 9 are connected to the split engine 5. The scroll engine 6 has a built-in color RAM 10 and various registers 11, and is connected to the VRAM 12. The settings related to the functions of the scroll engine 6 are damaged by the CPU 1 in the register 11. Related to this embodiment are a VRAM access register for storing a cycle pattern for controlling VRAM access during a display period, a register for specifying whether or not VRAM is divided into banks. A monitor 4 is further connected to the video processor 3.

The CPU 1 stores the game program read from an external storage device (not shown) such as a CD-ROM in the RAM 2 and stores the read image data for output together with the commands and instructions necessary for image processing along with the video processor 3 Transfer to In the video processor 3, the split engine 5, which is an image processing unit for the foreground,

The command for the foreground transferred from the CPU 1 is temporarily stored in the command RAM 8 as a command table. The command is read by the split engine, set in an internal system register, and executed. On the other hand, the command RAM8 also stores the foreground image data transferred from the CPU 1. The split engine 5 reads this image data from the command RAM 8, and performs image processing such as rotation, enlargement, reduction, and color calculation. After that, this image data is Write to a predetermined address on the frame buffer 9 to develop a foreground moving image. The image data of the foreground image FG in the frame buffer 9 is sequentially read out by the split engine 5 and supplied directly to the scroll engine 6 without passing through the bus 14.

Next, the configuration of the scroll engine 6 for forming a background image will be described with reference to FIG. As shown in FIG. 3, in FIG. 2, the image data of the split engine 5 is supplied to the scroll * engine via the terminal A. The scroll ♦ engine 6 includes a window control unit 21 for performing window processing on the split screen and the scroll screen, a background image generation unit 22 (described later) for processing image data of the scroll screen, and a display control unit 23. including. The display control unit 23 includes a priority circuit 24 and a colorization circuit 25. The display control unit 23 determines the priority of output for each pixel of the image data of the foreground image and the background image read by the background image generation unit 22, and synthesizes the images. Further, colorization of image data is performed by the connected color RAMI0. The image data thus processed is transferred from the terminal B to the DZA converter 5 in FIG. 2 together with the RGB data generated in the color conversion circuit 25. The image data is converted into an analog color video signal here and displayed on a display 4 typified by a standard TV monitor.

1-2 Configuration of background image processing unit of the present embodiment

In FIG. 3 showing the structure of the scroll engine 6 in the video processor 3, the background image generation unit 22 particularly includes various registers 11 that can be written by the CPU 1, and It is characterized by the ability to control RAM access and adjust the VRAM capacity allocated to image data. Of these, a VRAM access register is provided for controlling VRAM access during the display period, and the contents of one cycle of access (cycle pattern) executed during the display period of image data are written by the CPU. It is. Hereinafter, the configuration of the background image generation unit 22, which is the circuit of the present invention, will be described in detail with reference to FIG.

In FIG. 1, a background image generation unit 22 includes an access circuit 31 for controlling VRAM access, a synchronization circuit 32, and until the image data read from the VRAM is output. -Includes a data buffer (registers 33-36) for storing data, an image data output circuit (37, 38), and a coordinate calculation unit 39 for motion control such as vertical and horizontal movement and rotation of the scroll screen. It is connected.

The access circuit 31 includes a VRAM access register 40, a decoder 41, and an address selector 42. Terminal C is connected to CPU 1 and supplies commands from the game / program, image data, and address of image data.

The synchronization circuit 32 generates a horizontal and vertical synchronization signal synchronized with the scanning of the monitor 4 and a synchronization signal for each dot. These synchronization signals are supplied from terminal D to the split engine, and are also supplied to each part of the background image generation unit 22 via the coordinate calculation unit 39. As a result, the positions of the foreground image and the background image at the time of output coincide with the timing. Further, the synchronization circuit 32 generates an address signal of one dot (pixel) cycle and supplies it to the VRAM access register.

The pixel-based image data generated by the image data output circuits 37 and 38 in the background image generation unit 22 is output to the display control unit 23 in FIG.

2. Function and effect of this embodiment

The operation of the background image processing unit of the present embodiment having the above configuration will be described below.

2-1 Setting display conditions

In the access circuit 31 of FIG. 1, it is necessary to set the following conditions in advance before setting a cycle pattern for specifying the contents of a VRAM access within a unit time (one cycle). That is,

(1) Display conditions such as the number of scroll screens to be displayed, the number of colors used by each scroll screen, and reduction settings

(2) Allocation of VRAM capacity to store image data of each scroll screen — number of VRAM to be used, whether to divide into banks

(3) Whether to perform CPU access,

And so on. In this embodiment, the number of scroll screens to be displayed is BG0 and BG1, and the scroll screen BG0 uses 16 colors and the scroll screen BG1 uses 256 colors. Also, in these scroll screens, no reduction setting is made, and one VRAM is used without division in storing image data. Also, it is assumed that the scroll screen has no image change and does not require CPU access time.

2-2 Cycle pattern setting

After the above conditions are determined, the cycle pattern for VRAM access is set. As described above, in VRAM access, one access is performed within the output time of one pixel, and eight accesses, which is a time for outputting eight pixels in a horizontal row of cells, are set as a unit time (one cycle). In FIG. 1, the VRAM access register 40 in the access circuit 31 is divided into eight registers R1 to R8 each corresponding to one access time. In each embodiment, an access command is used in this embodiment as a means for designating each access operation. This access command is a 4-bit binary code that specifies which scroll screen image data to read. The cycle pattern is set by specifying this access command at an appropriate timing within one cycle.

Hereinafter, the contents set in the cycle pattern in the present embodiment will be described.

First, "BG0 pattern name / read" is set as the first access in order to read the image data relating to the scroll screen BG0.

Next, reading of the pattern data of the scroll screen B G0 is designated. The pattern data is a collection of a color code of a predetermined number of bits, which is information on the color of a pixel, among the information of each pixel, on a cell-by-cell basis. For example, if the cell is composed of 8 pixels vertically and horizontally, the pattern data contains 64 rows (8 x 8) of color code. When reading pattern data with VRAM access, the number of accesses increases or decreases depending on the amount of information in the pattern data. The amount of information of the pattern data is determined by various display conditions such as the number of color code bits per pixel included in the pattern data and the reduction ratio.

1 On the scroll screen BG0 using 6 colors, included in the pattern data The color code per pixel is 4 bits. Therefore, the 16-bit pattern data read in one access is equivalent to 4 pixels of color code. The predetermined amount of pattern data read in VRAM access is eight pixels (horizontal rows of cells). Therefore, in order to read pattern data on the scroll screen BG0, it is necessary to perform two consecutive accesses. Therefore, set "BG0 pattern data ♦ read" twice in succession.

Subsequently, “BG 1 pattern name / read” is set for the scroll screen BG 1 using 256 colors, and reading of pattern name data is designated. Next, in reading the pattern data, the color code per pixel contained in the pattern data of the scroll screen BG1 is 8 bits. Therefore, the 16-bit pattern data is equivalent to two pixels of the color code. Therefore, in order to read out the pattern data of a predetermined amount of 8 pixels, it is necessary to perform the access four times continuously. Therefore, set "BG 1 pattern data read" continuously.

The cycle pattern as described above is set in a form that can be read by the CPU. Examples of the setting means include a method of determining an optimal cycle pattern by a unique program, and a method of specifying a cycle pattern prepared in advance in a CD-ROM, a memory cartridge, or the like. The cycle pattern is read by the CPU from the setting means, and further stored in the VRAM access register 40 from the CPU. Figure 4 shows the cycle pattern stored in each register in the VRAM access register.

2-3 Function of this embodiment

Next, the operation of the access circuit that controls VRAM access based on the cycle pattern stored in the VRAM access register 40 as shown in FIG. 4 will be described below.

[Procedure 1] Read access command

First, the operation when reading the access command from the cycle pattern will be described. As described above, the VRAM access register 40 in FIG. 1 is composed of eight registers R1 to R8, and the synchronization circuit 32 transmits the address signal of one dot (pixel) cycle. Take it. This address signal is The addresses in the VRAM access register of each of the eight registers are sequentially indicated. The VRAM access register 40 sequentially reads the access command stored in each register specified by the address signal. Each read access command is decoded by the decoder 37, and a read / write control signal obtained by this is supplied to the address selector 42 and the VRAM 12.

According to the access command read from the VRAM access register 40 as described above, the address in the VRAM of the image data that needs to be read or written is selected and supplied to the VRAM. Hereinafter, the operation of generating the address of the image data supplied to the VRAM will be described in detail.

A. When the access command is "Pattern name ♦ Read"

If the access command read out in Procedure 1 is the “pattern name read” that reads out the pattern name data of each scroll screen, first the address of the specified pattern name data on VRAM12 (pattern name key) Dress) is generated. The pattern name address is generated by the following actions.

[Procedure 2] Generation of pattern name and address

In the coordinate calculation unit 39 in FIG. 1, the synchronization circuit 32 supplies a synchronization signal of (vertical and horizontal scroll screens BG0 and BG1 and a dot (pixel) cycle. For each of the scroll screens BGO and BG1, perform processing such as up, down, left, and right rotations, etc. Such processing is performed, for example, while the game is running, by viewing the state of the ground as viewed from above an airplane flying in the sky This is necessary when displaying the movement of an airplane by rotating or moving the background image while keeping the position of the airplane fixed, such as when displaying.

The coordinate calculator 39 assumes a scroll screen based on the pattern data (stored in the VRAM 12) and the pattern name data, and synchronizes the synchronization signal from the synchronization circuit 32 with the instruction of the CPU 1 received from the terminal C. The coordinates are calculated for each pixel according to. The coordinate value of each pixel on the scroll screen obtained in this way is called a pixel address.

As shown in Fig. 5 (a), this pixel address has, for example, 9 bits (XO -It has coordinate data consisting of X 8) and 9 bits of Y coordinate (ΥΟ-Υ8). The upper 6 bits (Χ3—Χ8, Υ3-Υ8) of these two coordinate data excluding the lower 3 bits (Χ0—Χ2, ΥΟ— 両 2) are shown in Fig. 5 (d). This is data that indicates the position of the cell on the scroll screen. Therefore, as shown in FIG. 5 (b), the data obtained by removing the lower 3 bits of the X coordinate and the Y coordinate from the coordinate data are combined to form a 12-bit pattern name address (X3—X8ZY3—Y8). Is generated and supplied to the address selector 42.

The lower three bits (X0—X2, Y0-Y2) of the XY coordinates in the pixel address coordinate data are, as shown in FIG. 5 (e), 0 or The combination of 1 codes gives 64 pixels in a 8x8 pixel cell.

Shows the X and Y coordinate values. Of these, the lower three bits (XO—X2) of the X coordinate representing the eight X coordinates セル in the cell contain the number of bits of the color—code of each pixel, as shown in Fig. 5 (c). Is added. Then, according to the number of bits of the color code, the image data output circuit 37 is used for the scroll screen BG 0 (color code 4 bits) in the case of the scroll screen BG 0 (color code 8 bits). If it is, it is supplied to the image data output circuit 38. The lower three bits (YO-Y2) of the Y coordinate are supplied to the address selector 42 as they are, and are used as data when generating the address of the pattern data.

[Procedure 3] Address selector—Specify read address 1

Returning to FIG. 1, the address selector 42 is supplied with the address of the VRAM12 from the CPU 1 via the terminal C together with the 12-bit pattern name and address provided by the coordinate calculator 39. ing. The address selector 42 accesses the VRAM 12 based on the address of the VRAM 12 and gives the pattern name address to the VRAM 12.

[Procedure 4] Reading VRAM-pattern name data

In the background image generation unit 22 in FIG. 1, the VRAM 12 is connected to a plurality of data buffers corresponding to the type of image data for each scroll screen. Of these, register 33 is the buffer for storing the pattern name data of scroll screen BGO, and register 34 is the pattern name data of scroll screen BG1. This is a buffer for storage. The VRAM 12 is supplied with the pattern name address from the address selector 42, and reads out the pattern name data based on the address. Also, in synchronization with this, the control signal from Deco

(Write), the read pattern name data is stored in register 33 if this is for scroll screen BG0, and to register 34 if it is for scroll screen BG1. Is done.

According to the procedure 1-4 described above, the access command “pattern name read” is executed in the VRAM access, and the pattern name data is read and stored in a predetermined data buffer.

When the reading of the pattern name data is completed, the access circuit 31

Reads the next access command based on the cycle pattern stored in M access register 40. In other words, the process shifts to reading out pattern data, which is color data for each cell, for output. The procedure when the access command moves to "Pattern data ♦ Read" is described below.

B. When the access command is “pattern data read”

If the access command read by procedure 1 is “pattern data read”, the address of the pattern data on VRAM 12 is given to VRAM 12 by the address selector to read the pattern data from VRAM 12. There is a need. The address is generated by the following operation based on the pattern name data read from the VRAM 12 by the above procedures 1-4.

[Procedure 5] Address generation of pattern data

At the time of reading the pattern data ♦, in FIG. 1, the decoder 41 supplies a control signal (read) to the registers 33 and 34. Upon receiving this control signal, the pattern name data is read out from the register 33 (when the scroll screen is BG0) or the register 34 (when the scroll screen is BG1), and is sent to the address selector. As shown in FIG. 6 (a), the pattern name data usually includes, for example, the lower 9 bits of the top address of the scroll screen (or VRAM 12) of the pattern data. The first address indicates which cell is to be read. Is specified.

Also, from the coordinate calculation unit 39, the lower 3 bits of the Y coordinate that specifies eight Y coordinate values in the cell among the lower 3 bits of the XY coordinate data from the pixel address generated in the procedure 2 (YO-Y2) Force Sent to address selector 42. The lower 3 bits of this Y coordinate specify the Y coordinate of the pixel in the cell.

As shown in FIG. 6 (b), the pattern data address is generated in a 12-bit form obtained by synthesizing the start address and the lower 3 bits of the Y coordinate. Thus, the pattern data address is responsible for specifying one of the eight horizontal columns in the cell. At this time, to the pattern data address, a predetermined number of bits indicating the number of times of the read access the pattern data specified by the address are added.

[Procedure 6] Address selector-read address specification 2

Referring back to FIG. The address selector 42 is supplied with the address of the VRAM 12 from the CPU 1 via the terminal C together with the 12-bit pattern data and the address of the pattern data generated in the procedure 5 on the VRAM 12. You. The address selector 42 accesses the VRAM 12 based on the address of the VRAM 12 and gives the VRAM 12 the pattern data address.

[Procedure 7] VRAM—reading of pattern data

In the background generation unit 22, a plurality of data buffers for pattern data are connected to the VRAM 12 for each scroll screen. Of these, registers

Reference numeral 35 denotes a buffer for storing pattern data of the scroll screen BGO, and register 36 denotes a buffer for storing pattern data of the scroll screen BG1.

The VRAM 12 is supplied with the pattern data address from the address selector 42, and reads out the pattern data based on the address. In addition, since the control signal (write) from the decoder 41 is given in synchronization with this, the read-out pattern data is transferred to the register 35 if this is the scroll screen BG0, and to the scroll screen. If it is BG 1, it is stored in register 36 respectively.

According to the procedure 5-7 as described above, the access command “pattern data read” is executed in VRAM access, and the pattern data is read out. Is stored in a fixed data buffer.

By the above procedure 117, the image data (pattern data) read from the VRAM 12 is reconstructed in the image data output circuit 37 or 38 into the form of pixel data which is information for each pixel. The operation at the time of pixel data output will be described below in detail with reference to FIG.

[Procedure 8] Pixel data output

The image data output circuits 37 and 38 output a control signal for specifying the number of bits of the color code of the pixel from the coordinate calculation section 39 for each scroll screen, and the lower three bits (X0—X) of the X coordinate of the pixel address. 2) have received When the control signal specifies 4 bits, two words (32 bits) of pattern data are read from the register 35 for the scroll screen BG 0 (using 16 colors) to the image data output circuit 37. . This is pattern data for 8 pixels in a horizontal row of cells read out by two accesses based on the cycle pattern. As shown in FIG. 7 (a1), the pattern data for these eight pixels is divided into eight (P0-P7) every 4 bits from the lower order. The lower 3 bits of the X coordinate select one of these 8-bit 4-bit data. That is, by selecting one X-coordinate value of the horizontal column, one of the eight pixels of the horizontal column is designated. Thus, the color code for one pixel in the pattern data is specified.

Also, as shown in FIG. 7 (b 1), the pattern name data of the scroll screen BG 0 is read from the register 33, and the upper 7 bits specifying the leading address of the color RAMI 0 in FIG. Is added to the selected 4-bit color code. In this way, a total of 11 bits of pixel-based color data is formed as shown in FIG. 7 (c1).

On the other hand, when the control signal specifies 8 bits, the image data output circuit 38 stores 4 words (64 bits) of pattern data from the register 34 for the scroll screen BG1 (using 256 colors). Is read. This is pattern data for 8 pixels in a horizontal column of cells read out by 4 accesses based on the cycle pattern. As shown in FIG. 7 (a2), the pattern data for these eight pixels is divided into eight (P0-P7) every eight bits from the lower order. The lower 3 bits of the X coordinate are Select one of the divided 8-bit data. That is, by selecting one X coordinate value of the horizontal column, one pixel of the eight pixels of the horizontal column is designated. In this way, the color code for one search in the pattern data is specified.

Also, as shown in FIG. 7 (b), the pattern name data of the scroll screen BG1 is read from the register 34, and the upper 3 bits designating the head address of the color RAM are replaced with the lower 3 bits of the X coordinate. Append to the 8-bit color code selected by the bit. In this way, a total of 11 bits of pixel-based color data as shown in FIG. 7 (c2) are formed.

The image data for each pixel formed as described above is output from the image data output circuit 37 or 38 to the priority order circuit 24 of the display control unit 23 in FIG. 3 via the terminal E or the terminal F. You.

2-4 Effects of this embodiment

As described above, in the access circuit of the present invention, an access operation in VRAM access is specified in a predetermined form called an access command. Then, a cycle pattern in which access commands for eight accesses in one cycle of the unit time are set is set so that it can be read by the CPU, and stored in a form that can be written from the CPU. Thus, in the case of changing the cycle pattern, it is only necessary to specify the access command rewriting operation from the CPU. In addition, it is possible to flexibly cope with a case where a VRAM access register is installed in correspondence with a plurality of VRAMs only by appropriately modifying and setting the access command from the CPU. As described above, the cycle pattern can be set more freely. For example, if the optimal number of colors and the like are appropriately adjusted for each scroll screen according to the display contents of each scroll screen, the amount of image data can be reduced. It can also be kept to a minimum. In this sense, the advantage is that the limited VRAM capacity can be used effectively.

3. Other embodiments

The present invention is not limited to the above embodiment. The present invention originally aims to freely set and change the display conditions of the scroll screen. Therefore, the present invention realizes an access circuit having a flexible configuration as required according to the original purpose. It is possible. Hereinafter, other reference examples will be described with examples. 3-1 Reference example 11--1 Setting of CPU access

Access Register and VRAM Configuration

For example, in the above embodiment, it is assumed that CPU access is required during at least one of the scroll screens BG0 and BG1 during the display period. In this case, in the above embodiment, a single VRAM is used, and all access contents for eight times in one cycle are used for reading image data. In such a case, in the access circuit of the present invention, a VRAM is provided as necessary, and an access register is added corresponding to each VRAM. Now, assuming that VRAM is allocated according to the image data of each scroll screen, as shown in FIG. 8, even in the scroll screen BG1 that uses a large number of colors, CPU access can be set within one cycle. Therefore, new image data can be written from the CPU during the display period. As described above, since the VRAM and the access register corresponding to the VRAM can be added as necessary, it is not necessary to fix unnecessary access time which is not used in some cases as in the related art. In this sense, there is an effect that the burden on the door is reduced.

3-2 Reference example 2-Effective use of VRAM capacity

In the above-described embodiment, 256 colors may be used for the scroll screens BG0 and BG1, or the number of scroll screens to be displayed may be increased. In this way, even when a large amount of image data needs to be read at once in VRAM access, it is necessary to allocate VRAM in advance or allocate it to each scroll screen by dividing the bank (see 2- 1 Refer to Display condition setting).

In the image processing apparatus of the present invention, not only can these multiple VRAMs and VRAM banks be accessed at the same time, but also the amount of image data held by each scroll screen, the difference in VRAM usage depending on the access frequency, and the like are considered in advance. Thus, the allocation of VRAM capacity for each scroll screen can be set freely from the CPU.

3-3 Action and effect

Hereinafter, examples of using the VRAM of the present invention will be described with examples.

[Example] There are three scroll screens BG0, BG1, BG2. With a game In scene A, the number of colors used in the scroll screen BG 2 is particularly increased. In another scene B of the same game, the scroll screen BG1 requires a lot of display changes; ', the scroll screen BG2 is not displayed at all.

In such a case, two VRAMs of the present invention are installed, and these are referred to as VRAM-1 and VRAM-2. As shown in FIG. 9, in the above-mentioned scene A, the setting of bank division is performed by dividing VRAM-1 into two equal parts. This is determined by the 1 bit in the register that controls the RAM. Then, the image data of the scroll screen BG0 and the scroll screen BG1 for scene A are stored in VRAM-1. Also, the image data of the scroll screen BG2 for scene A is stored in VRAM-2 which is not divided into banks. Thus, the access register is made to correspond to each VRAM, the cycle pattern is set, and the image data in the scene A is read. Then, when switching to scene B, the image data for scene B of scroll screen BG0 is stored in bank 1a in VRAM-1. Then, the contents of the cycle pattern for VRAM-1 are changed to read the image data of the scroll screen BG0. The VRAM-2 stores the image data of the 0 scroll screen BG1 for scene B. Then, the contents of the cycle pattern of the access register for VRAM-2 are changed to read the image data of the scroll screen BG1. In this way, in the scene B, more CPU access time can be allocated to the image data of the scroll screen BG1. At the same time, in the scene B, the VRAM capacity can be saved for the scroll screen BG2 which is not displayed at all. As described above, in the present invention, since the setting of the cycle pattern can be easily changed, the allocation of the VRAM capacity can be more freely and appropriately adjusted according to the information amount of the image data and the necessity of access. . Therefore, there is an effect that the limited VRAM capacity can be used effectively.

[Industrial applicability]

As described above, according to the present invention, the cycle pattern at the time of VRAM access, which changes according to the display conditions, can be set and changed more freely. Therefore, the degree of freedom to display a more varied image is high. An image processing device and a game machine can be provided. In addition, since the number of access registers that store cycle patterns can be easily reduced, there is no need to fix the settings in hardware in advance, and the burden on hardware is reduced as much as possible, regardless of the fixed cycle pattern. It is possible to provide an image processing device and a game machine that can appropriately determine the amount of image data required for each image and save VRAM capacity. Further, it is possible to provide an image processing apparatus and a game machine that can change the allocation of the VRAM capacity according to the amount of information of the image data.

5 one

Claims

【The scope of the claims】

An image data for forming a foreground image is stored in a frame buffer, image data for forming a background image is stored in a video RAM, and the image data for the foreground image is processed in foreground image processing. The background image data is read from the video RAM by the background image processing unit in synchronization with the reading from the frame buffer in the unit, thereby generating the foreground image and the background image at the same timing and superimposing them. In an image processing method for outputting these as a composite image,

Specify the specific operation details to be given to the video RAM to read and write the image data of the background image, set the specified operation contents for each predetermined unit time, and instruct this setting from the CPU. And accessing the video RAM based on an instruction from the CPU.

2. An image processing method comprising: installing at least one video RAM for storing image data of a background image, storing image data in each video RAM, and accessing these video RAMs simultaneously.

An image processing method, wherein a video RAM and reading of image data stored in the video RAM are designated from a CPU.

3. The video RAM is divided into two banks, each of which is a plurality of RAM portions having the same capacity, and each bank and reading of image data stored in the bank are designated by a CPU. 3. The image processing method according to claim 2, wherein:

4. A foreground image which stores image data for forming a foreground image in a RAM, expands the image data in a frame buffer, and reads out the image data for the foreground image from the frame buffer at a predetermined timing. Processing means; background image processing means for reading image data for forming a background image from a video RAM; foreground image data transferred from the foreground image processing means and transferred from the background image processing means Image processing comprising: priority determining means for determining display priority with respect to image data of a background image; and output means for outputting both image data of the foreground image and the background image in accordance with the priority. In the device, Specifying means for specifying an operation of reading or writing image data stored in the video RAM;

First setting means for setting the operation specified by the specifying means for each predetermined unit time;

Storage means for storing the contents of the operation for each predetermined unit time set by the first setting means;

Access control means for controlling access to the video RAM based on the content stored in the storage means;

Bit number output control means for controlling output at the time of output according to the number of bits of predetermined data in the image data according to the information amount of the image data which differs for each background image, Processing equipment.

5. The access control means,

Conversion means for converting the designation by the designation means into a control signal;

Address selecting means for selecting an address on the VRAM of the image data to be read from the VRAM and applying the selected address to the VRAM;

5. The image processing apparatus according to claim 4, comprising:

6. The address selecting means,

6. A method according to claim 5, further comprising: first generating means for generating an address of the pattern name data on the VRAM; and second generating means for generating an address of the pattern data on the VRAM. The image processing apparatus according to any one of the preceding claims.

7. As background image data, pattern data consisting of a predetermined number of pixel information and pattern name data indicating the position of the pattern data constituting the image to be displayed in the background image are stored. In the video RAM access for accessing the video RAM to be read and reading the image data,

5. The image processing apparatus according to claim 4, wherein an access command is used as designating means for designating an operation for reading or writing the pattern data or the pattern name data.

8. The image processing apparatus according to claim 7, wherein the access command is a binary code having a predetermined number of bits.

9. In the video RAM access,

8. The image according to claim 7, wherein the operation specified by an access command is set in units of one cycle during a display period, and a cycle pattern is set in a form readable by a CPU. Processing equipment. _

10. The video RAM access, wherein:

The image processing apparatus according to claim 7, wherein a VRAM access register is used as storage means for storing the cycle pattern.

11. The video RAM access, wherein:

8. The image processing apparatus according to claim 7, wherein access control to the video RAM is controlled according to an access command sequentially read from a cycle pattern stored in the access register.

12. When a plurality of video RAMs or a plurality of video RAM banks for storing image data for a background image are used,

A second setting means for setting whether the video RAM is divided into banks,

An access means for allocating a plurality of the storage means to each of the plurality of RAMs or the banks of the RAM and simultaneously accessing the RAMs or the banks of the RAM;

5. The image processing apparatus according to claim 4, comprising:

13. An image data for forming a foreground image is stored in a RAM, said image data is expanded in a frame buffer, and the image data for the foreground image is stored in the frame at a predetermined timing. Foreground image processing means for reading from a buffer, background image processing means for reading image data for forming a background image from a video RAM, foreground image data transferred from the foreground image processing means and the background image processing Means for determining display priority between the image data of the background picture transferred from the means and output means for outputting the image data of the foreground picture and the background picture in accordance with the priority. Game machine

Specifying means for specifying an operation of reading or writing image data stored in the video RAM;

A first setting for setting the operation specified by the specifying means at every predetermined unit time; Setting means,

Storage means for storing the content of the operation for each predetermined unit time set by the first setting means;

Bit number output control means for controlling output when the number of bits of predetermined data in the image data is changed according to the information amount of image data which differs for each background image. Game console.

14. The access control means,

Address selection means for selecting an address on the VRAM of the image data to be read from the VRAM and applying the selected address to the VRAM;

14. The game machine according to claim 13, comprising:

15. The address selecting means,

15. The game machine according to claim 14, further comprising: first generating means for generating an address of the pattern name data on the VRAM; and second generating means for generating an address of the pattern data address on the VRAM. .

16. As background image data, pattern data composed of a predetermined number of pixel information and pattern name data indicating the position of the pattern data constituting the image to be displayed in the background image are stored. In the video RAM access for accessing the video RAM to be read and reading the image data, an access command is used as designating means for designating an operation for reading or writing the pattern data or pattern name data. 14. The game machine according to claim 13, wherein

17. The game machine according to claim 16, wherein the access command is a binary command having a predetermined number of bits.

18. The video RAM access, wherein:

As a setting means to set the operation specified by the access command in units of one cycle during the display period, a cycle pattern can be read by the CPU. 17. The game machine according to claim 16, wherein the setting is performed.

19. The video RAM access, wherein:

17. The game machine according to claim 16, wherein a storage means for storing the cycle pattern uses a VRAM access register.

20. In the video RAM access,

17. The game machine according to claim 16, wherein access control to the video RAM is controlled in accordance with an access command sequentially read from a cycle pattern stored in the access register.

21. When a plurality of video RAMs for storing image data for a background image or a plurality of video RAM banks are used,

Second setting means for setting whether to divide the video RAM into banks, and allocating a plurality of the storage means to each of the plurality of RAMs or each bank of the RAM, and simultaneously assigning these RAMs or RAM banks. Access means to access,

14. The game machine according to claim 13, comprising: