JP2624667B2 - Graphic processing unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processing apparatus for generating graphic data such as straight lines and circular arcs at high speed and executing drawing.

[Conventional technology]

As a system for outputting characters and graphics to a display device such as a CRT or a printing device, a so-called bit map system having a memory for storing information corresponding to pixels of the output device is increasing. This method has a high degree of freedom, such as the ability to handle arbitrary figures in pixel units, but has a problem in processing performance because it handles a large-capacity memory. For this reason, a system in which a high-speed graphic generation function is built in an integrated circuit is a system excellent in price / performance ratio. Japanese Patent Application Laid-Open No. 60-13 / 1985 discloses an example of such a graphic processing apparatus which performs high-speed generation of a color or multi-gradation graphic.
No. 6793 discloses this. According to this known technique, a plurality of pieces of pixel information are stored in one word of a memory, a predetermined word is read from the memory while sequentially generating an address for specifying a pixel, and a predetermined pixel data in the one word is read out. Is updated and one-word data obtained is rewritten to execute drawing. That is, drawing of one pixel is executed by a series of read / calculation / write processing.

Japanese Patent Application Laid-Open No. 60-40588 discloses a technique for writing one bit of pixel information in the raster direction.

[Problems to be solved by the invention]

The above-described prior art has a problem that, as processing of one pixel, two processes of reading and writing are required for a memory, and the processing time for this memory is a lower limit of processing of one pixel. As a memory access method, a method using one read-modify-write cycle may be used in addition to a method using two random access cycles of read and write. It is difficult to control the memory in addition to taking a longer time than a cycle.

SUMMARY OF THE INVENTION It is an object of the present invention to solve at least the above-described problems and to increase the processing speed by executing processing of at least one pixel with only one writing process.

[Means for solving the problem]

A feature of the present invention is that a plurality of pieces of pixel data are included in one word as an access unit, and each piece of pixel data stores a graphic data composed of a plurality of bits, and a calculation process of the graphic data or the pixel data. A mode setting unit for designating a memory address for designating graphic data in one word unit of the memory, a pixel address for designating pixel data in one word of the graphic data, and writing graphic data in one word unit Or a graphic processing unit that generates a control signal that specifies whether to write predetermined pixel data in one word, and the arithmetic processing specified by the mode setting unit uses the graphic data at the write destination position in the memory. If the calculation is not performed without reading the graphic data of one word unit from the above memory, In response to the control signal, or write the graphic data on the position of the one-word units in said memory specified by said memory address, or,
The 1 in the memory specified by the memory address
A memory control unit that writes the pixel data at a pixel position specified by the pixel address in a word unit position.

[Action]

According to a feature of the present invention, when graphic data or pixel data is written without using data at the write destination, direct writing is performed without reading data at the write destination in word units as in the related art. Therefore, writing for one memory cycle becomes possible.
Therefore, processing of graphic data can be performed at high speed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Graphic processing processor (hereinafter referred to as GDP) 10, memory control circuit 11, memory 1
2, consisting of The GDP receives the commands and control parameters transferred from the CPU (not shown) and generates figures and CRs.
A processor for performing control necessary for display on T, and internally includes a drawing processor 100 and a display processor 101. The drawing processor 100 interprets the command, executes various graphic processing algorithms, generates a memory read and / or write address, and executes an image data calculation process. The display processor 101 generates a memory read address in synchronization with a raster scan of a CRT (not shown). A similar operation is performed when another output device such as a printer is connected as an output device. The memory control circuit 11 includes a timing generation circuit 110, an address generation circuit 111, a data buffer 112, and a video control circuit 113. The timing generation circuit 110 outputs the bus state signals (FBS0 to FBS0) supplied from the GDP10.
3) The timing signals (（, 〜, ▲, ▼) required for accessing the memory 12 using the pixel addresses (PA0 to PA1) and other control signals.
▲ ▼) is generated. The address generation circuit 111 outputs
From the address supplied from 10, dynamic memory 12
Generates a multiplexer address necessary for the control of. The data buffer 112 buffers data transfer between the GDP 10 and the memory 12. The video control circuit 113 receives the display data read from the memory and generates a video signal necessary for a CRT or a printer. In this embodiment, the memory 12 is constituted by using eight dynamic memory chips (120 to 127). However, the memory 12 can be easily expanded to other memory elements (such as a static RAM) or a large number of memories. . In this case, a control signal different from that of the present embodiment may be required. However, it goes without saying that the present invention can be applied similarly to the present embodiment.

FIG. 2 shows an example of a logical arrangement of the memory 12. The addresses are arranged two-dimensionally in the lower right direction, with the smaller address at the upper left. The present embodiment is an example of 4 bits / pixel in which 4 bits are assigned to one pixel, and is applicable to 16-color display or 16-level multi-level display. Memory 1
The word is, for example, 32 bits, but the memory address is given in units of 16 bits. Eight horizontal pixels of data are assigned to one word. Each of the memory elements 120 to 127 in FIG. 1 shares four bits in one word. Conventionally,
Although reading and writing of one word in the memory were performed simultaneously, in the present embodiment, different write control signals (▼ to ▲) are supplied to each memory element to enable writing in pixel units. That is, when the bus status signals (FBS0 to FBS3) designate writing in pixel units, the pixel addresses (PA0 to 1) and the memory address 0 (MA0) are decoded to generate ▲ to ▲. I do.

Next, an example of the bus status signals (FBS0 to 3) output from the GDP 10 will be described with reference to FIG. There are 16 access states of the memory (frame buffer) bus shown in FIG. 3 (however, 3 are undefined). FBS = "000
"0" indicates that nothing is performed on the frame buffer. Writing to the memory is performed in 32-bit units (FBS
= “0111”), 16-bit unit (FBS = “0101”), and pixel unit (FBS = “0001”). The memory control circuit 11 decodes this status signal and outputs a "Low" level to all of the symbols ▼ to ▼ when writing in units of 32 bits to instruct the writing to all the memory chips 120 to 127. In writing in units of 16 bits, either the upper 16 bits or the lower 16 bits are specified by the MA0 signal, and ▲ ▼ to ▲ ▼ or ▲ ▼ to
One of ▲ ▼ becomes active. On the other hand, in the pixel unit writing, the pixel address (PA0 to PA1) and one bit (MA0) of the memory address are used to indicate ▲ ▼ to ▲.
One of ▼ becomes active.

FIG. 4 shows a list of terminals of GDP10. The CPU bus control terminal includes a data bus connected to the CPU bus and control signals. The DMA control pin is directly connected to the memory access controller (D
MAC). The bus switch control signal is a group of signals for controlling an external bus switch when the CPU bus and the frame buffer bus are connected. The FB bus control signal controls the frame buffer bus. The display control signal is a signal input / output required for video control and synchronization control. The clock system consists of one input clock and three output clocks. Here, the address buses (MA0 to MA27) for the frame buffer have a memory address output and a pixel address output multiplexed according to the operation mode.

FIG. 5 shows the contents of the multiplex output of the address. Since the memory address is assigned in units of 16 bits, these terminals are used for outputting the memory address at 32 bits / pixel and 16 bits / pixel. On the other hand, at 8 bits / pixel, a 1-bit pixel address is output to the MA26 terminal. In each case of 4, 2, 1 bit / pixel, a 2, 3, 4 bit pixel address signal is output to each terminal of MA25 to MA26, MA24 to MA26, MA23 to MA26. The MA27 output is a signal for switching between the address space of the CPU and the address space of the system memory, and is output in all cases. When multiplexing is performed in this manner, the maximum memory space that can be used decreases as the number of bits per pixel decreases, but the screen size that can be handled is constant, which is practically convenient.

FIG. 6 shows an example of a list of main commands of the GDP 10. Among these, the commands for performing memory access in pixel units are line drawing commands and each of CHR, ZOOM, and ROT commands. Command processing modes include replacement, logical operation, arithmetic operation, and conditional replacement. However, in modes other than replacement, data must be read out. reading,
Requires two memory accesses for writing. On the other hand, in the case of the replacement mode, the operation can be performed only in the write cycle, so that the speed can be increased.

FIG. 10 shows a time chart of reading and writing of the memory.

FIG. 10 (a) shows a case in which one pixel is updated in two conventional read and write cycles. MCYC is 1
This is a clock signal (not shown in FIG. 1) indicating a cycle of each memory cycle. FBS0 to FBS3 are coded signals indicating bus states (see FIG. 3), MA0 to MA27 are address outputs, and D0 to 31 are data input / output terminals. To update the data of one pixel, one word including the target pixel data is read from the memory in the first memory cycle, and in the second memory cycle, the read data is specified at the specified pixel position inside the GDP with respect to the read data. And the result is written back to the memory. That is, the data update processing of one pixel is performed using two memory cycles. Fig. 10 (b)
Shows a pixel unit write cycle. In this case, FB
The outputs of S0 to S3 indicate the pixel unit write cycle and
Information (PA) for specifying a pixel is output from the MA terminal. These signals can be decoded outside the GDP 10 to generate a write signal for each pixel. Therefore, since writing of one pixel can be executed in one memory cycle, the writing speed is higher than that of the method of FIG.

FIG. 11 shows a configuration of a drawing mode register included in the GDP 10. The drawing mode register is a 32-bit register that specifies various operation modes during drawing, and is mapped as one of the parameter registers.
Replacement and reading are possible using the R command. Operation mode, color comparison mode, binary mode, color mode, logical pel mode, character area mode,
It has designated bits for a drawing area mode and a pick mode. Hereinafter, the operation mode will be described in detail in relation to the present embodiment, and the description of the other mode bits will be omitted.

FIG. 12 shows a breakdown of five bits specified as the operation mode. 16 types of logical operations and 4 types of calculation operations can be specified. S indicates drawing data (transfer source data in the case of a text or image transfer command), D indicates write destination memory data, and D 'indicates write data. For example, when OPM = 00001 is specified as the operation mode, the logical product of the drawing data and the memory data of the writing destination is calculated and written. When OPM = 00001 is designated, this is a so-called replacement mode in which only drawing data is written. The column on the right side of the figure indicating whether a write-only cycle is possible is
This shows whether or not the write-only mode is executed in the pixel-by-pixel write cycle. In the operation mode in which the write destination memory data (D) is required for the operation, the memory data is always required. Therefore, the pixel data is updated using two memory cycles of read and write regardless of the designation of the write-only mode. Will be On the other hand, the mode (D ′ = 0,
D ′ = S, D ′ = NOT (S), D ′ = 1)
When the write-only mode is specified, a pixel-by-pixel write cycle is executed.

As described above, according to the present embodiment, in the case of the replacement mode, there is an effect that the speed can be increased as a result of performing access in pixel units only by the write cycle.

Next, another embodiment of the present invention will be described. FIG. 7 shows another embodiment to which the present invention is applied. In this embodiment,
GDP'20 outputs pixel mask information (MSK0 to 7) instead of outputting a pixel address. That is,
The pixel mask information indicates a pixel position to be drawn among 8 pixels (32 bits in the case of 4 bits / pixel). The memory control circuit 21 uses this pixel mask information to
▼ to ▲ ▼ can be controlled. Therefore, writing to arbitrary plural pixels in one word becomes possible. In this embodiment, the case of 4 bits / pixel is used, but in the case of 8 bits / pixel or more, a part of the pixel mask information may be used. Further, if 32 bits are output as pixel mask information, it goes without saying that the present invention can be applied to 1 bit / pixel and 2 bits / pixel. As described above, in this embodiment, writing to a plurality of pixels in one word becomes possible, and the speed can be further increased.

FIG. 8 illustrates two types of drawing. FIG. 8A shows an example of arbitrary direction drawing (vector drawing), and FIG. 8B shows an example of raster direction drawing. Vector drawing refers to a case where drawing points sequentially move in an arbitrary direction, and includes line drawing such as generation of straight lines, arcs, elliptical arcs, and arbitrary curves in arbitrary directions. That is, this vector drawing is basically a pixel-based process, and the pixel-based writing according to the present invention can be applied. On the other hand, raster direction drawing is to perform drawing in the same horizontal direction as the array of pixels, and this raster direction drawing is applied to surface drawing such as horizontal linear, filling and copying of area data. In raster direction drawing, writing can be performed in word units except for the left and right ends. At the left and right ends,
Although the drawing boundary does not always coincide with the word boundary, application of the embodiment of FIG. 7 enables drawing in only such a write cycle in such a case. In the case of vector drawing, a plurality of horizontally continuous pixels may be included in the same word. However, if the embodiment shown in FIG. 7 is applied, drawing can be performed only in a write cycle.

FIG. 9 shows yet another embodiment of the present invention.
Automatically detect the case where the pixels included in the same word are continuous,
The writing into a plurality of pixels in one word can be performed at a time. The drawing processor (GDP ″) 30 includes a drawing control unit 31, an address buffer 32, a data buffer 33, a match detection circuit 34, a mask generation circuit 35, and an access request control circuit 3.
6, built-in. The drawing control means 31 sequentially calculates drawing pixel positions in accordance with a predetermined algorithm and calculates drawing data. The address buffer 32 is a drawing control means.
The memory address information output from 31 is temporarily stored.
The data buffer 33 buffers data transfer between the drawing control means 31 and the memory. The match detection circuit 34 compares the memory address of the current processing target stored in the address buffer 32 with the next memory address of the next processing target output from the drawing control means 31, and determines whether there is a match. A signal indicating whether or not the signal is output. The mask generation circuit 35 decodes a pixel address output from the drawing control means 31 and generates pixel mask information. The mask generation circuit 35 is controlled by an output from the coincidence detection circuit 34, and is controlled while the memory address to be processed matches. Works to set only the bit corresponding to the pixel position to be processed next with respect to the immediately preceding pixel mask information. If a different memory address is specified, the mask information is output after outputting the immediately preceding mask information to the outside. And works to set the bit corresponding to the next pixel position. The access request control circuit 36 outputs an access request signal to the memory.While the memory address to be processed matches, the access request control circuit 36 does not perform writing to the memory. A memory access request signal is generated for writing. That is, writing to the memory is not performed while the processing for the pixels in the same word continues, and when the target memory address moves, the writing processing for the previous memory address is executed. Therefore, even when processing is performed on a pixel basis, for example, when a straight line in an arbitrary direction is generated, if a pixel to be processed is horizontally continuous and included in the same word, one memory Writing can be done. As described above, according to the present embodiment, even when the operation is performed based on the pixel-by-pixel processing algorithm, the number of memory accesses can be reduced as a result of writing to a plurality of pixels in one word only once. effective.

〔The invention's effect〕

As described in detail above, according to the present invention, access can be made on a pixel-by-pixel basis only by a write cycle, and as a result, high-speed graphic processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram showing a memory array, FIG. 3 is an explanatory diagram of a bus access state signal, FIG. 4 is a diagram showing a list of GDP terminals, FIG. 5 is an explanatory diagram of an address multiplex,
FIG. 6 is a diagram showing a list of commands, FIG. 7 is a diagram showing another embodiment of the present invention, FIG. 8 is a diagram showing an example of vector drawing and raster direction drawing, and FIG. FIG. 10 is a diagram showing still another embodiment of the invention, FIG. 10 is a time chart of reading and writing of a memory, FIG. 11 is a configuration diagram of a drawing mode register, and FIG.
FIG. 12 is a diagram showing a breakdown of the operation modes. 10: Graphic processing processor (GDP), 11: Memory control circuit, 12: Memory.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jun Sato, 1450, Kamizuhoncho, Kodaira City, Hitachi, Ltd.Musashi Factory (72) Inventor Takashi Sone, 1450, Kamisuihonmachi, Kodaira City, Hitachi, Ltd., Musashi Factory ( 56) References JP-A-59-114588 (JP, A) JP-A-56-31154 (JP, A) JP-A-61-296385 (JP, A) JP-A-59-157882 (JP, A) JP-A-56-33735 (JP, A) JP-A-61-296386 (JP, A) JP-A-62-15593 (JP, A) JP-A-58-222371 (JP, A)

Claims (8)

(57) [Claims] 1. A memory having a plurality of pixel data in one word as an access unit, each pixel data storing a graphic data composed of a plurality of bits, and designating an arithmetic processing of the graphic data or the pixel data. A memory address for specifying one-word graphic data of the memory, a pixel address for specifying pixel data within one word of the graphic data, and whether to write one-word graphic data. A graphic processing unit for generating a control signal for specifying whether to write predetermined pixel data in one word; and an arithmetic process specified by the mode setting unit uses graphic data at a write destination position of the memory. If the calculation is performed without
In response to the control signal, graphic data is written to the one-word unit position in the memory specified by the memory address without reading out the word-based graphic data, or specified by the memory address. A graphic controller for writing the pixel data at a pixel position specified by the pixel address at the position of the one word unit in the memory. 2. The method according to claim 1, wherein when the memory control unit writes predetermined pixel data in one word, the memory address and the pixel address are multiplexed to generate a write address signal. A graphics processing apparatus. 3. The graphic processing unit according to claim 1, wherein said graphic processing unit generates a control signal for writing predetermined pixel data in said one word when a curve including a straight line in an arbitrary direction is generated. A graphic processing device for generating a control signal for writing the graphic data in units of one word at the time of surface painting. 4. The first, second or third aspect of the present invention.
In the paragraph, the graphic processing unit has a bit number specifying unit that specifies a bit number per pixel, and generates the memory address and the pixel address according to the specified bit number per pixel. A graphic processing device characterized by the following. 5. A memory having a plurality of pixel data in one word as an access unit, each pixel data storing a graphic data composed of a plurality of bits, and designating an arithmetic processing of the graphic data or the pixel data. A memory address that specifies graphic data in one word unit of the memory, a pixel address that specifies pixel data in one word of the graphic data, and whether to read out graphic data in one word unit in the memory. A graphic processing unit for generating a control signal for specifying whether to write graphic data in units of one word or predetermined pixel data in one word; and the arithmetic processing designated by the mode setting unit is If the operation is to be performed using graphic data at the write destination position of the memory, Ri reads graphic data of one word units, and processing the read the graphic data, in response to said control signal,
Graphic data is written at the one-word unit position in the memory specified by the memory address, or specified by the pixel address at the one-word unit position in the memory specified by the memory address. When the pixel data is written at a pixel position to be calculated and the arithmetic processing specified by the mode setting unit is to perform an arithmetic operation without using the graphic data at the write destination position of the memory, the word unit is used from the memory. The graphic data is written to the one-word unit position in the memory specified by the memory address, or the memory specified by the memory address, according to the control signal without reading the graphic data of At the pixel position specified by the pixel address at the one-word unit position Graphics processing apparatus characterized by having a memory controller for writing data. 6. A memory device according to claim 5, wherein said memory control section multiplexes said memory address and said pixel address to generate a write address signal when writing predetermined pixel data in one word. A graphics processing apparatus. 7. The graphic processing unit according to claim 5, wherein the graphic processing unit generates a control signal for writing predetermined pixel data in the one word when a curve including a straight line in an arbitrary direction is generated, A graphic processing apparatus for generating a control signal for writing graphic data in units of one word at the time of surface painting. 8. The method according to claim 5, 6 or 7, wherein
In the paragraph, the graphic processing unit has a bit number specifying unit that specifies a bit number per pixel, and generates the memory address and the pixel address according to the specified bit number per pixel. A graphic processing device characterized by the following.