JPH0193868A - Data processor - Google Patents

Abstract

PURPOSE:To execute a raster operation at high speed by selecting the type of the operation of respective parts from the plural types of the previously provided operations according to the contents of the storage of source data. CONSTITUTION:For instance, in case of the logic operation of REPLACE, the data is read from a first source area before the logic operation and stored in a MASK register 4. Then, according to the contents of the MASK register 4, the type of the logic operation by the logic operation circuit 5 of the respective bits of a second source area and a destination area stored in a SRC register 2 and a DST register 3 is changed. Namely, the respective bits of the MASK register 4 are referred and in case of '1', the logic operation is set to REPLACE and in case of '0', it is set to NOP (the data of the destination area is directly rewritten). According to such a processing, the number of memory accesses conventionally requiring 9M times can be reduced to 4M times.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to data processing that reads and writes in word units a memory that stores data in a two-dimensional array in which each word consists of N bits (N is an integer). The present invention relates to an apparatus, and particularly to a data processing apparatus that performs a so-called rask operation on image data developed on a memory at high speed.

2. Description of the Related Art In recent years, devices such as word processors and image workstations that can easily edit texts and images have become popular. The so-called rask operation is becoming more important as a function necessary for these devices. Rask operation refers to a logical operation when transferring image data developed as a two-dimensional bit image on memory from one area to another area. These areas are generally rectangular, and conventional mask operations are performed as follows.

Transfer source area of image data to SRC (SO[IRCE)
DESTINATI area, transfer destination area
ON) area. DST this SRC area
When transferring data to an area, one word of data A in the SRC area is first read, and then one word of data B in the DST area to which this word is to be transferred is read. Here data A
and data B, and write the obtained data back to the original word in the DST area. The type of logical operation is A.
ND (logical product), OR (logical sum), X0R (exclusive logical sum), REPLACE (write data in the SRC area as is to the DST area), etc. can be selected. Such processing is performed for all words in the SRC area and DST area.

Problems to be Solved by the Invention By the way, in the conventional mask calculation as described above, in order to perform a mask calculation that targets two SRC areas and one DST area as shown in FIG. No. 3
Steps had to be taken. In FIG. 3, it is assumed that "1" is written in the black part and "0" is written in the white part in the corresponding memory.

First stage: ANDL the inverted data of the first SRC area and the DST area and store the result in the first work area.

2nd stage: 1st SRC area and 23rd RC area
DL stores the result in the second work area.

Third stage: OR the first work area and the second work area and store the result in the DST area.

Here, the →-ri area is a rectangular area on the memory, and the SRC
It is prepared separately from the area and the DST area.

For these three stages of processing, assuming that the number of words in one rectangular area is M, a total of 9M memory accesses, including reading of 6M words and writing of 3M words, were required.

In this way, although the process of modifying only the arbitrary-shaped area defined by the data of the first SRC area is regarded as an advanced form of the basic rectangular area mask operation, the processing speed is slow. There was a problem that.

Therefore, it is an object of the present invention to provide a data processing device that can process mask operations at high speed.

Means for Solving the Problems According to the present invention, a memory storing data in a two-dimensional array, each word consisting of N bits (N is a positive integer), is read and written in word units. In the data processing device, there is provided a read means for reading data by sequentially generating three types of addresses corresponding to at least three arbitrary areas in the memory, and a read means for reading data from the read means 1; first, second, and third storage means for storing each N-bit data read corresponding to;
The operation of the data stored in the first storage means and the data stored in the second storage means is divided into n parts (n is a positive integer of n≦N), and the type of operation of each part is independent. and an arithmetic means that executes the arithmetic operation according to the above, and the arithmetic means selects the arithmetic operation type of each part from a plurality of arithmetic operation types based on the data stored in the third storage means. A data processing device is provided.

Operation The operation of the data transfer apparatus according to the present invention described above will be explained using FIG. 3 as an example.

In the data transfer device according to the present invention described above, RE
Prior to the logical operation of PLACE, data is read from the first SRC area and stored in the third storage means. This data is called mask data. Next, the type of logical operation for each bit of the 23rd RC area and DST area stored in the first and second storage means is changed depending on the contents of the mask data.

In other words, refer to each bit of mask data and set it to “1”.
If so, the logical operation is REPLACE, and if it is 0, it is NOP (the data in the D'ST area is written back as is). Through this process, the number of memory accesses that were conventionally required 9M times has been reduced to 4M times. can be reduced.

Therefore, in the example of FIG. 3, the basic processing is a transfer from the 23rd RC area to the DST area with the logical operation REPLACE, and the transfer is masked by the data of the first SRC area. Therefore, if mask processing is not performed, the result will be the same as the pattern of the 23rd RC area.

In this way, the present invention minimizes the number of memory accesses by introducing the concept of "mask processing" into the mask operation itself, and by performing the processing that was conventionally divided into three stages at once. , it is possible to perform mask calculations for arbitrary-shaped regions at high speed.

Embodiment Next, an embodiment of the data processing apparatus of the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of the present invention.

The data processing device shown in FIG. 1 includes a memory control circuit 1 that generates addresses for an SRC area and a DST area in a memory (not shown) to control data read/write. The memory control circuit 1 includes a memory address bus 6 that supplies addresses to the memory;
A memory data bus 7 that transfers data to and from the memory is coupled to a read data bus 8 that transfers data read from the memory. The read data bus 8 stores SRC area data.
The RC register 2, the DST register 3 which stores f-data in the DSTIi area, and the MASK register 4 which stores mask data are coupled.

The illustrated data processing device further includes a logic operation circuit 5. This logic operation circuit 5 is connected to a data bus 10.1.
1.12 respectively, SRC register 2, DST
Data is transferred from the register 3 and the MASK register 4, and it has a logical operation circuit 5 that performs a logical operation on the data of the SRC register 2 and the data of the DST register 3 based on the data of the MASK register 4. The output data of the logic operation circuit 5 is transferred to the memory control circuit 1 via the write data bus 9.

Furthermore, the memory control circuit 1 outputs a read request signal 20 and a write request signal 21 to the memory, respectively, and outputs a read request signal 20 and a write request signal 21 to the memory.
C register 2, DST register 3, MASK register 4
data latch signals 22, 23, and 24 respectively for
Output.

Each register and data bus has a width of 16 bits, and an SRC area, a DST area, and a MASK area in which mask data is stored can be arbitrarily set on the memory. The configuration of one word of the memory is a so-called plane configuration in which data of 16 pixels is packed.

The operation will be explained in detail. First, memory control circuit 1
outputs the first address of the preset MASK area to the memory address bus 6, and simultaneously activates the read request signal 20. Then, the read data read from the memory is transferred to the memory data bus 7.
The data is taken into the memory control circuit 1 via the memory control circuit 1. This data is output to read data bus 8 and latched into MASK register 4. The latch timing is supplied from the memory control circuit 1 to the MASK register 4 as a data latch signal 24.

Similarly, data is read from the first address of the SRC area and taken into the SRC register 2.

The latch signal of the SRC register 2 is also supplied as a data latch signal 22 from the memory control circuit 1. Subsequently, data in the DST area is also taken into the DST register 3.

Once the data of these three areas are taken in, mask calculation is started. The logic operation circuit 5 controls this mask operation, and the operation of this circuit will be explained with reference to Table 1 below.

Table 1 (1) Table 1 (2) Table 1 shows an example of the mask operation.
, 0 in SR register 2 and DST register 3 respectively.
This shows the calculation result when FFD++, CCCCH, 619 (h (H represents a hexadecimal number) is latched. In this example, there are two types of calculations, the first is MASK
In the operation of a bit position of "1" among the bits of register 4, REPLACE, that is, the data of SRC register 2 is output. The second is an operation on the bit position that is ``0'' among the bits of the MASK register 4, and the NOP, that is, the data of the DST register 3, is output.In this way, the operation result 6CCOH is obtained.

Now, the calculation result in the logic mental arithmetic circuit 5 is inputted to the memory control circuit 1 via the write data bus 9, and then the data is transferred to the memory data bus 7 and the address (DS
T area address) is output to the memory address bus 6, and at the same time the write request signal 21 becomes active.

When these processes are performed for all words in the SRC area, DST area, and MASK area, a processed image as shown in FIG. 3 is obtained.

Example 2 Next, a second example of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a second embodiment of the invention.

The data processing device shown in FIG. 2 is obtained by adding the following circuit to the data processing device shown in FIG. That is, the data processing device shown in FIG. 2 includes a selection circuit 50 that selects 4 bits out of 16 bits of data in the MASK register, and a mask data that transfers the 4 bits of mask data output from the selection circuit 50.・Bus 51 is provided. Furthermore, a numerical calculation circuit 52 is provided in place of the logical calculation circuit 5 in FIG. Each register and data bus has a width of 16 bits except for the mask data bus 51, and an SRC area, a DST area, and a MASK area where mask data is stored can be arbitrarily set on the memory. can. The configuration of one word of the memory is different from the first embodiment, and is a so-called pixel configuration in which 4 bits per pixel are packed into 4 pixels.

The operation will be explained. MASK area, SRC area, D
The steps up to generating the address of the ST area and loading the data read from the memory into the MASK register 4, SRC register 2, and DST register 3 are the same as in the first embodiment. The difference is the first feature, which is the method of calculating the data of the three captured areas.

In the first embodiment, all 16 bits of mask data controlled the operations of the logic operation circuit, but in this embodiment, the operations of the numerical operation circuit 52 are controlled by the 16-bit mask data. These are the 4 bits selected by the selection circuit 50 out of the data. The first four bits of the mask data are selected from the most significant bits (bit positions 15 to 12 of MASK register 4).

Examples of calculations are shown in Table 2 below.

Table 2 (2) Table 2 (2) When mask data is “1”, 4 bits of the SRC area corresponding to that bit are output, and when it is “0”, DST
The 4 bits of the area are output. The obtained 16-bit data is written to memory using the same procedure as in the first embodiment.

Thus, the first word has been processed, but the second feature of this embodiment lies in the following processing. Only the data in the SRC area and DST area is taken into the SRC register 2 and DST register 3 without reading the data in the second MASK area.

Furthermore, at the same time as the DST register 3 is latched, the selection circuit 50 selects the next 4 bits by the data launch signal 23.
) is output to the mask data bus 51. From this point onwards, the processing is the same as for the first word. Furthermore, the third and fourth words are similarly processed by changing the selection of mask data.

At this point, all the mask data that was read first has been referenced. Therefore, processing of the fifth word begins with reading data in the MASK area, as in the first case.

When these processes are performed for all words in the SRC area, DST area, and MASK area, all the processes are completed.

Effects of the Invention As described above, according to the present invention, by sequentially reading mask data that controls logical operations, mask operations in arbitrary areas can be executed at high speed. It is thought that this will dramatically improve the processing performance of various applications in general personal computers, as well as word processors and image workstations.

In the embodiment, one word is made up of 16 bits, but the present invention is not limited to this. In addition, in the first embodiment, NOP and REPLACE were illustrated as logical operations, but high-performance operations such as AND, 0RSXOR, etc., such as inverting read data from the SRC area or DST area and then performing a logical operation It is also possible to provide a circuit.

Furthermore, in the second embodiment, by significantly reducing the number of times mask data is read, further performance improvement can be achieved. The numerical calculation process in this second embodiment is as follows:
Although a simple REPLACE is taken as an example, it is easily possible to perform various comparison operations by considering the data in the SRC area and the data in the DST area as 4-bit numerical values using the mask data I10.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a data processing device according to the present invention that executes mask operations at high speed. FIG. 2 is a block diagram showing a second embodiment of a data processing device according to the present invention that executes mask operations at high speed. FIG. 3 is a block diagram showing an example of the mask operation. (Main reference numbers) 1...Memory control circuit, 2...SRC register, 3...DST register, 4...MASK register, 5...Logic operation circuit, 6...Memory address bus, 7... Memory data bus, 8. Read data bus, 9. Write data bus, 10, 11. 12...Data bus, 20...Read request signal, 21...Write request signal, 22, 23.24...Data latch signal, 50...Selection circuit, 51...Mask data bus, 52.・Numerical calculation circuit

Claims (1)

[Scope of Claims] A data processing device that reads and writes in units of words a memory storing data in a two-dimensional array, each word of which is composed of N bits (N is a positive integer), comprising: read means for reading data by sequentially generating three types of addresses corresponding to at least three arbitrary areas; and read means for reading data by sequentially generating three types of addresses corresponding to at least three arbitrary areas; n first, second, and third storage means to store data, and n operations on data stored in the first storage means and data stored in the second storage means (n is a positive integer of n≦N). divided into parts,
calculation means for independently determining and executing the calculation types of each part, and the calculation means selects a calculation type from among a plurality of calculation types preliminarily provided with the calculation types of each part.
A data processing device characterized in that the selection is made based on data stored in the third storage means.