JPH0547867B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a data processing device that reads and writes data word by word in which data in which one word consists of N bits (N is an integer) is stored in a two-dimensional array. The present invention relates to a data processing device that performs so-called raster operations on expanded image data at high speed. 2. Description of the Related Art In recent years, devices such as word processors and image workstations that allow text and images to be easily edited have become popular. So-called raster operations are becoming more important as a function necessary for these devices. Raster operation refers to a logical operation when image data developed as a two-dimensional bit image on memory is transferred from one area to another area. These areas are generally rectangular, and conventional raster operations are performed as follows. The source area of the image data will be referred to as the SRC (SOURCE) area, and the destination area will be referred to as the DST (DESTINATION) area. When transferring this SRC area to the DST area, first read one word of data A in the SRC area, and then transfer this word.
Read one word of data B in the DST area.
Here, a logical operation is performed on data A and data B, and the obtained data is written back to the original word in the DST area.
The types of logical operations are AND (logical product), OR (logical sum), XOR (exclusive logical sum), and REPLACE (SRC
Write the data in the area as is to the DST area)
etc. can be selected. This kind of processing is done in the SRC area,
This refers to all words in the DST area. Problems to be Solved by the Invention By the way, in the conventional raster operation as described above, two SRC areas and one
In order to perform raster operations on two DST regions, three stages of processing generally have to be performed. In FIG. 3, it is assumed that "1" is written in the black part and "0" is written in the white part in the corresponding memory. First step: AND the inverted data of the first SRC area and the DST area and store the result in the first work area. 2nd stage: AND the 1st SRC area and 2nd SRC area
and stores the results in the second work area. 3rd stage: 1st work area and 2nd work area
OR and store the result in the DST area. Here, the work area is a rectangular area on memory, and is prepared separately from the SRC area and DST area. For these three stages of processing, if the number of words in one rectangular area is M, 6M words are read and 3M words are written, a total of 9M times.
needed access. In this way, although the process of modifying only the arbitrarily shaped area defined by the data of the first SRC area is regarded as an advanced form of raster operations for basic rectangular areas, the processing speed is slow. There was a problem that. Therefore, it is an object of the present invention to provide a data processing device that can process raster operations at high speed. Means for Solving the Problems According to the present invention, one word consists of N bits (N
is a positive integer) in a two-dimensional array, and has at least three data storage areas including a transfer destination area and first and second transfer source areas, In a data processing device that reads data stored in the three areas, performs mutual operations, and generates data to be written to the transfer destination area, three types of addresses corresponding to the three areas are sequentially generated. , read means for reading out the data stored in each of the areas word by word, and each word read by the read means.
a first, a second and a third for storing word data;
The mutual arithmetic processing of the data stored in the storage means, the first storage means and the second storage means is divided into n parts (n is a positive integer of n≦N), and each of the parts is a calculation means capable of individually selecting and executing the type of calculation in the calculation means; and a connection means for inputting data stored in the third storage means to the calculation means as data specifying the type of calculation selected by the calculation means. There is provided a data processing device, wherein the arithmetic means is configured to execute an arithmetic operation of an arithmetic type selected from a plurality of predefined arithmetic types. Operation The operation of the data transfer device according to the present invention described above will be explained using FIG. 3 as an example. In the data transfer device according to the present invention described above, data is read from the first SRC area and stored in the third storage means prior to the logical operation of REPLACE. This data is called mask data. Next, depending on the contents of the mask data, the first
and a second SRC area stored in the second storage means.
Change the type of logical operation for each bit in the DST area. In other words, each bit of the mask data is referenced, and if it is "1", the logical operation is REPLACE,
If it is “0”, it is a NOP (the data in the DST area is written back as is). Through such processing, the number of memory accesses that were conventionally required 9M times can be reduced to 4M times. Therefore, in the example shown in Figure 3, the basic processing is performed from the second SRC area with the logical operation as REPLACE.
As a transfer to the area, the transfer is masked using the data of the first SRC area. Therefore, without masking, the result will be the same as the pattern in the second SRC area. In this way, the present invention minimizes the number of memory accesses by introducing the concept of "mask processing" into the raster operation itself and performing processing that was previously divided into three stages in one go. , it is possible to perform raster operations on arbitrarily shaped areas at high speed. Embodiment Next, an embodiment of the data processing apparatus of the present invention will be described with reference to the accompanying drawings. Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of the present invention. The data processing device shown in FIG. 1 includes a memory control circuit 1 that generates addresses for an SRC area and a DST area in a memory (not shown) to control data read/write. The memory control circuit 1 includes a memory address bus 6 that supplies addresses to the memory, a memory data bus 7 that transfers data to and from the memory, and a read data bus 7 that transfers data read from the memory.・
The bus 8 is connected to the bus 8. The read data bus 8 includes an SRC register 2 that stores data in the SRC area, a DST register 3 that stores data in the DST area, and a MASK register 4 that stores mask data. are combined. The illustrated data processing device further includes a logic operation circuit 5. This logical operation circuit 5 is connected via data buses 10, 11, and 12, respectively.
Data is transferred from SRC register 2, DST register 3, and MASK register 4, and SRC register 2
For the data of and the data of DST register 3,
It has a logic operation circuit 5 that performs logic operations based on data in the MASK register 4. The output data of the logic operation circuit 5 is transferred to the memory control circuit 1 via the write data bus 9. Furthermore, the memory control circuit 1 outputs a read request signal 20 and a write request signal 21 to the memory, respectively, and outputs the SRC register 2, DST register 3,
Data latch signals 22, 23, and 24 are output to the MASK register 4, respectively. Each register and data bus are 16 bits wide, and the memory has an SRC area, DST area,
and MASK where mask data is stored
The area can be set arbitrarily. The structure of one word of memory is a so-called plane structure in which 16 pixel data is packed. The operation will be explained in detail. First, the memory control circuit 1 outputs the first address of the preset MASK area to the memory address bus 6, and at the same time makes the read request signal 20 active. Then, the read data read from memory
Data is taken into the memory control circuit 1 via the memory data bus 7. This data is output to read data bus 8 and ASK register 4.
is latched to. The latch timing is determined by the data latch signal 24 from the memory control circuit 1.
Supplied to MASK register 4. Similarly, data is read from the first address of the SRC area and taken into the SRC register 2.
The latch signal of the SRC register 2 is also supplied as a data latch signal 22 from the memory control circuit 1. Subsequently, data in the DST area is also taken into the DST register 3. When the data of these three areas is taken in, raster calculation is started. The logic operation circuit 5 controls this raster operation, and the operation of this circuit will be explained with reference to Table 1 below.

[Table] Table 1 shows examples of raster operations, including MASK register 4, SR register 2, and DST register 3.
2A and 2B show the calculation results when OFFO _H , CCCC _H , and 6190 _H (H represents a hexadecimal number) are latched, respectively. In this example, there are two types of operations, the first
The operation on the bit position that is “1” among the bits in MASK register 4 is REPLACE, that is,
Data of SRC register 2 is output. The second is
By calculating the bit position that is "0" among the bits in the MASK register 4, NOP, that is, data in the DST register 3, is output. In this way, the calculation result
6CCO _H is obtained. Now, the operation result in the logic operation circuit 5 is input to the memory control circuit 1 via the write data bus 9, and then the data is transferred to the memory data bus 7, and the address (address of the DST area) is transferred to the memory address. The write request signal 21 is output to the bus 6, and at the same time the write request signal 21 becomes active. These processes are performed in the SRC area, DST area, and MASK.
If all words in the area are processed, a processed image as shown in FIG. 3 will be obtained. Embodiment 2 Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing a second embodiment of the invention. The data processing device shown in FIG. 2 is obtained by adding the following circuit to the data processing device shown in FIG. That is, the data processing device shown in FIG. 2 includes a selection circuit 50 that selects 4 bits out of 16 bits of data in the MASK register, and a mask data that transfers the 4 bits of mask data output from the selection circuit 50.・Bus 51 is provided. Furthermore, a numerical calculation circuit 52 is provided in place of the logical calculation circuit 5 in FIG. In addition, each register, data
The buses are 16 bits wide except for the mask data bus 51, and the SRC area and DST area are located on the memory.
Area and mask data are stored
MASK area can be set arbitrarily. The configuration of one word of the memory is different from the first embodiment, and is a so-called pixel configuration in which 4 bits per pixel are packed into 4 pixels. The operation will be explained. The steps up to generating addresses for the MASK area, SRC area, and DST area and taking data read from the memory into the MASK register 4, SRC register 2, and DST register 3 are the same as in the first embodiment. The difference is the first
This is the method of calculating the data of the three captured areas, which is a feature of . In the first embodiment, all 16 bits of mask data controlled the operations of the logic operation circuit, but in this embodiment, the operations of the numerical operation circuit 52 are controlled by the 16-bit mask data. These are the 4 bits selected by the selection circuit 50 out of the data. The first 4 bits from the most significant bit of the mask data are selected (bit positions 15 to 12 of MASK register 4).
It is. Examples of calculations are shown in Table 2 below.

[Table] When the mask data is “1”, the 4 bits of the SRC area to which that bit corresponds are output, and “0” is output.
When , 4 bits of the DST area are output. The obtained 16-bit data is written into memory using the same procedure as in the first embodiment. Thus, the first word has been processed, but the second feature of this embodiment lies in the following processing. second
Without reading the data in the MASK area, read the data in the SRC area.
Transfer only data in the DST area to SRC register 2, DST
Import into register 3. Further, at the same time as latching the DST register 3, the selection circuit 50 outputs the next 4 bits (bit positions 11 to 8 of the MASK register 4) to the mask data bus 51 in response to the data latch signal 23. From this point onwards, the processing is the same as for the first word. Furthermore, the third
Similarly, the fourth word is processed by changing the selection of mask data. At this point, all the mask data that was read first has been referenced. Therefore, processing of the fifth word begins with reading data in the MASK area, as in the first case. These processes are performed in the SRC area, DST area, and MASK.
All processing is completed when all words in the area are processed. Effects of the Invention As described above, according to the present invention, by sequentially reading mask data that controls logical operations, raster operations in arbitrary areas can be executed at high speed. It is believed that this will dramatically improve the processing performance of various applications in general personal computers as well as word processors and image workstations. In addition, in the example, one word is 16 bits, but
The present invention is not limited to this. In addition, in the first embodiment, NOP is used as a logical operation.
Although REPLACE is shown as an example, it is also possible to include a high-performance arithmetic circuit such as AND, OR, XOR, etc., which performs logical operations after inverting read data from the SRC area or DST area. Furthermore, in the second embodiment, by significantly reducing the number of times mask data is read, further performance improvement can be achieved. The numerical calculation processing in this second embodiment uses a simple REPLACE as an example, but by considering the data in the SRC area and the data in the DST area as 4-bit numerical values by mask data I/0, various comparisons are performed. It is also easily possible to perform calculations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a data processing device according to the present invention that executes raster operations at high speed, and FIG. 2 shows a second embodiment of the data processing device according to the present invention that executes raster operations at high speed. FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing a specific example of raster calculation. (Main reference number), 1...Memory control circuit, 2
...SRC register, 3...DST register, 4...
...MASK register, 5...Logic operation circuit, 6...
...Memory address bus, 7...Memory data bus, 8...Read data bus, 9...
Write data bus, 10, 11, 12...data bus, 20...read request signal, 21...
Write request signal, 22, 23, 24...data
Latch signal, 50... selection circuit, 51... mask data bus, 52... numerical calculation circuit.

Claims (1)

[Claims] 1. Data in which one word consists of N bits (N is a positive integer) is stored in a two-dimensional array, and includes a transfer destination area and first and second transfer source areas. In a data processing device for a memory having at least three data storage areas, the data processing device reads data stored in the three areas, performs mutual calculations, and generates data to be written to the transfer destination area. read means for sequentially generating three types of addresses corresponding to the areas and reading the data stored in each of the areas word by word; and storing one word of data each read by the read means. the first, second, and third storage means to perform mutual arithmetic processing of data stored in the first storage means and the second storage means n times (n is n≦N);
(a positive integer)) and an arithmetic means that can individually select and execute the type of operation in each of the parts; and a third storage means as data specifying the type of operation selected by the arithmetic means. connection means for inputting stored data to the calculation means, and the calculation means is configured to execute an operation of an operation type selected from a plurality of predefined operation types. data processing equipment.