FR2587520A1 - MEMORY DIRECT ACCESS WINDOW DISPLAY APPARATUS AND METHODS - Google Patents

Abstract

THE PRESENT INVENTION RELATES TO AN APPARATUS FOR TRANSFERRING DATA BETWEEN A MEMORY DEVICE AND A DISPLAY INCLUDING: A DISPLAY MEANS 14 FOR DISPLAYING DATA; A FRAME BUFFER 18 COUPLES TO THE DISPLAY MEANS FOR STORING THE DATA TO BE DISPLAYED, THIS FRAME BUFFER CONSISTING OF AT LEAST ONE BIT CARD INCLUDING A PLURALITY OF DATA BITS, THESE BITS REPRESENTING THE STATE OF AN ELEMENT OF ' DISPLAY ON DISPLAY; A MEMORY MEANS 15 FOR STORING DATA TO BE DISPLAYED, THIS DATA BEING STORED IN THE FORM OF A FRAME; A COMMAND MEANS 20 FOR READING A DATA FRAME FROM THE MEMORY MEDIA AND TRANSFERRING THE DATA TO SELECTED LOCATIONS OF THE FRAME BUFFER, THESE LOCATIONS BEING DEFINED BY A WIDTH VALUE AND A POINT OF ORIGIN, THEREFORE THE COMMAND MEAN SEQUENTIALLY READING DATA BEGINNING WITH A BASE ADDRESS; AS A RESULT THAT THE DATA CAN BE TRANSFERRED AT HIGH SPEED TO THE DISPLAY.

Description

The present invention relates to an apparatus and

  methods of displaying graphical information. More particular-

  The present invention relates to apparatus and methods

  direct memory access (DMA) to produce and process ima-

  ges and data on a display system. In the data processing industry, it is conventional to represent and transport information to a user by graphical representations. These representations can take various forms, for example alpha-numeric characters, graphics in Cartesian or other coordinates, as well as forms of well-known physical objects. Historically, interfaces between humans and

  computers took place via computer systems

  discrete mandes which typically include a combination of text and symbolic mathematical characters. The examples of such systems are numerous and include the programming languages FORTRAN, ALGOL, PL1, BASIC and COBOL which transform a given set of commands from a user into "object" code

machine-executable.

  However, the ease with which a user becomes efficient at programming or interconnecting with a system comprising a computer is generally a function of how close the system is to the logical thinking of the user himself. A system that has been developed to minimize the learning and acclimatization period that a user must go through to become effective in interacting with his computer system is frequently referred to as an "object-oriented" system. This system can use multiple "windows" displayed on a cathode ray tube (CRT) on which combinations of text and graphics are used to convey information. For example, each window can take the form of a folder page of the type used in a standard folder, covering other folders, the completely visible "upper" page constituting the current working folder. A user can add or delete information from a window, refill the folder page in another location, and generally act on windows exactly as if actual desktop folders were used. Thus, by graphically representing an image which represents the object of the user's commands and allows the user to act on an image and to process it in substantially the same way as if the image constituted the real object, the machine becomes

  easier to operate for the user and a human interface

stronger machine is realized.

  A historical limitation to the use of window-based displays exists in the case where animation inside a window is desired. In such a case, a series of sequential frames of data is displayed in a window over time, thus appearing to the user as if the displayed object was animated, for example as in a television or movie presentation. . However, speed limits for memory access have historically made animation of images difficult to achieve. The time taken by the central processing unit (CPU) to read data including an image from a memory and then display this data has generally been rather long and the images do not appear as "moving" d 'one frame to another in a continuous and fluid way. As will be described, the present invention provides a direct memory access (DMA) system which allows images stored in memory to be displayed in a window on a CRT at a speed which allows

achieve an animation effect.

  The present invention describes an apparatus and methods

  direct memory access (DMA) finding specific applications

  particulars for use in displaying animated digital images on a cathode ray tube screen. The present invention includes a DMA controller coupled by a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A

Z587520

  contiguous block of memory in the frame buffer is plotted on sequential picture elements (pixels) on the display. The frame buffer continuously analyzes the bit map representing the CRT screen so that changes to the data bits in the frame buffer are displayed correspondingly on the screen. A plurality of windows can be displayed on the CRT by having predefined variable widths which are appropriately represented in the frame buffer. Digital images stored as sequential "frames" of data in memory, such as a hard drive or RAM, can be transferred directly from memory to a frame buffer window for display without the need for provide for intervention by the central processing unit (CPU) and a recalculation of addresses. A user initially defines a window width. The window height results from the number of data transfers to be performed. A rectangular area is thus

  defined in which the graphic data will be transferred.

  The user then establishes a base address which corresponds to the initial memory address and is assigned to the origin of the

  predefined window, namely, the upper left pixel defined

  closing the window. A DMA controller initiates a read operation, resulting in a data frame defining the image being read sequentially from the disc or

  from main memory and writes to memory in a device

  graphic command. The graphics controller transfers the incident data to a window in the frame buffer for later display. The h6te software then waits for a predefined time interval ("T") to elapse before initiating any other data transfer operation. If additional frames are to be displayed, a new base address is established for the next sequential frame and the process repeats. Using the present invention, digital images stored in memory can be transferred directly to a "window" in the frame buffer at

  high speed, making it possible to achieve an animation effect.

  These and other objects, features and advantages of the present invention will appear in more detail in

  the following description of particular embodiments made

  in relation to the attached figures, among which: FIG. 1 represents a computer system incorporating the teachings of the present invention;

  FIG. 2 is a diagram in the form of blocks represented

  feeling an implementation of the present invention to allow DMA access and display of stored images; FIG. 3 symbolically represents the use of the DMA control device according to the present invention for data transfers comprising images stored on magnetic disks and for displaying such images in an animated manner; and Figure 4 is a flow diagram illustrating the sequence of operations according to the present invention for displaying images.

stored in a memory.

NOTATIONS AND NOMENCLATURE

  The following detailed description is largely

  presented in terms of algorithms and symbolic representations of operations on data bits in a memory

  computer. These descriptions of algorithms and representations

  are the means used by those skilled in the art in the field of data processing to most effectively transmit the

  substance of his work towards other men of art.

  An algorithm is here conceived as a self-

  consistent steps leading to a desired result. These stages are those requiring physical processing of physical quantities. Usually, although not necessary, these quantities take the form of electrical or magnetic signals which can be stored, transferred, combined, compared

  and manipulated in other ways. It is sometimes convenient, essential

  tially to satisfy current uses, to call these signals: bits, values, elements, symbols, characters, terms, numbers or the like. It should be borne in mind, however, that all of these and similar terms must be associated with the appropriate physical quantities and are simply

  convenient labels applied to these quantities.

  In addition, the manipulations carried out are often

  designated by terms such as addition, transfer or

  parison which are conveniently associated with mental operations performed by a human operator. No such human operator capability is necessary, or desirable, in most cases for all of the operations described herein which are part of the present invention; these operations are machine operations. Machines useful for performing operations according to the present invention generally include digital computers or similar devices. In all cases, it is necessary to keep in mind the distinction between the operations of the actuation process of a computer and the calculation process itself. The present invention relates to procedural steps.

  to operate a computer and process physical signals

  electrical, or other (eg mechanical, chemical, etc.)

  to produce other desired signals.

  The present invention also relates to an apparatus for carrying out these operations. This apparatus may be specially constructed for the required purposes (i.e., a direct memory access controller and a frame buffer), or it may include a non-specific computer selectively activated or conformed by a stored computer program. The algorithms and circuits presented here are not

  inherently linked to a computer or other device

particular.

  DETAILED DESCRIPTION OF AN EMBODIMENT OF THE INVENTION

  Apparatus and methods for direct memory access (DMA) for displaying digital images in animated form are

  described. In the following description, many details are

  statements such as bit numbers, architectures, sequences of operations, etc. to provide an accurate understanding of the present invention. However, it will be clear to those skilled in the art that the present invention can be implemented.

  works without these particular details. In other cases,

  well-known structures and structures are not described in detail so as not to unnecessarily obscure the presentation

of the present invention.

  Figure 1 shows a computer system for producing and displaying digital images according to the present

  invention. A central computer 10 (which in the embodiment

  tion currently preferred comprises a 32-bit MOTOROLA 68010 microprocessor) is coupled to a bus 12. The central computer 10 performs various functions including the execution of software

  provided by a user who can define images

  ges to display in windows on a cathode ray tube display (CRT) 14. A memory 15 is shown as coupled to the computer 10 allowing data to be transferred on the bus to the various data processing resources associated. To display images, the present invention uses a graphic controller 26 comprising a color frame buffer 18 coupled to the bus 12 and to the CRT 14. The frame buffer 18 comprises one or more "bit cards" of the screen d display of CRT 14. In each bit card, a memory block in the frame buffer 18 is allocated so that each memory address and data value is represented on a corresponding picture element (pixel) of the display system . Thus, for each bit card, the complete screen of the CRT is represented as 1 or else a 1 (for example foreground) or else an O (for example background) in a memory block called "bit card". In a multi-plane system, the "N-bit" value of each memory address is typically represented by a color map reference RAM to provide a range of colors for each pixel. The

  frame buffer 18 continuously analyzes the bit map shown

  both the CRT screen, as is well known in the art,

  so changes to bits of data in the tam-

  frame pon 18 are displayed correspondingly on the CRT 14. A DMA controller 20 is coupled to bus 12 and a hard disk drive 22. In addition, the DMA controller 20 can be coupled to a network 24, for example ETHERNET, DECNET or the like, or to additional hard disk drives or other memory devices. As shown in Figures 1 and 3, according to the present invention, a plurality of windows can be displayed on the CRT 14 by appropriately writing data to areas of the frame buffer 18. In practice, the frame buffer 18 comprises a bit card memory comprising a dynamic dual access RAM in which each byte of memory

  corresponds to one pixel on the CRT 14 display. In addition, the tam-

  frame pon 18 can include a plurality of bit cards representative of CRT 14, so that a memory set can

  be updated while another is read for display, the first

  mier ensemble being displayed while the second ensemble is updated and so on. This technique is called the double buffer technique and allows instantaneous passage from one image to the next without the visual effect of displaying a partially updated image. As shown, each window displayed

  on CRT 14 can include several alpha characters

  digital and / or graphics. The windows can be overlapped with respect to each other, thus giving the appearance of files placed on a desk. In most cases, the data to be displayed is processed by the CPU 10 by executing an application program. The data to be displayed is then transferred by the bus 12 in the frame buffer 18 comprising one or more bit cards. However, in the case where digital images have to be displayed in animated form, it has turned out that the processing requirements of the CPU 10 to access the image, located for example in memory 15, are too slow to perform a credible animation effect. In addition, the memory space required to store hundreds or thousands

  of pre-calculated images in a main CPU memory is pro-

  hibitively expensive compared to the cost of mass storage devices

  such as a disc 22. The present invention overcomes the limitations

  tions of the display systems of the prior art by providing a

  circuit in the DMA 20 control device which allows the

  command to read disc 22, or the data received at

  from network 24, comprising a frame of digital information

  risks defining an image, and displaying the image on the CRT 14 without it being necessary to provide processing by the CPU 10 and to use large amounts of the main memory of the CPU. The present invention allows a "window" to be defined

  on CRT 14 with a desired dimension and to write sequentially-

  data in part of the frame buffer 18 o is

located the window.

  In connection with FIGS. 1, 3 and 4, it will be assumed for example that a user wishes to have access to a sequence of digital images (called frame) stored on the magnetic disc 22. In the currently preferred embodiment, the CRT 14 and the corresponding bit map in the frame buffer 18 are organized so that the pixel in the corner

  upper left of screen 14 is designated as the point of ori-

  gine (0,0) of the display. Furthermore, in this embodiment, the CRT display 14 numbers each subsequent pixel along a scan line in a sequential linear fashion. Currently, there are 1,152 pixels along each scan line of the CRT 14 display, numbered 0 through 1151. The pixel beginning at the

  Next scan line is numbered 1152 and so on.

  The windows provided in the display screen are defined by areas containing the largest bit map, like this

  is better represented in FIGS. 1 and 3. According to the present invention

  tion, a user wishing to transfer sequentially and directly graphic images stored in digital form in a memory, such as memory 15 or disk 22, initially defines a window width inside each of the bit cards of the frame buffer. 18 and a corresponding zone of the CRT 14. As is better represented in FIG. 3, the window width defines a rectangular zone in which the graphic data will be transferred. In the currently preferred embodiment, the size of the image stored in the memory device corresponds to the size of the image which will then be displayed on the CRT 14 as stored in the frame buffer 18. For example, an image The digital memory stored in the hard disk 22 having dimensions of 512 × 512 bits will be displayed on the CRT 14 as an image with a width of 512 pixels and a height of 512 pixels. It is therefore important for the user to specify the window width which corresponds to the width of the images displayed in the window. The user

  then establishes the base address for memory access, which cor-

  corresponds to the initial memory address which will be assigned to the origin of the predefined window, namely the upper left point defining the window. In the example of FIG. 3, this base address point is called point "B". The DMA controller 20 then initializes a sequential read operation from which it results that a data frame defining the image is read from the memory (for example the hard disk 22 or the memory) and is transferred by the bus 12 in the frame buffer 18 at a predetermined address range. The logic provided on the control device 26 and the frame buffer 18 decides to

  the address provided and redirects incident data to the job

  appropriate cementing on the frame buffer comprising the desired window on the CRT 14. Following the transfer of the data to the frame buffer 18, these are then analyzed, in a manner known in the art, and displayed on the CRT 14. The host software then waits for a predefined duration (for example 1 / 24th or 1 / 16th of a second) before processing other operations on the data to display subsequent frames of digital graphic data. Those skilled in the art will note that, in the event that the tampon

  weft 18 is a double buffer (so for example that the tam-

  frame pon 18 contains two bit cards of full dimensions which can be alternately "toggled"), during the vertical return of CRT 14, the DMA controller 20 will alternate between the bit cards of the frame buffer for each

writing cycle.

  In the event that additional frames are to be displayed to provide an animated effect, the DMA controller 20 establishes a new base address for the next memory access and initiates additional read operations from memory to search for the frame next of the digital image. This cycle continues until all the frames

  are formed directly from memory through the

  of the DMA 20 control device and in the window

frame buffer 18.

  FIG. 2 represents a block diagram of part of the memory access logic in the frame buffer

  18. As will be described below, the circuit shown provides

  nit row address signals (RAS) and column address signals (CAS) which are coupled to the appropriate memory device storing the digital images. A user establishes an initial base address and supplies this address to the base counter 30. Similarly, the user establishes the width of the DMA window displayed on the CRT 14 by defining, in binary, the number of pixels corresponding to the width what must the

  window and writing this number to a register of width 32.

  The output of the width register 32 is coupled to a 12-bit counter 34 so that the width value is supplied to the

  counter 34 data loading inputs. The output terminal

  TC counting tie of a limit counter 36 is coupled to

  the counter validation input (CFN) of counter 30 which

  tera up to a predefined number of cycles before maintenance. For example, in the case shown in FIG. 3, the size of the CRT screen and, consequently, the size of the bit map of the frame buffer are 1152 pixels wide. This value represents the limit of the scan line length for the particular display system, the count value

  maximum for counter 36, and the number of cycles including

  tor 30 will advance before maintenance. A 20-bit counter 38 is loaded by the outputs Qx of the base counter 30, and the outputs Ox of the counter 38, as will be described, define the RAS and CAS addresses controlling the frame buffer memory

which we had access to.

  In the event that no DMA transfer is to take place, a system clock 39 increments the limit counter 36 from its initial value to its maximum count. Likewise, the system clock 39 simultaneously increments the base counter 30 from the base value initially planned. Once the limit counter reaches its maximum, it no longer increments and prevents the basic counter 30 from doing so as well. As a result, the final base value is equal to the initial base value plus the range of the limit counter (i.e. 1152). The value contained in the 20-bit counter 38 is the initial base address value since no DMA transfer has taken place. Thus, the 20-bit counter 38 has not been incremented. Likewise, the value in the width register 32 and the 12-bit counter 34 also remains the same

  since no DMA transfer took place.

  In the event that a DMA transfer from memory to frame buffer 18 is to take place, the initial base and width values are provided, as discussed above. Consequently, before the initialization of the DMA transfer, the initial basic value is stored in the basic counter 30 and the

  20-bit counter 38, and the initial width value from it

  The width register 32 is supplied to the 12-bit counter 34. As shown, the 12-bit counter 34 is incremented upon completion of each memory cycle by a signal supplied on line 40. Each cycle memory

  increments the 12-bit width counter 34 as well as the

  20-bit counter 38. Consequently, the 20-bit counter 38 provides

  nit a frame buffer address in incrementation for each new data received on the system bus 12. When the 12-bit counter 34 reaches the predefined maximum window width, a terminal counting signal (TC) is supplied on line 42 who

  reloads a new base value in base counter 30.

  As described above, the new base address provided will be the previous base address plus the limit value of the counter (i.e. 1152). The effect of loading this modified address into the base counter 38 is to advance the counter to the starting address of the next scan line in the defined window. In addition, the insertion of the signal TC 42 recharges the limit counter 36 so that it begins to count again again until its limit. In addition, the signal TC 42 reloads the value of the width provided in the width register 32 in the 12-bit counter 34, and causes

  its own disinsertion. The sequence of operations described is

  continues until the entire data frame has been read and stored in the frame buffer 18. Accordingly, apparatus and methods have been described for direct memory access for displaying digital images in animated form on a CRT. It will be noted that the present invention has been described in particular relation to FIGS. 1 to 4 but that it is however possible for a person skilled in the art to make various changes and modifications to the elements and arrangements of the elements of the invention without get out of the domain of it.

Claims (29)

  1. Apparatus for transferring data between a device   memory positive and a display, characterized in that it comprises: - display means (14) for displaying data, this display means comprising a display provided with several selectively validated display elements; - a frame buffer means (18) coupled to the display means for storing the data to be displayed, this frame buffer means comprising at least one bit card comprising a plurality of data bits, these bits representing the state d a display element on the display; - memory means (15) for storing data to be displayed, this data being stored in the form of a frame in the memory means and defined by unique address locations; - control means (20) coupled to the memory means and the frame buffer means for reading a frame of data from the memory means and transferring the data to selected locations of the frame buffer means, these locations being defined by a width value and a point of origin, said control means sequentially reading the data starting with a base address so that the data is   transferred in the order in which they will be read from   firing of the frame buffer for display; from which it follows that the data can be transferred at high speed to the display.   2. Apparatus according to claim 1, characterized in that the display elements are organized in scanning lines and in that the data in the memory means are read by the command line by line.   3. Apparatus according to claim 2, characterized in that the locations chosen in the frame buffer comprise a rectangular network, the locations of the network constituting a bit card subset.   4. Apparatus according to claim 3, characterized in that the locations defining the rectangular network are read by the control means in the order in which the data are   read from the memory medium.   5. Apparatus according to claim 4, characterized in that the control means reads successive frames of the stored image and transfers each of the data frames to the network.   rectangular separated by a duration "T".   6. Apparatus according to claim 4, characterized in that the width value and the base address are defined by the user. 7. Apparatus according to claim 2, characterized in that   that the control means comprises a buffer for storing time   porally each of the frames before transfer to the means of frame buffer.   8. Apparatus according to claim 1, characterized in that   that the data to be displayed includes a digital image.   9. Apparatus according to claim 4, characterized in that the control means comprises: - a basic counting means (30) for receiving the basic value; - a limit counting means (36) coupled by means of   basic counting to count up to a hand limit value   hold and then prevent the basic counting means from continuing to count; - width counting means (32, 34) for receiving the width value; - an address output counting means (38) coupled to the basic counting means and to the width counting means, the address output counting means providing signals   RAS and CAS output defining unified address locations   ques in the memory means; - system clock means (39) coupled to the base counting means for incrementing the base counting means and the limit counting means; a memory cycle signal generation means coupled to the width counting means for supplying a memory cycle signal for incrementing the width counting means and thus increment the RAS signal.   10. Apparatus according to claim 9, characterized in that the width counting means (34) provides a terminal count signal (TC) after reaching said width value, said signal (TC) reloading said width value in the width counting means, resetting the limit counter (36) and providing a new base address for   memory by means of basic counting (30).   11. Apparatus according to claim 10, characterized in that the basic counting means (30) comprises a 20-bit counter. 12. Apparatus according to claim 11, characterized in that the width counting means (34) comprises a counter   12 bits coupled to a width register (32).   13. Apparatus according to claim 12, earactérisé in that the address output counting means (38) comprises a 20-bit counter.   14. Apparatus according to claim 13, characterized in that the control means, the memory means and the means of   frame buffer are coupled to each other by a bus (12).   15. Method for transferring data between a device   memory and display in a computer display system   tor comprising a display means provided with a display with a   plurality of selectively validated display elements, character-   characterized in that it comprises the following steps: - storing the data to be displayed in a memory means, this data being organized in frames and defined by unique address locations; defining a data frame from the memory means and transferring the data to selected locations in a coupled frame buffer using the display means, this frame buffer comprising at least one bit card comprising a plurality of bits of data, these bits representing the state of a   display element on the display, the locations in the tam-   frame pon being defined by a width value and an origin point, the frame being read sequentially from a base address so that the data is transferred in the order in which it will be read from the buffer frame for display; from which it follows that the data is transferred at high speed to display.   16. Method according to claim 15, characterized in that the display elements are organized in scanning lines and in that the data stored in the memory means are read line by line.   17. The method of claim 16, characterized in that the locations chosen in the frame buffer comprise a rectangular network, the locations of the network constituting a bit card subset.   18. Method according to claim 17, characterized in that the locations defining the rectangular network are read by the control means in the order in which the data are   read from the memory medium.   19. Method according to claim 18, characterized in that the data are read in successive frames and transferred   to the frame buffer means separated by a duration "T".   20. The method of claim 19, characterized in that the width value and the base address are defined by the user. 21. The method of claim 20, further comprising a buffer for temporarily storing each of the frames before transferring the data frame to the buffer means. frame.   22. Method according to claim 21, characterized in that   that the data displayed includes a digital image.   23. Method according to claim 18, characterized in that the reading step is carried out by a control means comprising: - a basic counting means (30) for receiving the basic value; - a limit counting means (36) coupled by means of   basic counting to count up to a hand limit value   hold and then prevent the basic counting means from continuing to count; - width counting means (32, 34) for receiving the width value; - an address output counting means (38) coupled to the basic counting means and to the width counting means, the address output counting means providing signals   RAS and CAS output defining unified address locations   ques in the memory means; - system clock means (39) coupled to the base counting means for incrementing the base counting means and the limit counting means; a memory cycle signal generation means coupled to the width counting means for supplying a memory cycle signal for incrementing the width counting means and thus increment the RAS signal.   24. The method of claim 23, characterized in that the width counting means (34) provides a terminal count signal (TC) after reaching said width value, said signal (TC) reloading said width value in the width counting means, resetting the limit counter (36) and providing a new base address for   memory by means of basic counting (30).   25. The method of claim 24, characterized in that the basic counting means (30) comprises a counter at 20 bits.   26. Method according to claim 25, characterized in that the width counting means (34) comprises a counter with 12   bits coupled to a width register (32).   27. The method of claim 26, characterized in that the address output counting means (38) comprises a 20-bit counter. 2587S20   28. Method according to claim 27, characterized in that   that the control means, the memory means and the tam-   frame pon are coupled to each other by a bus (12).   29. Method according to claim 15, characterized in that the frame buffer comprises a plurality of bit cards, so that the contents of each of the bit cards are alternately displayed while the contents of another card bit is updated.