JPS636684A - Multi-image control device - Google Patents

Abstract

PURPOSE:To speed up processing by constituting a device so that superposed reading of image data stored in plural image memory to a frame memory can be executed only by one scanning. CONSTITUTION:The reading of picture element data corresponding to plural image memories 11-1N is executed so that picture element data in the image memory having the highest priority order out of the priority order applied to the image memories 11-1N by a priority order applying means 4 and having a flag indicating the picture data to be displayed are successively read out. Thereby, the superposed reading of image data from the plural image memories 11-1N to the frame memory 2 can be executed only by one scanning.

Description

[Detailed Description of the Invention] [Summary] To generate image data superimposed on frame memory,
Addresses flags that give read priority to the multiple image memories into which image data is sent, and that distinguish between display target pixel data and background pixel data for each address corresponding to each pixel data of the image data in each image memory. The image data is stored in the control memory, and in response to the priorities and flags, the overlapping reading of image data from a plurality of image memories into a frame memory is completed in one scan.

[Industrial application field]

The present invention relates to a multi-image control device, and more specifically, to a multi-image control device that can complete reading of image data from a plurality of image memories into a frame memory in a single scan.

Some image display devices write a plurality of image data in a superimposed state into a frame memory and display this on a display device.

In overlapping writing to the frame memory, control must be performed according to the degree of overlapping between these images. If this control cannot be carried out at high speed, there is a problem in that especially when the superimposition is changed, the changed screen does not appear instantaneously.

(Prior Art) The above-mentioned control in the past has been carried out as follows. When display object A of image memory A and display object B of image memory B are to be displayed on the display screen as shown in FIG. , a technique is used in which the display object B of the image memory B is first written in the area corresponding to the display screen of the frame memory, and then the display object A of the image memory A is overwritten thereon.

[Problem that the invention seeks to solve]

This conventional method has no means for recognizing the existence of an image to be superimposed on another image memory while scanning one image memory. Therefore, as mentioned above, when newly reading data into the frame memory, it is necessary to sequentially overwrite data in order from the lowest priority to the highest priority, which is the reason for the low speed performance.

The present invention was created in view of such problems, and an object of the present invention is to provide a multi-image control device that can write superimposed image data into a frame memory at high speed.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in the figure, the present invention includes a plurality of image memories 1. . . . It is stored for each address corresponding to each pixel data of the image data in each image memory based on the priority given to IN by the read priority assigning means 4, and whether it is display target pixel data or background pixel data. In response to the flag of the address control memory 5 that provides the distinction between the image data of the plurality of image memories 11...IN, the overlapping reading of the image data into the frame memory 2 is completed in one scan. be.

[For production]

A plurality of image memories 11... Each corresponding pixel data of IN is read out with the highest priority among those given to the image memories, and the flag indicates that it is pixel data to be displayed. This is done in such a way that pixel data in the image memory is read out sequentially. Therefore, overlapping reading from the plurality of image memories 11 . . . IN to the frame memory 2 can be performed in one scan.

〔Example〕

FIG. 2 shows an embodiment of the invention. In this figure, 1
1.12 is image memory A of the same size.

This is image memory B. The outputs of these image memories are connected to the frame memory 2. 3 is a CRT display device connected to the frame memory 2;

Reference numeral 4 denotes a read priority order assigning circuit for giving read priority orders to the images (image memories (A)ll, CB) 12. 5. is image memory 1. This is an address control memory that has the same size as , and stores a flag indicating whether it is display target pixel data or background pixel data corresponding to each pixel data.

6 is image memory (A) 11. (B) A readout circuit that reads out 12 bits, and refers to the readout priority order and the flag during the readout.

The operation of the device of the present invention configured as described above will be explained.

For convenience of explanation, data as shown in FIG. 3 is written into the image memory (A) 11, the image memory (B) 1*, and the address control memory 5 from the host device, and read priority is given by the father host device. It is assumed that a command is given to the circuit 6 indicating that the image memory A has a higher read priority than the image memory B, and the circuit 6 generates the output.

The readout circuit 6 refers to the readout priorities and flags when reading out the image memories A and B.

That is, the image data in the image memory A having a higher priority is read out. At the same time as this reading, the contents of the address one address ahead of the address from which the image memory A was read are read from the address control memory A.

The flag read from address control memory A is “0”
, that is, if the image data in image memory A becomes a background pixel, then the image memory (B) 1 with lower priority
2 is read from the address between the address of the flag that became "0". Then, when the flag becomes 1" again, the process switches to reading from the image memory (A) 11. The pixel data sequentially read from both memories is sequentially written to the frame memory 2, and then the display device 3 Provided for display.

Generation of superimposed image data on the frame memory 2 for display on the display device 3 is performed using the image memory l.
It ends with one scan of + and 12.

Displaying images A and B upside down can be done instantly by simply reversing the readout priority order.

In the above embodiment, the case where there are two image memories has been described, but there may be three or more. It is necessary to change the address control memory 41g9t and the readout circuit accordingly. Alternatively, the number of address control memories may be one, and each flag for each image memory may be stored at an address corresponding to pixel data read from each image memory.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to read image data stored in a plurality of image memories into a frame memory in a superimposed manner in one scan, thereby speeding up the processing.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a diagram showing an embodiment of the present invention, Figure 3 is a diagram for explaining the embodiment of Figure 2, and Figure 4 is a diagram explaining the conventional system. This is a diagram for 1 and 2, 1, . . . IN are image memories, 2 is a frame memory, 3 is a display device, 4 is a read priority assigning means (circuit), and 5 is a read circuit. ]) γ f-萱8 Kanoshu'a', ]"Yohi ε(h' to Fig. 11 for DI'l)" Fig. 2 Figure 3

Claims (1)

[Scope of Claims] A multi-image control device that superimposes image data of a plurality of image memories (1_1...1_N) on a frame memory (2) and displays it on a writing display device (3), comprising: (1_1...1_N); read priority assigning means (4) for assigning read priority to pixel data (1_1...1_N); an address control memory (5) that provides a distinction between the two; and an address control memory (5) that sequentially reads pixel data of the plurality of image memories (1_1...1_N) while switching reading of the plurality of image memories (1_1...1_N) in response to the read priority order and flag. A multi-image control device comprising: a readout circuit (6) for reading out data to the frame memory (2);