JP2001034258A - Picture display processing circuit and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the overlapping of pictures without making the access frequency and the read-out clock for a frame memory high speed. SOLUTION: A priority encoder 8 makes picture data whose priority are high to be read out from a frame memory 3 based on the display position monitored by a display position monitoring circuit 7 and the read out picture data are written in buffer memories 10, 11 in the order of the increasing of the priority. When picture data are not present in the display position, transparent color data are written in the position. By this operation, only picture data having high priority is written in the buffer memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display processing circuit for realizing superimposition of screens, and more particularly, to an OSD (On S
LSI for creen display) and LS for car navigation
The present invention relates to an image display processing circuit for displaying an image such as I.

[0002]

2. Description of the Related Art For example, on a display of a car navigation system, a plurality of screens such as a map screen, a screen indicating a direction in which an operator should go, and a screen indicating other information such as radio reception frequency information are superposed. May be displayed. For example, while navigating, when the current position of the operator is displayed on the map, for example, when there is an intersection to turn right in the traveling direction of the operator, a screen indicating that the intersection should be turned right is displayed on the display. Will be.

FIG. 3 shows a circuit for outputting image data while controlling the superposition of screens in a car navigation system, for example.

As shown in FIG. 3, in a circuit for outputting an image, image data input from an external device such as a microcomputer is
After being stored in the input data buffer RAM 31, it is once stored in the large-capacity image memory 33 (frame memory) via the data input / output selector 32. The image data to be actually displayed is read from the stored frame memory 33 and output as display data.

[0005] The superposition of images is realized as follows. First, the pixel data of each image for the overlapping images is
It is read from the frame memory 33 in advance. Next, the pixel data of each image is compared at the same time, and
One pixel data is selected. The selected pixel data becomes display output data as a superimposed image. Hereinafter, a specific description will be given.

First, in order to simultaneously select display output data from the pixel data of each image so as to obtain a superimposed image, the pixel data of each screen is kept until all the pixel data for the superimposed screen is completed. You have to store the data. Therefore, a plurality of buffer memories or buffer registers corresponding to each screen are required.

In FIG. 3, the data read from the frame memory 33 is further stored in the plurality of buffer memories 34.
To 36. The pixel data of each image stored in the buffer memories 34 to 36 is read from each buffer memory at the same timing and input to the data selector 37.

The data selector 37 selects pixel data of an image to be output from pixel data of each image stored in each buffer memory. As the data to be output, pixel data having a high priority among a plurality of screens is preferentially selected. Data selector 3
At 7, the pixel data of each screen is compared, and if a certain pixel is transmission color data, it is selected to output the pixel data of the lower image.

Here, the transmitted color data is data indicating whether or not the pixel is transparent. For example, if the transmitted color data in the pixel data is 8 bits "00H" and indicates a transmitted color, , Other data indicate data other than the transparent color. Specifically, it is data as to whether or not to display data with the next lower priority. The upper and lower sides of the image (pixel) to be superimposed are determined by the priority set for the image based on the output of the priority encoder 39.

FIG. 2 shows an example in which three images A, B and C are superimposed. Now, the priority is A
Is the highest and decreases in the order of B and C.
C has no transmission color data.

In the data output selector 37, first,
It is determined whether or not a certain pixel A ′ in the image A having the highest priority has a transmission color. When the pixel A 'is not the transmission color data, the pixel A' becomes a display pixel as it is. However, when A 'is the transmission color data, the lower pixel, that is, the pixel B' in the image B having the second priority is a candidate for the display pixel output.

Next, when the pixel B 'is determined to be a display pixel output candidate, it is determined whether or not the pixel B' in the image B is also a transparent color, as in the case of the image A. When the pixel B 'is not a transparent color, B' is a display pixel as it is, and when the pixel B 'is a transparent color, a further lower C' is a final display pixel.

In this manner, the selected pixel data is input from the data output selector 37 to the color conversion table 38. The output is converted into an RGB output, a YCbCr output, or a YUV output by the color conversion table, and becomes an actual display output.

For example, for example, according to the NTSC system 72
When outputting an image to a monitor having a screen size of 0 pixels × 480 lines, in a case where data of 720 pixels exists for each line of the frame memory, the configuration as shown in FIG. 1 is used as described above. It is possible.

[0015]

However, when it is desired to display an image as shown in FIG. 4A by using the circuit of FIG. 3, the image is stored in the frame memory 33 in a state as shown by b. In such a case, it is necessary to fill a portion irrelevant to the actual display, for example, around the pattern i, with the transparent color j. It is necessary to store image data other than the actual image display, and a large capacity of the frame memory 33 is required. In order to avoid the above situation and effectively utilize the capacity of the frame memory 33, it is conceivable to store only the images required for display in the frame memory 33 as shown in c.

In particular, in recent years, data stored in the frame memory 33 has increased due to an increase in the size of a display screen in a navigation system or the like. However, there is a problem that the data cannot be stored in the frame memory 33.

Further, since the processing time from the reading of the frame memory 33 to the display until the display is substantially fixed, when the screen size increases, the frequency read from the frame memory 33 increases in order to increase the amount of data read per unit time. Was higher. Further, even if the read frequency is increased, data for an image to be superimposed may not be read due to a large amount of image data. In this case, there is a problem that the read frequency must be further increased.

For example, a display output rate (also referred to as a pixel clock) of a screen size of 720 pixels × 480 lines is 1
In the case of 3.5 MHz, if pixel data for two screens is read from the frame memory within a predetermined time, the frequency read from the frame memory 33 is at least 27.
MHz is required. However, 1920 pixels x 1080
When a large size display such as a line is displayed, the pixel clock is 74.25 MHz, and when pixel data for two screens is read from the frame memory 33, it is at least 14 pixels.
8.5 MHz is required.

As described above, as the screen becomes larger, the frequency read from the frame memory 33 must be increased in order to read all the display data for the superimposed images. However, since the access frequency for reading from the frame memory 33 has an upper limit depending on the performance and specifications of the memory, there is a limit to increasing the read frequency. At present, the access frequency of an SDRAM (Synchronous DRAM) frequently used as a frame memory is 125 to 143M even at the fastest.
Hz.

On the other hand, assuming that the capacity of the buffer memories 34 to 36 is the memory capacity of one line, the larger the screen is, the larger the number of pixels per line is, so the circuit scale is increased. Further, when a plurality of buffer memories are provided corresponding to the screens to be superimposed, a problem occurs when the capacity of the buffer memory increases.

[0021]

According to the present invention, there is provided an image display processing circuit for controlling superimposed display of a plurality of images.
The display position of the screen is monitored, and among the image data of a plurality of images, the image data having the highest priority at the display position is selected and output as display data.

An image display processing circuit for controlling superimposed display of a plurality of images, further comprising storage means for storing display data, wherein the storage means indicates which one of the plurality of images is to be brought to the front. And image data as display data is stored based on the position of each superimposed image data.

Further, in an image display processing circuit for controlling superposition display of a plurality of images, an image memory for storing image data to be superimposed, a monitoring circuit for monitoring a display position, and a monitoring circuit for monitoring the display position Readout means for selectively reading out the image data having the highest priority from the image memory for each display position to be read, and storage means for storing the readout image data as display data. Features.

[0024] Further, there is provided a setting means for setting data for determining the priority of superposition. Further, a writing circuit for writing the transmission color data into the storage means when there is no image data at the image position is provided.

In particular, the read means determines a read address of the image memory according to a priority.

According to the present invention, the coordinate position of the screen to be displayed is monitored, and the image data having the highest priority at the display position is output. Therefore, it is possible to always read only high-priority image data from the frame memory, and it is not necessary to read data of a plurality of images.

[0027]

FIG. 1 is a diagram showing an embodiment of the present invention. An input buffer RAM 1 stores image data from an external device such as a microcomputer or a CPU, and has a role of buffering a transfer clock from the external device and the internal clock of FIG. 2 is an input / output selector, 3 is a frame memory for storing image data corresponding to a plurality of images, and selects image data read from the input buffer RAM 1 when writing to the frame memory 3; When reading from the frame memory 3, the image data from the frame memory 3 is selected. Reference numeral 4 denotes an address control circuit which controls designation of a write / read address of the frame memory 3 and writing and reading. Reference numeral 5 denotes a write image selection unit, which controls the address control circuit 4 so that image data input from the outside is written in a predetermined area of the frame memory 3. The write image selection unit 5 controls the address control circuit 4 based on a write address of an external device and a write operation instruction. Reference numeral 6 denotes a read image selection unit, which controls the address control circuit 4 so as to select and read image data stored in the frame memory 3.

Reference numeral 7 denotes a display position monitoring circuit which monitors the actual display position on the coordinates of the screen. Display position monitoring circuit 7
Has a counter (not shown) that counts at least the positions of the coordinates X and Y. Reference numeral 8 denotes a priority encoder, which selects an image in descending order of priority in pixel data at a certain display position and controls a read-out image selection unit to read out the image. The priority encoder 8 receives the priority of each screen from an external device, determines a read address in accordance with the display position information and the priority information output from the display position monitoring circuit 7, and converts the image data with a high priority. Select and read from the frame memory 3. Reference numeral 9 denotes a write selector as a write circuit, and reference numeral 10 denotes a buffer memory, which stores image data read from the frame memory 3 via the input / output selector 2. Further, the write selector 9 sets the display position at a certain display position.
When there is no image data, the transmission color data is selected and stored in the buffer 10. Therefore, the buffer 10 stores the image data with the highest priority. The gist of the present invention is to select the image with the highest priority and store it in the buffer memory.

Reference numeral 11 denotes a readout circuit, and reference numeral 13 denotes a color conversion table, which converts the output of the readout circuit 11 into, for example, an RGB output.

FIG. 5 shows an example in which three images A, B and C are superimposed. It is assumed that the priority is highest in A and lower in order of B and C. Further, it is assumed that the images B and C have no transmission color data. The display positions are as follows, for example. Image A: display start coordinates (Xs, Ys) = (20,
0), display end coordinates (Xe, Ye) = (99, 1
9). Image B: display start coordinates (Xs, Ys) = (50,
0), display end coordinates (Xe, Ye) = (139, 3
9). Image C: display start coordinates (Xs, Ys) = (10,
0), display end coordinates (Xe, Ye) = (709, 9)
9).

The display position data as described above is transferred from the external device to the priority encoder 8. The priority information of the images A, B, and C is also transferred to the priority encoder 8. The display position data is output to a detector of the display position monitoring circuit 7, and the detector performs detection based on the display position data. On the other hand, the detection output of the detector is input to the priority encoder 8, and the priority encoder 8 changes the selection of the frame memory 3 based on the detection output.

That is, when the images are superimposed, the display position monitoring circuit 7 and the priority encoder 8 determine, for each pixel, a high-priority image and the display position of the image A, B, and C. Monitor if it is. Further, the priority encoder 8 selects an image in descending order of priority at a certain pixel, and sets the output as priority 1.

Next, the operation of FIG. 1 when the first line 0 of the image to be displayed as shown in FIG. 5, ie, the Y coordinate is 0, will be described. FIG. 6 shows an image corresponding to the X coordinate of the line 0.

The counting of the X and Y counters of the display position monitoring circuit 7 is started from (X, Y) = (0, 0). When the Y coordinate is 0 (line 0), no data is read from the frame memory 3 when the X coordinate is between 0 and 9 because there are no pixels to display. Instead, based on the priority information of the priority encoder 8, a transmission color data write command is output from the display position monitoring circuit 7 as the priority 1, and the transmission color data is written into the buffer memory 10.

Subsequently, while the X coordinate is between 10 and 19, the display monitor circuit 7 detects (X, Y) = (9, 0) and outputs X and Y.
When the counter reaches (X, Y) = (10, 0), the display position monitoring circuit 7 determines the display of the image C based on the display position data. Further, based on the detection output of the display position monitoring circuit 7, the priority encoder 8 controls to selectively read out the pixel data of the image C in the frame memory 3. As a result, image C is read from frame memory 3 as priority 1. Therefore, the pixel data of the image C is written in the buffer memory 10. Such control is performed by setting the X and Y counters to the coordinates (19, 0).
It is performed continuously while counting up.

Further, while the X coordinate is between 20 and 49, the display monitor circuit 7 detects (X, Y) = (19, 0), and the X and Y counters determine (X, Y) = (20, 0). Fig. 5
The display of the image A is started as shown in FIG.
The display of images A and C is determined based on the display position data. Also, based on the detection output of the display position monitoring circuit 7, the priority encoder 8
Control is performed so that pixel data of the middle image A is selectively read. As a result, image A is read from frame memory 3 as priority 1. Therefore, the pixel data of the image A having a high priority is written in the buffer memory 10. Such control is continuously performed while the X and Y counters are counting up to the coordinates (49, 0).

Next, while the X coordinate is between 50 and 99, the display monitor circuit 7 detects (X, Y) = (49, 0) and outputs X and Y.
When the counter reaches (X, Y) = (50, 0), the image display B is started as shown in FIG.
The display of images A, B, and C is determined based on the display position data. Further, based on the detection output of the display position monitoring circuit 7, the priority encoder 8 controls to read the pixel data of the image A in the frame memory 3. As a result, the image A is read from the frame memory 3 as the priority 1 respectively. Therefore, the pixel data of the image A having a high priority is written in the buffer memory 10. Such control is based on X and Y
This is continued while the counter is counting up to the coordinates (99, 0).

Further, while the X coordinate is between 100 and 139, the display monitor circuit 7 detects (X, Y) = (99, 0), and
When the Y and Y counters reach (X, Y) = (100, 0), the display range of the image A on the line 0 has ended as shown in FIG. The display of images B and C is determined based on the images. Also,
Based on the detection output of the display position monitoring circuit 7, the priority encoder 8 controls the pixel data of the image B in the frame memory 3 to be read. As a result, image B
Are read from the frame memory 3 as the priority 1 respectively. Therefore, the pixel data of the image B having a high priority is written in the buffer memory 10. Such control is performed by setting the X and Y counters to the coordinates (13
This is performed continuously while counting up to 9,0).

Next, since the display range of the image B on the line 0 has ended while the X coordinate is 140 to 709, the display position monitoring circuit 7 detects that only the image C is displayed. Therefore, the circuit of FIG.
The same operation is performed as when the value is between .about.19. As a result, the pixel data of the image C is written in the buffer memory 10.

Next, since the entire display range on the line 0 has been completed while the X coordinate is between 710 and 719, the circuit of FIG. 1 performs the same operation as when the X coordinate is between 0 and 9. As a result, the buffer memory 10 is written.

The pixel data for one line written in the buffer memory 10 as described above is read out in accordance with the display timing of an external display device. The output data from the buffer memory 10 is output via the readout circuit 11 and is converted into an output such as RGB by the color conversion table 13 to be an actual display output.

Thereafter, when the X counter counts up to 719 in the display position monitoring circuit 7, the Y counter becomes 1
The reading of the pixel data for line 1 is incremented by one and executed as described above. Also, NTSC
In the case of the system, the same operation in the X direction is repeated 480 times in the Y direction, that is, the line direction, so that one screen having a display size of 720 × 480 can be output.

For line 0, the pixel data stored in the buffer memory 10 is as shown in FIG. This indicates that the buffer memory 10 stores pixel data with high priority in each image. As described above, since it is not necessary to read out a plurality of image data from the frame memory 3, it is possible to sufficiently overlap the images without increasing the access frequency or the read clock of the frame memory 3.

Next, the buffer memory 10 shown in FIG. 1 will be described. If the buffer memory 10 is, for example, a line memory capable of storing 720 pixels in accordance with the NTSC system, when the current line, for example, line 0 is read from the line memory, it cannot be overwritten on the line memory. To prepare the next line, for example line 1,
Originally write pixel data corresponding to line 1
Two line memories are provided.

In the configuration shown in FIG. 1, the capacity of the buffer memory is not set to a capacity capable of writing all the 720 display pixels in the line direction, but is set to a line memory for 256 pixels. Each bank is divided into 128 pixels. 1 buffer memory to 2
By using 56 pixels, the circuit scale is reduced. The buffer memory 10 serves as a data buffer for 128 pixels instead of a line memory for 720 pixels, for example.

The above two banks are referred to as bank 0 and bank 1, and the operation of each bank will be described. When data is read from the buffer memory from bank 0, writing to the buffer memory is performed from bank 1
Conversely, when data is read from the buffer memory from the bank 1, writing to the buffer memory is performed from the bank 0.

Since data must be output from the buffer memories 10 and 11 at a constant rate in accordance with the display pixel clock, writing to the buffer memory is performed by reading from the frame memory in time for this display rate. The data is written in the respective banks of the buffer memories 10 and 11.

[0048]

According to the present invention, the display position of the screen can be monitored, and the pixel data having the highest priority can be displayed at that position according to the priority. Therefore, it is possible to prevent the access frequency and the read clock of the frame memory from increasing. Also, since only one buffer memory is required, LSI
This is effective in reducing the circuit area and power consumption. Since the image data to be displayed is stored in the image memory, and the image data is read from the image memory according to the display position and the priority of the screen, the frame memory can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram for explaining superposition of images.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing a memory map in an image memory 33 of FIG. 3;

FIG. 5 is a diagram showing image superposition on one screen according to the present invention.

FIG. 6 is a diagram showing the superposition of images at line 0 on the screen according to the present invention.

FIG. 7 is a view showing image data written in a buffer memory 10 of FIG. 1;

[Explanation of symbols]

 3 Image memory 4 Address control circuit 5 Write image selection unit 6 Read image selection unit 7 Display position monitoring circuit 8 Priority encoder 9 Write selector 10 Buffer memory 11 Read selector

Claims (8)

[Claims] An image display processing circuit for controlling superimposed display of a plurality of images, wherein a display position of a screen is monitored, and among image data of a plurality of images, image data having the highest priority at the display position is determined. An image display processing circuit for selecting and outputting as display data. 2. An image display processing circuit for controlling superimposed display of a plurality of images, comprising storage means for storing display data, wherein the storage means indicates which of the plurality of images is to be brought to the front. And an image display processing circuit for storing image data as display data based on the position of each superimposed image data. 3. An image display processing circuit for controlling superimposed display of a plurality of images, comprising: an image memory for storing image data to be superimposed; a monitoring circuit for monitoring a display position; Readout means for selectively sequentially reading out the image data with the highest priority from the image memory for each display position to be performed, and storage means for storing the readout image data as display data. Characteristic image display processing circuit. 4. The image display processing circuit according to claim 3, further comprising setting means for setting data for determining the priority of superposition. 5. When there is no image data at the image position,
4. The image display processing circuit according to claim 3, further comprising a writing circuit for writing transmission color data into said storage means. 6. The image display processing circuit according to claim 3, wherein said read means determines a read address of said image memory according to a priority. 7. An image display processing method for controlling superposition display of a plurality of images, wherein a position of a screen is monitored, image data having the highest priority is selected at the display position, and the selected image data is stored. An image display processing method, wherein the method is stored in a means. 8. When there is no image data at the display position,
8. The image display processing method according to claim 7, wherein the transmission color data is written into said storage means.