JP2003274137A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a processing speed. <P>SOLUTION: An image compositing circuit 105 for exclusive use which composites images of foreground data 1 and background data 4 in memory areas 106 and 107 is provided independently of a CPU 101, so that an image compositing speed is increased. Image data is transferred from the image compositing circuit 105 to a display memory 21 through a bus 116 for exclusive use different from a CPU bus 104, so that the image data is quickly transferred. As a result, an image is quickly displayed on a screen of a display device 12. Sizes of memory areas 106 and 107 are variably set in accordance with the data quantities of the foreground data 1 and the background data 4 to be stored therein, so that an incorporated memory 102 is effectively utilized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for synthesizing a plurality of different images via a memory for display.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for multimedia processing that handles voice, video, and other types of information in an integrated manner. Further, in a mobile terminal device such as a mobile phone, high-speed communication is possible, a high level function is being provided, and the added value is also increasing. Also, terrestrial digital broadcasting will be started in television broadcasting. Against this background, moving images can be distributed in portable terminal devices, and higher-speed image processing in portable terminal devices is desired.

Conventionally, in a portable terminal device, when images are combined and displayed on a screen, a frame memory corresponding to the size of the screen is prepared for each of a plurality of combined images, and the frame memory is built in the portable terminal device. CPU (Central Processing U
nit) reads image data from the frame memory for each image and performs arithmetic / composite processing on the read image data as needed. The data of the calculated / synthesized image has been transferred by the CPU to the display device controller or the display device via the CPU bus in order to display it on the screen.

The structure for the conventional image synthesizing function in the portable terminal device is shown in FIGS. FIG. 6 shows an excerpt of a part of the configuration of FIG. 5 and 6
In the mobile terminal device, a controller 500 including a one-chip LSI (Large Scale Integration), a display device controller 51 having a built-in display memory 511, and an LCD (Liquid Crystal Displa) are used for the mobile terminal device for the image synthesizing function.
y) and other display device 52 and controller 5
RAM (Random Access Memor)
y) 53 is included. Each of these units communicates data and signals with the CPU 501 via a CPU bus 504 indicated by a thick arrow in the figure. Display device controller 51
Transmits a control signal for driving the display device 52 and data for display to the display device 52.

The controller 500 includes a CPU 501 for centrally controlling and managing the portable terminal device itself, a memory 502 built in the controller 500, a control register section 503 and an address generating circuit 505. The built-in memory 502 includes frame memories 605 and 606 and a calculation memory 607. The display memory 511 of the display device controller 51 stores the image data 50. The image data 50 corresponds to the display image on the display device 52. A screen image displayed on the display device 52 is created in the display memory 511.

Image data 50 is stored in the frame memory 605.
The foreground data 30 of is stored. Frame memory 606
The background data 40 of the image data 50 is stored in. The calculation memory 607 is assigned as a work area for calculation by the CPU 501. Frame memory 605
And 606 each have a memory capacity capable of storing image data for one screen of the display device 52. Here, the foreground data 30 refers to the data of the image displayed at the front when it is displayed on the screen of the display device 52, and the background data is the data of the image displayed at the back. Refers to data. Therefore, on the screen of the display device 52, the foreground data 30 is displayed so as to be superimposed on the background data 40.

Image synthesizing procedures by the image synthesizing functions of FIGS. 5 and 6 are shown in FIGS. 7 (A) and 7 (B). Figure 7
In (A), the foreground data 3A having a size corresponding to one screen of the image data 50 is stored in advance in the frame memory 605, and the image data 50 is stored in the frame memory 606.
The background data 4A having a size corresponding to one screen is stored in advance.

The control register 503 has a frame memory 6
Read start and end addresses for reading data from 05 and 606 are stored in advance. The CPU 501 operates as follows when starting image synthesis. First, when an image read signal is output to the control register 503,
The read start address and the end address are output from the control register 503 and applied to the address generation circuit 505. The address generation circuit 505 generates a read address based on the applied address. When data is read from each of the frame memories 605 and 606 based on the generated read address, the CPU 501 inputs the read data via the CPU bus 504, and the input data via the CPU bus 504. Then, the synthesis processing is performed while accessing the calculation memory 607. CPU 501
Writes the data resulting from the combining process to the display memory 511 outside the controller 500 via the CPU bus 504. When the synthesizing process is completed, the image data 50 is stored in the display memory 511.
0 is the display memory 51 by the display device controller 51.
It is read from the display device 1 and displayed on the screen of the display device 52.

After that, when the foreground data 3A in the frame memory 605 changes to the foreground data 3B in FIG. 7B,
Similarly to the above, the CPU 501 inputs the data read from the built-in memory 502, the combination processing of the input data, and the display memory 511 of the result data of the combination processing.
The image data 50 obtained by the writing result is displayed on the display device 52.

As described above, in image composition, the CPU
Reference numeral 501 denotes input of data corresponding to an image for one screen from a built-in memory, synthesizing processing (arithmetic processing), and display memory 5.
All data transfer to 11 will be performed.

FIG. 8 is a flow chart showing a conventional procedure for image synthesis. Here, it is assumed that the foreground data 30 and the background data 40 are stored in advance in the built-in memory. Referring to FIG. 8, CPU 501 sets the read start and end addresses for reading foreground data 30 and background data 40 from frame memories 605 and 606, respectively, in control register section 503 during image composition (S82). . Control register unit 503
When the data of the foreground data 30 and the background data 40 are respectively read from the frame memories 605 and 606 based on the address generated and output by the address generation circuit 505 based on the setting contents of the CPU 501,
Inputs the data read via the CPU bus 504 and performs a combining process on the input data using the arithmetic memory 607 (S83 to S85). CPU 501
Writes the data of the result of the combining process to the display memory 511 outside the controller 500 (outside the LSI chip) via the CPU bus 504 (S86). After that, CPU5
01 determines whether or not the combining process using the image data for one frame is completed (S87). If it is determined that the processing has not ended, the processing of S82 to S86 is repeated in the same manner. If it is determined that the image composition is completed (Yes in S87), the image composition is completed. At this time, the image data 50 is stored in the display memory 511, and the image data 50 is read from the display memory 511 and displayed on the screen of the display device 52.

As described above, the CPU 501 operates in the built-in memory 50 during the period in which the synthesizing process is performed on one screen image.
Since the data of the image for one screen read from No. 2 is input, the synthesizing process (arithmetic process) using the input data and the data of the synthesizing process result are transferred to the display memory 511, this period is The CPU 501 could not execute other processing.

Further, since the foreground data 30 always consumes the capacity of the frame memory 605 corresponding to one screen regardless of the data amount, the memory capacity of the internal memory 502 is wasted.

Further, in the synthesis processing, the CPU bus 50
Display memory 51 external to the controller 500 via
Since the data was transferred to No. 1, it was difficult to speed up the synthesizing process. That is, although the CPU 501 can access the built-in memory 502 in the same LSI chip at high speed, when writing data to the display memory 511 outside the LSI chip via the CPU bus 504,
The transfer speed is low, and as a result, the speeding up of the image synthesizing process is hindered.

Further, Japanese Laid-Open Patent Publication No. 11-355705 discloses an image processing device for synthesizing images captured by a digital camera. In this image processing device, the CPU controls the reading and writing of image data to be combined from the magnetic disk, and the image data to VRAM (Vi
Since the CPU is responsible for control of writing to the deo RAM), the load on the CPU is high and other processing cannot be executed, resulting in a decrease in processing efficiency.

Japanese Unexamined Patent Publication No. 6-180574 and Japanese Unexamined Patent Publication No. 2000-181441 show an image processing apparatus for displaying an image by combining a background image and a sprite image. In this image processing device, VR
Since the data storage area is fixedly assigned to each of the background image and the sprite image in the AM, a certain area is always consumed in the VRAM regardless of the data amount of the background image and the sprite image. As a result, the memory area cannot be effectively used.

Therefore, it is an object of the present invention to provide an image processing device capable of processing an image at high speed.

Another object of the present invention is to provide an image processing apparatus capable of processing an image at high speed while effectively utilizing a memory area.

[0019]

An image processing apparatus according to an aspect of the present invention includes a plurality of image storage areas that are set corresponding to a plurality of image data and store the corresponding image data. The data storage unit is connected to a dedicated bus, and the image data input via the dedicated bus is read from a plurality of image storage areas and a display storage unit that stores as display image data corresponding to the image displayed on the screen. An image generation unit that inputs a plurality of image data, generates image data that is combined by performing image processing, and outputs the generated image data to a display storage unit via a dedicated bus, and a dedicated bus. Includes a processing unit that executes a plurality of types of processing except image processing while transferring data to another via different data buses.

In the above-described image processing apparatus, the image processing unit is provided with a dedicated image generation unit for performing image processing on a plurality of image data in a plurality of image storage areas, separately from the processing unit, so that the image processing speed is increased. In addition, since the image data is transferred from the image processing unit to the display storage unit via a dedicated bus different from the data bus to which the processing unit transfers data for executing a plurality of types of processing, The display image data can be transferred to the storage unit for high speed and stored. As a result, it is possible to quickly display the image on the screen. In addition, the processing unit is relieved of the burden of image processing and can execute other types of processing in parallel with the image processing.

In the above-mentioned image processing apparatus, preferably, the sizes of the plurality of image storage areas in the data storage unit are variably set according to the amounts of the plurality of image data.

Therefore, the size of the image storage area in the data storage unit is not fixed but can be set according to the actual data amount of the plural image data to be stored therein, so that the capacity of the data storage unit can be effectively used. it can.

In the above-mentioned image processing apparatus, it is desirable that the amount of image data is determined in correspondence with the size for displaying the screen. Therefore, the size of the image storage area in the data storage unit can be set according to the display size of the screen for displaying the image generated by the image processing.

In the above-mentioned image processing apparatus, it is desirable that the amount of image data is determined corresponding to the types of the plurality of image data to be combined. Therefore, the size of the image storage area in the data storage unit can be set according to the type of image data to be combined.

In the above image processing apparatus, it is desirable that the amount of image data is determined in correspondence with the size of display image data. Therefore, the size of the image storage area in the data storage unit can be set according to the size of the display image data stored in the display storage unit and displayed on the screen.

In the above-mentioned image processing apparatus, it is desirable that the plurality of types of processing executed by the processing unit accept image data supplied from the plurality of image data, and accept the received image data as a corresponding image. When one or more image data of the plurality of image data are changed, including the data writing process of writing in the storage area, the one or more changed image data is supplied to the data writing process. It

Therefore, when only one or more image data among a plurality of image data are changed and other image data are not changed, the data writing process is performed on one or more changed images. Only the data needs to be written in the corresponding image storage area, the processing efficiency is excellent, and the load on the processing unit is reduced.

In the above-mentioned image processing apparatus, preferably, in the image displayed on the screen when one or more image data of the plurality of image data in the plurality of image storage areas are changed,
The display storage unit further includes an image data reading unit which reads out image data of a plurality of image data portions for combining the partial images combined using the changed image data from the plurality of image storage areas. The data corresponding to the stored partial image of the display image data is updated using the image data input via the dedicated bus.

Therefore, the display image data in the display storage unit can be updated only by the data corresponding to the changed partial image, and the update processing time of the display image data can be shortened.

In the above-mentioned image processing apparatus, preferably, the data storage unit is connected to a data bus, and a processing storage area for storing data accessed for a plurality of types of processing executed by the processing unit. Further includes.

Therefore, the data storage section can be utilized as a processing storage area which is a work memory for the processing section to execute a plurality of types of processing. Further, since the sizes of the plurality of image storage areas are variably set as described above, if the size of the processing storage area is also variable, the empty area generated by the setting change may be allocated to the processing storage area. It becomes possible, and multiple types of processing can be executed at high speed.

According to another aspect of the present invention, the image processing apparatus is
A data storage unit that is set corresponding to each of a plurality of image data and includes a plurality of image storage areas in which the corresponding image data is stored, and a dedicated bus for image data are connected.
An image is input by inputting the image data input via the dedicated bus as display image data corresponding to the image displayed on the screen as display image data, and the plurality of image data read from the plurality of image storage areas. An image generation unit that generates combined image data by processing and outputs the generated image data to a display storage unit via a dedicated bus,
The size of the plurality of image storage areas in the data storage unit is
It is variably set according to the amount of a plurality of image data.

Therefore, in the above-mentioned image processing apparatus, the image processing unit is provided with the dedicated image generation unit for performing the image processing on the plurality of image data in the plurality of image storage areas, so that the image processing is speeded up. Further, since the image data is transferred from the image processing unit to the display storage unit via the dedicated bus, the display image data can be transferred and stored in the display storage unit at high speed.
As a result, it is possible to quickly display the image on the screen.

Further, since the size of the image storage area in the data storage unit is not fixed but can be set according to the actual data amount of the plural image data to be stored therein,
The capacity of the data storage unit can be effectively used.

In still another aspect of the present invention, the image processing device may be configured as follows. That is, an image input via a dedicated bus is connected to a data storage unit, which is set corresponding to each of a plurality of image data and includes a plurality of image storage areas in which the corresponding image data is stored, and a dedicated bus. An image synthesized by inputting a plurality of image data read from a plurality of image storage areas and a display storage unit that stores data as display image data corresponding to the image displayed on the screen An image generation unit that generates data and outputs the generated image data to the display storage unit via a dedicated bus.

Therefore, in the above-mentioned image processing apparatus, the image processing unit is provided with the dedicated image generating unit for performing the image processing on the plurality of image data in the plurality of image storage areas, so that the image processing is speeded up. Further, since the image data is transferred from the image processing unit to the display storage unit via the dedicated bus, the display image data can be transferred and stored in the display storage unit at high speed.
As a result, it is possible to quickly display the image on the screen.

The above-described image processing apparatus preferably further includes a processing unit for executing a plurality of types of processing except image processing while transferring data to another via a data bus different from the dedicated bus.

Therefore, in the above-described image processing apparatus, the image processing unit is provided with a dedicated image generation unit for performing image processing on a plurality of image data in a plurality of image storage areas, separately from the processing unit, so that the image processing speed is increased. In addition, since the image data is transferred from the image processing unit to the display storage unit via a dedicated bus different from the data bus to which the processing unit transfers data for executing a plurality of types of processing, The display image data can be transferred to the storage unit for high speed and stored. As a result, it is possible to quickly display the image on the screen. In addition, the processing unit is relieved of the burden of image processing and can execute other types of processing in parallel with the image processing. Since the data bus is not used for the transfer of image data, the traffic of the data bus is reduced accordingly, and a plurality of types of processing can be efficiently executed.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. In the present embodiment, it is mounted on a portable terminal device, for example, a portable telephone and a PDA (Personal digital assistants) capable of displaying an image, and a terminal device that displays a game screen while executing game software. The image synthesizing function performed will be described, but the mounted device is not limited to this. Further, although the number of images to be combined is two, the number is not limited to this and may be three or more.

1 and 2 show a configuration for an image synthesizing function installed in the portable terminal device according to the present embodiment. The configuration of FIG. 2 is an excerpt of the portion of FIG. 1 and 2, the image synthesizing function includes a controller 10 which is a one-chip LSI, a display memory 21 for storing the synthesized image data 3, a controller 22 and a display device controller 1 having a register 23.
1. LC of the image data 3 read from the display memory 21
A display device 12 for displaying on a medium such as D, a RAM 13 which is an external memory of the controller 10, a camera unit 14 for photographing a subject and outputting image data, a ten-key pad, a switch, a button and the like, and various information from the outside. It includes an input unit 15 that is operated to input. The contents of the display memory 21 correspond to the image of the screen displayed by the display device 12.

The controller 10 includes a CPU 101, a built-in memory 102, a control register section 103, and an arithmetic circuit 114.
Image synthesizing circuit 105 and address generating circuit 10
9 and a switch 115. The internal memory 102 is
It has a memory area 106 for storing the foreground data 1, a memory area 107 for storing the background data 2, and a memory area 108. The memory area 108 is the CPU 1
It is used as a memory or work memory in which data for calculation by 01 is stored. The sizes of the memory areas 106 and 107 are variably set according to the sizes of the foreground data 1 and the background data 2 stored therein. Therefore, when the size of the foreground data 1 or the background data 2 is small, the vacant area of the memory area 106 or 107 generated correspondingly is the memory area 10
8, that is, as a work memory for the CPU 101. CPU 101, built-in memory 10
2, the control register 103, the RAM 13, the camera unit 14, and the input unit 15 are connected to each other via a CPU bus 104 indicated by a thick arrow in the figure. CPU bus 104
Is a transmission path for transmitting signals and data between the CPU 101 and each unit. The image synthesis circuit 105 and the display device controller 11 are connected via a dedicated bus 116.

The built-in memory 102 is a single-port memory having only one port (not shown) for inputting / outputting data and the like, and this port is controlled by the switch 115 and the address generating circuit 109 (CPU 101). Side or the image synthesizing circuit 105 side. Specifically, the switch 115 is the CPU 1
When the switching signal SW is input from 01, the port of the built-in memory 102 is switched to one of the above sides based on the input switching signal SW. The circuit whose port is switched can input / output data to / from the built-in memory 102 via the port.

As described above, since the internal memory 102 is a single port memory, the address generation circuit 109 (C
In comparison with a dual port memory in which ports are provided on the PU 101) side and the image synthesizing circuit 105 side,
The mounting area of the built-in memory 102 in the chip can be halved.

The control register unit 103 includes a register 11
0, 111, 112A and 112B. The register 110 has a read start address 6S and an end address 6 for reading the foreground data 1 from the memory area 106.
E is stored. The memory area 107 is stored in the register 111.
Start address 7 for reading background data 2 from
S and the end address 7E are stored. Register 11
Color information 113 is stored in 2A. The color information 113 is information that can be arbitrarily changed according to the display mode of the image to be combined. The color information 113 is information for determining whether or not the image of the background data 2 is transmitted through the image of the foreground data 1 in image combination, and is white with respect to the color of the background data 2 so as to be the glass color. Indicates information such as adding the color of.

The register 112B has a memory area 106.
Foreground data 1 or background data 2 in the memory area 107
Is changed, foreground data 1 and background data 2
Change information UT indicating which of the data has been changed is stored. The initial value of the change information UT indicates that both data have not changed. Registers 110, 111,
The contents of 112A and 112B are set by the CPU 101.

The address generation circuit 109 includes a register 11
An address for reading the foreground data 1 from the memory area 106 is sequentially generated based on the start address 6S and the end address 6E given from 0, and the internal memory 10 is generated.
Give to 2. In parallel with this, the address generation circuit 109
Generates sequentially an address for reading the background data 2 from the memory area 107 based on the start address 7S and the end address 7E given from the register 111, and gives it to the built-in memory 102. Thus, from the memory areas 106 and 107, the foreground data 1 and the background data 2 are sequentially read out in pixel units, for example, by the address designation based on the applied addresses, and are supplied to the image synthesizing circuit 105. Further, at this time, the address generation circuit 109 generates an address TS designating the start address of the area in which the data transferred to the display memory 21 is stored, and the generated address TS and the color given from the register 112A. The information 113 and the information 113 are given to the image synthesis circuit 105. The address TS is the image synthesis circuit 105.
The write start address in the display memory 21 of the data synthesized by is shown. Address TS is start address 6S
It is generated based on Good 7S.

When the image synthesizing circuit 105 is not in the image synthesizing mode, the background data 2 read from the memory area 107 is subjected to a predetermined process and transferred to the display memory 21 via the dedicated bus 116. The data is stored in the display memory 21 as image data 3. Therefore, an image according to the background data 2 is displayed on the screen of the display device 12.

When the image synthesizing circuit 105 is in the image synthesizing mode, calculation is performed based on the foreground data 1 and the background data 2 read from the built-in memory 102 on a pixel-by-pixel basis, and the color information 113 provided from the address generating circuit 109. The circuit 114 performs arithmetic processing for image composition,
The resulting image data DD is sequentially output to the display device controller 11 via the dedicated bus 116. As the arithmetic processing, the foreground data 1 and the background data 2 are compared and the color of the foreground data 1 is preferentially combined, the color of the background data 2 is preferentially combined, and the intermediate between the foreground data 1 and the background data 2 is calculated. This is processing such as combining with colors. When the image synthesis circuit 105 receives the address TS given from the address generation circuit 109, the image synthesis circuit 105 outputs it to the display device controller 11 as it is.

The controller 22 of the controller 11 for the display device, when receiving the given address TS, temporarily stores it in the register 23. The controller 22 determines the write address of the sequentially supplied data DD to the display memory 21 based on the address TS stored in the register 23, and the data DD is displayed by the address designation based on the determined address. Write to. When the writing of the data DD to the display memory 21 is completed and the image data 3 is stored in the display memory 21, the image data 3 is read from the display memory 21 and the screen according to the image data 3 is displayed on the display device 12. Is displayed.

The foreground data 1 and the background data 2 stored in the built-in memory 102 are, for example, R which is an external memory.
It is data prepared in advance in the AM 13, and the CPU 101
Is read from the RAM 13 and stored in the memory areas 106 and 107. Further, the foreground data 1 and the background data 2 may be image data of a subject photographed by the camera unit 14. In that case, the image data output from the camera unit 14 is written by the CPU 101 into the memory areas 106 and 107 via the CPU bus 104, respectively. At this time, in the internal memory 102, memory areas 106 and 107 are set in a size corresponding to the data amounts of the foreground data 1 and the background data 2 according to the display state, the display content, and the image size, as described later,
The foreground data 1 and the background data 2 are written in the set memory areas 106 and 107, respectively. At this time, the start and end addresses of writing the foreground data 1 are specified by the CPU 101 and stored in the register 110 as the start address 6S and the end address 6E, respectively. Similarly, the start and end addresses of the writing of the background data 2 are specified by the CPU 101 and stored in the register 111 as the start address 7S and the end address 7E, respectively. Also, at this time C
The PU 101 has color information 1 according to the display mode at that time.
13 is set in the register 112A. This color information 113
Also, a plurality of types are stored in the RAM 13 in advance, and the CPU 1
01 stores the color information 113 according to the display mode at that time from the RAM 13 in the read register 112A. It is assumed that an initial value is set in the register 112B.

Since the data amounts of the foreground data 1 and the background data 2 change according to the display state, the display contents, the image size, etc., the memory area 10 in the internal memory 102 is changed.
6 and 107 are set to variable sizes according to any one of the display state, the display content and the image size, or a combination thereof. Here, the display state means a size for display on the screen of the display device 12 (vertical and horizontal sizes).
Refers to. Further, the display contents are types of the foreground data 1 and the background data 2 to be combined, for example, image data taken by the camera unit 14, image data stored in the RAM 13 in advance, image data received from the outside by communication (not shown), and the like. Refers to another. The image size refers to the size of the image data 3. As a result of variably setting the sizes of the memory areas 106 and 107, the empty area generated in the internal memory 12 is stored in the memory area 108, that is, the CPU 101.
C is assigned to the work area for calculation for
It is possible to speed up various arithmetic processes via the memory area 108 of the PU 101.

Since the foreground data 1 and the background data 2 are combined by the image combining circuit 105, the CPU 10
No. 1 does not require image synthesis processing, and the load on the CPU 101 is reduced. Further, the CPU 101 and the image synthesis circuit 10
5 and the built-in memory 102 are mounted on the same 1-chip LSI, the built-in memory 1 by the CPU 101
02 and the data read from the built-in memory 12 can be transferred to the image synthesizing circuit 105 at high speed. Further, the data read from the built-in memory 102 is transferred to the image synthesizing circuit 105 and the image synthesizing circuit 1
In order to transfer the image data DD synthesized in 05 to the display device controller 11, a large amount of data must be transferred within a short time.
Since the processing is performed via the dedicated bus 116 or the like instead of via the U bus 104, the traffic related to the CPU bus 104 is significantly reduced. By reducing the load on the CPU 101 and reducing the traffic on the CPU bus 104, the CPU 101 can execute other types of processing including the processing via the CPU bus 104 in parallel with the image combining processing. As a result, the overall processing in the portable terminal device equipped with the image composition function is speeded up.

Image composition will be described with reference to FIGS. 3A and 3B. In FIG. 3A, the memory area 1
Foreground data 1A is stored in 06, and the memory area 107
The background data 2A is stored in.

When the image synthesis is started, the memory area 1
The foreground data 1A and the background data 2A of 06 and 107 are read based on the address output from the address generation circuit 109 and given to the image synthesis circuit 105, while referring to the color information 113 using the arithmetic circuit 114. Is synthesized.

Image combining processing with reference to the color information 113 will now be described. For example, when the transparent mode is set and the color information 113 has a value of “0xxx”, information indicating that pixel data whose first bit is “0” is not displayed in color, that is, is treated as a transparent color. It is set. Here, when the foreground data 1A is combined by being superimposed on the background data 2A, the image of the area excluding the paper plane object PP of the foreground data 1A is treated as a transparent color, and the background data 2A is included in the area. May be transparent. Therefore, the value of the pixel data corresponding to the area of the foreground data 1A is “0xxx”.
Since the image information is set to 1,
Based on 13, the composite image data DD is output while setting the transparent color to the pixel data “0xxxx” of the foreground data 1A.

The combined image data DD is given to the display controller 11 without passing through the CPU bus 104. When the image composition for one screen is completed, the image data 3A is stored in the display memory 21, so that the image of the image data 3A is displayed on the screen of the display device 12. Therefore, the image according to the image data 3A becomes the image around the object PP according to the background data 2A.

After that, when the foreground data 1A or the background data 2A changes, the image synthesizing process is started. Here, it is assumed that only the foreground data 1A is changed to the foreground data 1B as shown in FIG. Foreground data 1A
When the new foreground data 1 is written in the memory area 106 from the camera unit 14, the RAM 1 is changed by the user's instruction through the input unit 15.
3, the new foreground data 1B is read from the memory area 1
When written in 06, the foreground data 1A is stored in the CPU 101.
It is assumed that the data is changed into the foreground data 1B and written in the memory area 106 by the data processing using the polygon according to the above.

When the foreground data 1B is written in the memory area 106 as described above, the CPU 101 sets the start address 6S and the end address 6E corresponding to the size of the foreground data 1B in the register 110 in the same manner as described above. At the same time, the change information UT in the register 112B is updated. As a result, the change information UT indicates that only the foreground data 1A has been updated.

The address generation circuit 109 includes a register 1
The contents of 10, 111, 112A and 112B are given. The address generation circuit 109 detects that only the foreground data 1A has been updated based on the change information UT in the register 112B. The foreground data 1B is read from the memory area 106 and the partial data 36 is read from the memory area 107 based on the address generated by the address generation circuit 109 according to the contents of the register 110. Specifically, when the address generation circuit 109 detects that only the foreground data 1A has been updated based on the change information UT,
Since the address for reading only the partial data 36 from the memory area 107 is generated based on the contents of the register 110 and the register 111, only the partial data 36 is read from the memory area 107 by addressing based on the generated address. To be done. The partial data 36 is image data corresponding to a portion of the image of the background data 2A on which the image of the foreground data 1B is superimposed. Therefore, the image synthesizing circuit 105 performs the image synthesizing process on the read foreground data 1B and the partial data 36 with reference to the color information 112A. The combined image data DD corresponds to an image in which the image of the foreground data 1B is superimposed on the image of the partial data 36. Further, the address generation circuit 109 updates the address TS so as to indicate the head address of the area corresponding to the partial data 36 of the display memory 21, and outputs it to the display device controller 11 via the image synthesis circuit 105.

The image data DD is written in the display memory 21 after the address corresponding to the address TS without passing through the CPU bus 104. As a result, only the data of the portion corresponding to the partial data 36 of the previous image data 3A stored in the display memory 21 is updated, and the image data 3B is updated.
Is obtained. The image data 3B is read from the display memory 21, and the image according to the image data 3B is displayed on the display device 12.

As described above, when the background data 2A does not change at all and only the foreground data 1A changes like the foreground data 1B, the process of combining the partial data 36 and the foreground data 1B ends. Further, the data update in the built-in memory 102 only needs the foreground data 1A. Further, the rewriting of the image data 3 in the display memory 21 is performed by the partial data 36.
It is only necessary to rewrite the data corresponding to. Due to these characteristics, it is possible to perform image combining processing and display while updating the combined image at high speed.

When the change information UT indicates that the foreground data 1 and the background data 2 are changing, FIG.
The combining process as described in (A) is performed.

An image synthesizing processing procedure according to this embodiment will be described with reference to the flowchart of FIG. In the flowchart of FIG. 4, the processing depending on the CPU 101 (S1 to S7)
And processing (S10 to S16) that does not depend on the CPU 101 are shown.

First, when the user operates the input unit 15 to instruct image composition, the CPU 101 starts image composition processing (S1). The CPU 101 is the RAM as described above.
The foreground data 1 and the background data 2 are selected from the data stored in 13 and the image data output from the camera unit 14, and the selected data are stored in the CPU bus 1
The data is stored in the memory areas 106 and 107 via 04 respectively. At this time, the CPU 101 specifies the sizes of the stored foreground data 1 and background data 2 (the vertical and horizontal sizes of the corresponding image), and the start address 6 in the registers 110 and 111 based on the specified size.
S and 7S and end addresses 6E and 7E are set (S2-S4). Then, memory areas 106 and 1
The image data is stored in 07 (S5). It is assumed that the color information 113 is preset according to the display mode, and the change information UT is also preset to the initial value.

Next, since the CPU 101 outputs the switching signal SW, the switch 115 switches the port of the internal memory 102 to the address generating circuit 109 (C) based on the switching signal SW.
The PU 101) side is switched to the image synthesizing circuit 105 side (S6). When the switching is completed, the CPU 101 outputs an image combining command to the control register unit 103 (S7).

The control register unit 103 includes a register 11
Since the contents set in 0, 111, 112A and 112B are given to the address generation circuit 109, the address generation circuit 109 outputs the foreground data 1 and the background data 2 from the memory areas 106 and 107 based on the given contents. Addresses for reading are sequentially generated and given to the built-in memory 102. In the internal memory 102, the memory areas 106 and 10 are generated based on the given address.
The data read from 7 is sequentially output to the image synthesizing circuit 105. At this time, the address generation circuit 109
The color information 113 and the address TS based on the contents given from the control register unit 103 are given to the image synthesizing circuit 105 (S10 to S12). The image synthesizing circuit 105 performs an image synthesizing process based on the supplied image data and color information 113, and outputs the synthesized image data DD and the address TS to the display device controller 11. In the display memory 21, image data DD is sequentially written in an area having an address corresponding to the address TS as a head (S14).

The image synthesizing circuit 105 has a memory area 106.
When it is determined that the reading of the foreground data 1 is completed (Yes in S15), the image composition circuit 105 notifies the display device controller 11 of the end of image composition (S1).
6). At this time, the image data 3 is stored in the display memory 21 of the display device controller 11. The controller 22 uses the image data 3 of the display memory 21.
Is read out and given to the display device 12, an image according to the image data 3 is displayed on the display device 12.

After that, when it is detected that the foreground data 1 has been updated, the processing from S1 onward in FIG. 4 is repeated again. At this time, since only the foreground data 1 is changed, the image synthesizing process is executed at high speed as described with reference to FIG.

Here, when the foreground data 1 is image data such as the foreground data 1A and 1B of FIGS. 3A and 3B, the image according to the background data 2A passes through the images of the foreground data 1A and 1B. A region that is transparently displayed is present in the foreground data 1A and 1B. In such a case, since the data corresponding to the transparent areas of the foreground data 1A and 1B can be interpolated with the data of the background data 2A, the foreground data 1A and 1B may be stored in the memory area 106 in a compressed state. By doing so, the capacity required for the memory area 106 can be reduced.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0071]

As described above, since a dedicated image generation unit for performing image processing on a plurality of image data in a plurality of image storage areas is provided,
Image processing is speeded up. Further, since the image data is transferred from the image processing unit to the display storage unit via the dedicated bus, the display image data can be transferred and stored in the display storage unit at high speed. As a result, it is possible to quickly display the image on the screen. Further, since the sizes of the plurality of image storage areas are variably set according to the amounts of the plurality of image data, the data storage unit can be effectively used.

[Brief description of drawings]

FIG. 1 is a configuration diagram for an image synthesizing function installed in a portable terminal device according to the present embodiment.

FIG. 2 is a configuration diagram for an image synthesizing function installed in the portable terminal device according to the present embodiment.

FIG. 3A and FIG. 3B are diagrams for explaining the image synthesizing procedure according to the present embodiment.

FIG. 4 is a flowchart of a processing procedure of image combination according to the present embodiment.

FIG. 5 is a configuration diagram for a conventional image combining function in a portable terminal device.

FIG. 6 is a configuration diagram for a conventional image synthesizing function in a portable terminal device.

7A and 7B are diagrams showing an image synthesizing procedure by the image synthesizing function of FIGS. 5 and 6.

FIG. 8 is a flowchart showing a conventional procedure for image synthesis.

[Explanation of symbols]

1,30 Foreground data, 2,40 Background data, 3,5
0 image data, 10,500 controller, 11,
51 display device controller, 12, 52 display device,
101, 501 CPU, 103, 503 Control register section, 102, 502 Built-in memory, 104, 504
CPU bus, 109, 505 address generation circuit, 10
5 Image synthesis circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G06T 1/20 G06T 1/20 A 3/00 300 3/00 300 (72) Inventor Takashi Yasumoto Osaka 22-22 Nagaike-cho, Abeno-ku, Osaka F-Term in SHARP Co., Ltd. (reference) 5B057 CE08 CH01 CH11 CH14 CH20 DA16 5B061 BA03 DD09 DD12 GG05 5B069 LA02 5B077 AA18 DD02 DD11 DD23 5C076 AA12 AA19 BA04 BA06

Claims (9)

[Claims] 1. A data storage unit, which is set corresponding to each of a plurality of image data and includes a plurality of image storage areas in which the corresponding image data is stored, and a dedicated bus are connected to each other via the dedicated bus. The image data input by inputting the input image data as display image data corresponding to the image displayed on the screen, and the plurality of image data read from the plurality of image storage areas, and image processing An image generation unit that generates combined image data by outputting the generated image data to the display storage unit via the dedicated bus, and data via the data bus different from the dedicated bus from other data. An image processing apparatus, comprising: a processing unit that executes a plurality of types of processing other than the image processing while transferring. 2. The image processing apparatus according to claim 1, wherein the sizes of the plurality of image storage areas in the data storage unit are variably set according to the amounts of the plurality of image data. 3. The image processing apparatus according to claim 2, wherein the image data amount is determined in correspondence with a size for displaying the screen. 4. The image data amount is determined according to the types of the plurality of image data to be combined.
Alternatively, the image processing device according to item 3. 5. The image processing apparatus according to claim 2, wherein the image data amount is determined in correspondence with the size of the display image data. 6. The plurality of types of processing executed by the processing unit receives image data supplied from the plurality of image data, and writes the received image data in the corresponding image storage area. And a data writing process for inserting the image data, and when one or more image data of the plurality of image data are changed, the one or more changed image data is supplied to the data writing process. Claims 1 to 5
The image processing device according to any one of 1. 7. A partial image of an image displayed on the screen, which is synthesized by using the changed image data, when one or more image data of the plurality of image data in the plurality of image storage areas is changed. Further comprising an image data reading unit that reads out image data of a portion of the plurality of image data for combining from the plurality of image storage areas, and the display storage unit stores the stored display image data. The image processing device according to claim 1, wherein data corresponding to the partial image is updated using image data input via the dedicated bus. 8. The data storage unit further includes a processing storage area to which the data bus is connected and which stores data accessed for the plurality of types of processing executed by the processing unit. Any one of claims 1 to 7
The image processing device according to item. 9. A data storage unit, which is set corresponding to each of a plurality of image data and includes a plurality of image storage areas in which the corresponding image data is stored, and a dedicated bus for the image data are connected. A display storage unit that stores image data input via the dedicated bus as display image data corresponding to an image displayed on the screen, and the plurality of image data read from the plurality of image storage areas are input. An image generation unit that generates combined image data by performing image processing and outputs the generated image data to the display storage unit via the dedicated bus. The size of the image storage area is variably set according to the amount of the plurality of image data.