JP4862470B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that captures video signals in the NTSC format, PAL format, etc. in real time, and superimposes them on an OSD image or the like to supply to a display device or the like.

2. Description of the Related Art In recent years, there has been a device that captures video signals of NTSC format, PAL format, etc., captured by a video camera or transmitted by broadcast as image data (video capture), and displays it on a display screen by expanding or reducing in real time Has been developed. In such an apparatus, an OSD image composed of characters, graphics, and the like is superimposed on the captured image data and supplied to a display device. This type of apparatus has a plurality of hardware image data processing circuits (display planes), and each display plane converts captured image data, image data created by a CPU, back image data, and the like into display data. Are displayed according to the priority order.
JP 2005-257886 A JP 2004-147285 A JP 2005-215252 A

By the way, the conventional image display apparatus is designed so that one display plane generates and displays image data of one rectangular area, and when generating and displaying image data of a plurality of rectangular areas, a plurality of image data are displayed. Each rectangular area image data is generated using the display plane.
Therefore, in order to increase the displayable rectangular area image data, it is necessary to increase the number of display planes accordingly.
The “display plane” is hardware necessary for displaying one rectangular area on the display device, and adding a display plane leads to an increase in size, complexity, and cost of the device.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image capable of displaying a plurality of rectangular area image data on a single display plane by adding a slight configuration to a conventional display plane. It is to provide a processing apparatus.

  The present invention has been made to solve the above-described problems. The invention according to claim 1 supplies a synchronization signal to an external display device, and images are displayed on the external display device at a timing synchronized with the synchronization signal. A display controller that generates a timing signal for supplying data, a plurality of display planes that each process image data of a predetermined rectangular area in the image memory based on the timing signal output from the display controller, In the image processing apparatus comprising: a combining unit configured to combine each rectangular image data processed by a plurality of display planes according to a predetermined rule and to supply to the external display device, each display plane has a plurality of rectangular shapes A plurality of sets of display instruction data supplied from the outside in order to display an image, each set being an address of the image memory An instruction data memory in which a plurality of sets of display instruction data including a display position and an enlargement / reduction magnification are stored, and an enlargement / reduction that reads out image data from the image memory based on a timing signal supplied from the display controller and performs enlargement / reduction A reduction circuit, and a first-in first-out buffer memory in which image data output from the enlargement / reduction circuit is written and the written data is supplied to the synthesis unit based on a timing signal supplied from the display controller The display controller generates a timing signal corresponding to each of the plurality of sets of display instruction data of each display plane, and supplies the timing signal to the enlargement / reduction circuit and the buffer memory. An image processing apparatus.

  According to a second aspect of the present invention, in the image processing device according to the first aspect, when the rectangular image data to be displayed is on the next display line of the external display device, the display controller A timing signal for instructing generation of image data to be displayed on the next display line is generated and supplied to the enlargement / reduction circuit. The enlargement / reduction circuit receives the timing signal and the display instruction data. Based on this, image data to be displayed on the next display line is generated and supplied to the buffer memory.

According to a third aspect of the present invention, in the image processing device according to the second aspect, the display controller reads out when the rectangular image data to be displayed is on the next dot of the external display device. A timing signal to be instructed is generated and supplied to the buffer memory, and the buffer memory reads out image data to be displayed with the next dot based on the timing signal and supplies it to the combining unit. It is characterized by.
According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, each display plane is provided to the instruction data memory, and a plurality of sets for instructing display of a plurality of rectangular images. Data relating to the display position of the instruction data is compared, and image data corresponding to a plurality of rectangular images is generated only when a plurality of rectangular images are not applied to the same display line.

  According to the present invention, the instruction data memory for controlling each display plane is configured to store a plurality of sets of display instruction data, and the display controller generates a timing signal corresponding to each of the plurality of sets of display instruction data. Thus, there is an effect that a plurality of rectangular area image data can be displayed on one display plane.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram showing the configuration of a VDP (Video Display Processor) according to an embodiment of the present invention. In FIG. 1, VDP 1 captures an image input, writes it in the video memory 3, and displays it on a CRT display device (not shown) in accordance with the display resolution. The VDP 1 has a function of inputting a drawing command from a CPU (Central Processing Unit) 2 and performing OSD (On Screen Display) display for video input.

  In this embodiment, three types of drawing commands are used: a LINE command, a FILL command, and a COPY command. The LINE command is a command for drawing a straight line by designating a start point and an end point, and the FILL command is a command for painting by designating a rectangular area. The COPY command is a command for designating a transfer source address and a transfer destination address to copy data in the video memory space. Further, the COPY command includes information for designating format conversion and setting information for transparent color control and α blending.

  The CPU interface module 101 in the VDP 1 manages communication with the CPU 2 and has a function of outputting a drawing command input from the CPU 2 to the DPU 106 and a function of controlling access from the CPU 2 to the video memory 3. The VRAM interface module 102 controls access to the video memory 3 from each part in the VDP 1.

  A VDU (Video Decoder Unit) 103 receives an analog image signal and converts it into a digital image signal. A VCC (Video Capture Controller) 104 captures a digital image signal output from the VDU 103 or a digital image signal directly input from the outside, and writes it into the video memory 3 as image data. Note that each of the decoder circuit of the VDU 103 and the capture circuit of the VCC 104 is provided with two circuits, and two-channel analog image signal inputs can be captured simultaneously.

  A CPC (Capture Plane Controller) 105 reads image data from the video memory 3 and outputs it to the PDC 108. A DPU (Drawing Processor Unit) 106 interprets a drawing command input from the CPU interface module 101, draws a straight line or a rectangle in the video memory 3, and performs predetermined processing on the drawn data. The CPU 2 can also draw directly in the video memory 3 without using a drawing command.

  The OSD plane controller 107 reads data to be displayed as an OSD image from the video memory 8 and outputs it to the PDC 108. A PDC (Pixel Data Controller) 108 displays an image input, that is, an image based on an externally input digital image signal and an image based on the digital image signal decoded by the VDU 103, respectively, as they are on the backdrop surface. Also, the captured image data output from the CPC 105 and the data to be displayed as the OSD image output from the OSD plane controller 107 are input, the format of each plane is unified, and the display priority order and α blending settings are set. The composition process is performed.

  In the VDP 1, a hierarchical display by four backplanes and a backdrop plane for displaying an image input from the outside, two display planes for displaying captured image data, and two display planes for displaying OSD images. The PDC 108 performs synthesis processing of the four display planes and the backdrop surface.

  Note that the term “display plane” indicates that all the configurations necessary for displaying one rectangular image data in a predetermined size on a predetermined location of the external display device are included, or the external display device. The display data itself supplied is shown.

  The PDC 108 outputs the combined display data as it is as a digital image signal, and also outputs it as an analog image signal via a DAC (Digital Analog Converter) 109. The CRT controller 110 outputs a timing signal for display on the CRT display device, and outputs information related to the monitor display to each part in the VDP 1. The clock generator 111 generates a clock used in each part in the VDP 1.

  FIG. 2 is a block diagram showing details of the CPC 105 in FIG. 1, and this CPC 105 is composed of two display planes 105a and 105b having the same configuration. In the display plane 105a, reference numeral 12 denotes an enlargement / reduction circuit. When a timing signal indicating a generation request for image data to be displayed on the next line is given from the CRT controller 110, the VRAM interface module 102 is sent from the video memory 3. The image data captured by the VCC 104 is read out, enlarged or reduced, and written into the line buffer 13a or 13b. The line buffers 13a and 13b are first-in first-out buffer memories in which writing and reading are alternately performed. When the output of the enlargement / reduction circuit 12 is written in the line buffer 13a, the data in the line buffer 13b is read out. When the output of the enlargement / reduction circuit 12 is written in the line buffer 13b, the data in the line buffer 13a is read and this operation is performed alternately. The writing to the line buffers 13 a and 13 b is performed in conjunction with the output of the enlargement / reduction circuit 12, but the reading is performed based on a timing signal supplied from the CRT controller 110. A controller 15 controls each part of the circuit based on data in the memory 16.

  Next, the enlargement / reduction circuit 12 will be described in detail. The enlargement / reduction circuit 12 is a conventionally known circuit, and a bilinear filter circuit, a nearest neighbor circuit, or the like is used. The bilinear filter circuit will be described below.

In FIG. 3, reference numeral 41 denotes image data written in the video memory 3, 42 denotes a window for designating image data to be enlarged on the display device 4, 43 denotes a display screen of the CRT display device, and 44 denotes an enlarged display. It is assumed that the window displays an image. At this time, the bilinear filter circuit converts the color data of a certain dot Xa in the window 44 into a point X in the window 42 corresponding to the dot Xa (this point X may or may not coincide with the dot in the window 42). It is obtained from the color data of the four dots around. That is, in FIG. 4, the four dots around the point X are D1 to D4, the horizontal distance between the point X and the point D1 is a, the horizontal distance between the point X and the point D2 is b, the point When the vertical distance between X and the point D1 is c, and the vertical distance between the point X and the point D3 is d, the color data of the point X is obtained by the following equation.
Color data of point Y1: (dD1 / (c + d)) + (cD3 / (c + d))
Color data of point Y2: (dD2 / (c + d)) + (cD4 / (c + d))
Color data of point X: (bY1 / (a + b)) + (aY2 / (a + b))

  In the case of the nearest neighbor circuit, the color data of the closest dot among the four points D1 to D4 is the color data of the dot Xa.

Next, the operation of the display plane 105a described above will be described.
Now, the color data of each dot in the window 42 preset in the image data 41 shown in FIG. 3 is enlarged and displayed on the window 44 of the display screen 43, and the color data of each dot in the window 46 is reduced. It is assumed that the data is displayed on the window 47 of the display screen 43.
In this case, the CPU 2 gives the following data to the controller 15 of the display plane 105a.
a1 = Storage position of the upper left corner dot of the window 42 before enlargement in the image memory 11 b1 = Display position of the upper left corner dot of the window 44 after enlargement on the display screen 43 c1 = Horizontal dot of the window 44 after enlargement Number d1 = Number of dots in the vertical direction of the window 44 after enlargement e1 = Enlargement / reduction ratio a2 = Storage position of the upper left corner dot of the window 46 before enlargement in the image memory 11 b2 = Dot of the upper left corner of the window 47 after enlargement C2 = number of dots in the horizontal direction of the enlarged window 47 d2 = number of dots in the vertical direction of the enlarged window 47 e2 = magnification / reduction magnification Note that the enlargement ratio in the vertical direction and the enlargement in the horizontal direction If the rates are different, separate magnifications are input to the controller 15 in the vertical and horizontal directions.

  The controller 15 receives these data and writes them in the memory 16. Further, the CRT controller 110 reads the data b1, c1, d1 and b2, c2, d2 described above from the memory 16 and temporarily stores them in the internal memory.

  Thereafter, the CRT controller 110 detects the data processing start timing of the window 44 in the display plane 105a based on the data b1, c1, and d1, and outputs a trigger signal for the window 44 to the controller 15, and the data b2, c2, Based on d 2, the data processing start timing of the window 47 is detected and a trigger signal for the window 47 is output to the controller 15. Here, the data processing start timing of the display plane 105a is not the time when the CRT display device starts displaying the first row of the window 44, but the timing considering the time when the display plane 105a prepares display data. is there.

  When the controller 15 receives a trigger signal for starting data processing on the first line of the window 44 from the CRT controller 110, the controller 15 outputs a data processing start command to the enlargement / reduction circuit 12. The enlargement / reduction circuit 12 receives this command, and reads out the data of the first and second lines of the window 42 of the video memory 3 based on the data a1. Next, the color data of each dot of the first line of the window 44 is obtained based on the read data, and written to the line buffer 13a according to the clock pulse. Thereafter, the enlargement / reduction circuit 12 performs the third line, the fourth line of the window 42 from the video memory 3 based on the data processing start command generated by the controller 15 in conjunction with the trigger signal of each row from the CRT controller 110. .., Sequentially read out the color data of each dot, and sequentially calculate the color data of the second, third,... Lines of the window 44 based on these color data, and alternately write them in the line buffers 13a and 13b.

Further, the controller 15 outputs a clock pulse for data output to the line buffer 13a at the display timing of the first line of the window 44. As a result, the data in the line buffer 13a is sequentially supplied to the display device 4 via the PDC 108 according to the clock pulse, and the first line of the window 44 is displayed. Next, the controller 15 outputs a clock pulse to the line buffer 13b at the display timing of the second line of the window 44, whereby the second line of the window 44 is displayed, and thereafter the same processing is repeated.
Then, the controller 15 stops the output instruction to the line buffers 13a and 13b when the display of the bottom line of the window 44 is finished, and enters a standby state.

  Next, when a trigger signal for starting data processing in the first row of the window 47 is output from the CRT controller 110 to the controller 15, the same processing as described above is performed, whereby the window 47 is displayed. . Thereafter, the above processing is repeated each time the trigger signal for window 44 and the trigger signal for window 47 are output from the CRT controller 110.

  As described above, in the above-described embodiment, functions as two display planes are achieved by adding a few configurations to one display plane 105a, b and CRT controller 110. This can be said to be very efficient since another display (display of window 47) is performed using the free time in the display plane (free time after finishing the display processing of window 44).

  When a plurality of windows are displayed using one display plane, as shown in FIG. 5, when two windows of the display screen 43 overlap or are arranged in the scanning line direction, the conventional display plane is greatly increased. Design changes are required. In the embodiment described above, the addition of a slight configuration of one display plane 105a, b and CRT controller 110 and the use of the free time in the display plane are performed, so that the display plane extension effect can be obtained at a very low cost. . Therefore, in order to cope with this, it is desirable to compare the data related to the display positions of the two windows and generate the image data only when the two windows do not cover the same display line.

  The present invention is used in a display device or the like that displays NTSC format or PAL format image data captured by a video camera in real time.

1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a block diagram which shows the structure of CPC105 in the embodiment. 6 is an explanatory diagram for explaining an operation of the CPC 105. FIG. 6 is a diagram for explaining the operation of an enlargement / reduction circuit 12 in the CPC 105. FIG. It is a figure for demonstrating the case which cannot be processed in the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 2 ... CPU, 3 ... Video memory, 12 ... Enlarging / reducing circuit, 13a, 13b ... Line buffer, 15 ... Controller (display controller), 16 ... Memory, 102 ... VRAM interface, 110 ... CRT controller (Display controller).

Claims (4)

A display controller that supplies a synchronization signal to the external display device and generates a timing signal for supplying image data to the external display device at a timing synchronized with the synchronization signal, and a timing at which each is output from the display controller A plurality of display planes for processing image data of a predetermined rectangular area in the image memory based on the signal and the respective rectangular image data processed by the plurality of display planes are synthesized according to a predetermined rule and the external display An image processing apparatus including a combining unit that supplies the apparatus;
Each display plane is
A plurality of sets of display instruction data supplied from the outside in order to display a plurality of rectangular images, each set including a plurality of sets including an address of the image memory, a display position on the display screen, and an enlargement / reduction ratio An instruction data memory for storing display instruction data;
An enlargement / reduction circuit that reads out image data from the image memory based on a timing signal supplied from the display controller and performs enlargement / reduction;
The image data output from the enlargement / reduction circuit is written, and is configured with a first-in first-out buffer memory that supplies the written data to the synthesis unit based on a timing signal supplied from the display controller.
The display controller is
An image processing apparatus, comprising: generating a timing signal corresponding to each of the plurality of sets of display instruction data of each display plane, and supplying the timing signal to the enlargement / reduction circuit and the buffer memory. The display controller generates a timing signal instructing generation of image data to be displayed on the next display line when rectangular image data to be displayed is on the next display line of the external display device. To supply to the enlargement / reduction circuit,
2. The enlargement / reduction circuit generates image data to be displayed on a next display line based on the timing signal and the display instruction data and supplies the image data to the buffer memory. The image processing apparatus described. The display controller generates a timing signal instructing reading when the rectangular image data to be displayed is on the next dot of the external display device, and supplies the timing signal to the buffer memory.
The image processing apparatus according to claim 2, wherein the buffer memory reads out image data to be displayed with the next dot based on the timing signal and supplies the read image data to the combining unit. Each display plane is
Compared with data related to the display position of a plurality of sets of display instruction data for instructing display of a plurality of rectangular images given to the instruction data memory, and only when a plurality of rectangular images are not applied to the same display line. The image processing apparatus according to claim 3, wherein image data corresponding to a plurality of rectangular images is generated.

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