JP5140942B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method for outputting a display video at a different period from a captured video.

  As an image scanning method, there are known an interlace method in which scanning is performed by dividing every other scanning line constituting the screen into two fields, and a progressive method in which all scanning lines are scanned at once. Also in the same interlace system, images with different display periods are used, such as the NTSC (National Television Standards Committee) format with a field period of 60 Hz and the PAL (Phase Alternation by Line) system with a field period of 50 Hz. .

Conventional image processing apparatuses are known that have a function of converting to video having a different scanning method and display cycle. However, if the video capture cycle differs from the video display cycle, the video memory Writing to and reading from are performed at independent timings.
JP 2004-147285 A

For this reason, in the conventional image processing apparatus, while image data of one frame or one field is being read from the video memory, the phenomenon that the captured image data is written to the video memory occurs, and at different times. Tiering occurs in which captured image data is mixed on the same display screen.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus capable of outputting a display video at a different period from a captured video without causing tearing.

The present invention has been made to solve the above problems, and an image processing apparatus according to the present invention captures input digital video data and stores the captured image data in three or more image storages in a first period. The image writing means for sequentially writing the three or more image storage areas with respect to the area, and the three or more image storage areas from the three or more image storage areas and sequentially rotating in the second cycle Image reading means for reading image data, and the three or more image storage areas to be written next by the image writing means when the image writing means finishes writing to one of the three or more image storage areas And determining means for determining whether the image reading means is reading data, and the determining means determines that the image storage area is being read by the image reading means. The case, the image writing means, said stops capturing digital image data, not the writing of image data into the image storage area in the first cycle of the following, an image processing apparatus.

In the image processing apparatus, the determination unit may further determine that the image storage unit to be read next by the image reading unit is read by the image writing unit when the image reading unit finishes reading from the image storage region. determines whether data is being written, in the case where the image storage area to read said image reading means and then said judging means to be in writing is determined by the image writing means, said image reading unit, the following in the second period of the, to read out again the image data from the image storage area is read immediately before.

In the image processing device, the image writing means captures the input interlaced video data in units of frames and writes it in the image storage area, so that each field is separately stored in the image storage area. It is possible to select whether to store in each area or to alternately store each line in one area in the image storage area.

The image processing method according to the present invention captures input digital video data, and circulates the image data captured in the first cycle through the three or more image storage areas with respect to the three or more image storage areas. An image writing procedure for sequentially writing, an image reading procedure for sequentially reading out the image data in a second cycle through the three or more image storage regions from the three or more image storage regions, and the image writing procedure When writing to one of the three or more image storage areas is finished, whether another one of the three or more image storage areas to be written next in the image writing procedure is being read out by the image reading procedure. ; and a determination procedure, when the image storage area is determined by the determining step to be in reading by the image reading procedure, the image writing step, the digital image data Stops capture, no writing of image data into the image storage area in the first cycle of the following, an image processing method.

In the image processing method, the determination procedure may further include the step of reading the image storage area to be read out next in the image reading procedure when the reading from the image storage area is completed in the image reading procedure. If it is determined by the procedure that writing is in progress and the determination procedure determines that the image storage area to be read next in the image reading procedure is in writing by the image writing procedure, the image reading procedure is in the next second period, to read out again the image data from the image storage area is read immediately before.

  According to the present invention, the image data captured in three or more image storage areas is sequentially written by the image writing means, and the image data is sequentially read by the image reading means, and the writing process by the image writing means is the reading process by the image reading means. In the case of catching up with the image, the capture is stopped for one cycle. Conversely, when the reading process by the image reading unit catches up with the writing process by the image writing unit, the same storage area is continuously read out. During the reading process from the image storage area, the image writing means does not write to the image storage area, and tearing can be prevented.

  In addition, as a storage method for the image storage area, either a method for storing each field in a different area or a method for alternately storing each line in one area can be selected. You can choose the right method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram showing the configuration of a VDP (Video Display Processor) according to an embodiment of the present invention. In FIG. 1, a VDP 1 captures a video input signal, writes it as image data in a video memory 3, and displays it on a monitor (not shown) in accordance with the display resolution. The VDP 1 has a function of inputting a drawing command from a CPU (Central Processing Unit) 2 and performing OSD (On Screen Display) display for video input.

  As drawing commands, for example, there are a LINE command, a FILL command, and a COPY command. The LINE command is a command for drawing a straight line by designating a start point and an end point, and the FILL command is a command for painting by designating a rectangular area. The COPY command is a command for designating a transfer source address and a transfer destination address to copy data in the video memory space. Further, the COPY command includes information for designating format conversion and setting information for transparent color control and α blending. However, the drawing command is not limited to these.

  In the present embodiment, the VDP 1 secures three storage areas (hereinafter referred to as a triple buffer) in the video memory 3 and stores captured image data. The VDP 1 sequentially writes the captured image data to each of the triple buffers, and then the CPC 105 sequentially reads from the triple buffer in accordance with the display timing.

  The CPU interface module 101 in the VDP 1 manages communication with the CPU 2 and has a function of outputting a drawing command input from the CPU 2 to the DPU 106 and a function of controlling access from the CPU 2 to the video memory 3. The VRAM interface module 102 controls access to the video memory 3 from each unit in the VDP 1.

  A VDU (Video Decoder Unit) 103 receives an analog video signal and converts it into digital video data. A VCC (Video Capture Controller) 104 captures digital video data output from the VDC 103 or video data input directly from outside as digital data, and writes the captured video data into the video memory 3 (image writing means). . Note that each of the decoder circuit of the VDC 102 and the capture circuit of the VCC 104 includes two circuits, and can capture two-channel video inputs simultaneously.

  A CPC (Capture Plane Controller) 105 reads image data from the video memory 3 (image reading means) and outputs it to the PDC 108. A DPU (Drawing Processor Unit) 106 interprets a drawing command input from the CPU interface module 101, draws a straight line or a rectangle in the video memory 3, and performs predetermined processing on the drawn data. The CPU 2 can also draw directly in the video memory 3 without using a drawing command.

  The OSD plane controller 107 reads out data to be displayed as an OSD image from the video memory 3 and outputs it to the PDC 108. A PDC (Pixel Data Controller) 108 inputs an externally input digital video, a digital video decoded by the VDU 103, a captured video output from the CPC 105, and an OSD image output from the OSD plane controller 107. The format of each plane is unified, and the composition processing is performed based on the display priority order and α blending setting.

  Note that the term “display plane” indicates that all the configurations necessary for displaying one rectangular display data in a predetermined size on a predetermined location of the external display device are included, and the external display device. The display data itself supplied to is also shown.

  In VDP1, hierarchical display is possible with a backdrop surface for displaying externally input video, two display planes for displaying captured video, and two display planes for displaying OSD images. The display plane and the backdrop surface are combined.

  The PDC 108 outputs the synthesized digital image to the outside as it is, and simultaneously outputs an analog video signal via a DAC (Digital-to-Analog Converter) 109. The CRT controller 110 outputs a timing signal for display on the monitor, and outputs information related to the monitor display to each part in the VDP 1. The clock generator 111 generates a clock used in each part in the VDP 1.

Next, the operation of the above-described embodiment will be described with reference to FIGS.
FIG. 2 is a diagram showing the correspondence between the capture and display modes in VDP 1 and the triple buffer increment, FIG. 3 is a diagram showing the function of each drawing mode shown in FIG. 2, and FIG. FIG. 6 is a diagram showing a storage area of captured image data in the video memory 3 in each mode shown in FIG.

  In FIG. 2, when the VCC 104 captures in the progressive mode, the drawing mode C * DM [1: 0] is not designated. At this time, as shown in FIG. 4A, in the video memory 3, one frame of captured image data is stored in one of the triple buffers.

  In FIG. 4A, only one video memory area is displayed as a triple buffer, but in reality there are three video memory areas with different address spaces (ie, drawing areas) in the video memory 3. To do. The same applies to FIGS. 4B to 4D.

  When the VCC 104 captures in the progressive format and the CPC 105 performs the display in the progressive format (setting 1 in FIG. 2), the CPC 105 increments the display frame unit and sets the address of the triple buffer for reading the image data from the video memory 3 Switch.

  When the VCC 104 captures in the progressive mode and the CPC 105 displays in the interlace mode (setting 2 in FIG. 2), the CPC 105 increments the display field unit and reads the image data from the video memory 3 Switch.

  On the other hand, when the VCC 104 captures by the interlace method, three types of drawing modes C * DM [1: 0] are selected according to the storage method in the video memory. When C * DM [1: 0] = 2'b0 * is selected as the drawing mode, the VCC 104 captures in units of fields, and as shown in FIG. 4B, the image data of the 1st field and the image of the 2nd field Data is stored in the same area in the video memory 3.

  When C * DM [1: 0] = 2'b10 is selected as the drawing mode, the VCC 104 captures in units of frames, and as shown in FIG. 4C, image data of the 1st field and image data of the 2nd field. Are stored in another area in the video memory 3.

  When C * DM [1: 0] = 2'b11 is selected as the drawing mode, the VCC 104 captures in units of frames, and as shown in FIG. 4D, the image data of the 1st field and the image data of the 2nd field Are alternately stored in the area in the video memory 3 for each line.

  In VDP 1, which setting shown in FIG. 2 is used is designated by inputting a command from CPU 2, and VCC 104 captures image data according to the designated setting. Further, the VCC 104 receives timing information related to the cycle of the display video from the CRT controller 110, and manages the timing for performing capture and the timing for performing display.

  On the other hand, the CPC 105 inputs an instruction as to which image buffer the image data is read from the VCC 104 and reads the image data according to the setting designated by the CPU 2.

Next, processing when the VCC 104 writes the captured image data in the triple buffer in the video memory 3 will be described with reference to the flowchart of FIG.
In the following, the three drawing areas (image storage areas) constituting the triple buffer are referred to as a drawing area_0, a drawing area_1, and a drawing area_2, and the VCC 104 is a drawing area_0, a drawing area_1, a drawing area_2, a drawing area_0,. In this order, the captured image data is written sequentially into the three drawing areas.

In this embodiment, using the variable n, the drawing area_0, the drawing area_1, and the drawing area_2 are represented as “drawing area_n”. Here, the variable n takes any value of 0, 1, and 2. By incrementing the variable n in the process of accessing each drawing area described later, the value of n becomes 0, 1, 2, 0. , 1, 2,... Therefore, for convenience of explanation, it is defined that n + 1 represents 0 when n = 2, and n−1 represents 2 when n = 0. That is, in the above-described number-of-times value sequence, when the variable n is incremented when n = 2, the variable n becomes 0, and when the variable n is decremented when n = 0, the variable n becomes 2.
In the present embodiment, the three drawing areas_0, the drawing area_1, and the drawing area_2 are taken as examples. However, the present invention is not limited to this, and the number of drawing areas may be increased as necessary. In that case, the number of buffers in the video memory 3 may be increased in accordance with the number of drawing areas.

  When the VCC 104 writes image data to the triple buffer in the video memory 3, that is, when image data is written to the drawing area_n (arbitrary one of the drawing area_0, the drawing area_1, and the drawing area_2) of the triple buffer, In FIG. 5, the VCC 104 determines whether or not the CPC 105 is reading the drawing area_n based on the timing information regarding the cycle of the display video input from the CRT controller 110 (step S501).

  If the CPC 105 determines that image data has been read from the drawing area_n (step S501: Yes), the VCC 104 stops capturing in the next cycle of the captured video and does not write to the triple buffer (step S501). S503).

  Thereafter, the VCC 104 does not increment n, and determines whether or not writing of one frame (or one field) is completed (step S505). If the writing is not finished (step S505: No), the process returns to step S501 again to determine again whether image data is being read from the same drawing area.

  On the other hand, when the CPC 105 determines that no image data has been read from the drawing area_n (step S501: No), the VCC 104 writes the captured image data into the drawing area_n (step S502). Then, the VCC 104 increments n (step S504), returns to step S501 again, determines whether or not the next drawing area is being read, and executes similar processing.

  Thereafter, while writing is not finished (step S505: No), steps S501 to S505 are repeatedly executed, and the VCC 104 sequentially writes the captured image data into the drawing area_0 to the drawing area_2, and the writing of the drawing area_2 is finished. Then, returning to the drawing area_0 again, the same writing is repeated.

  In the above-described series of loop processing, when it is determined in step S505 that writing has been completed (step S505: Yes), writing of an image for one frame (or one field) is completed, but then the next frame (or field) is completed. The same process is repeated to write the image of In the increment in step S504, as described above, the increment of n = 2 is set to n = 0, and changes in the order of n = 0, 1, 2, 0,.

  As described above, the VCC 104 stops the next capture when the CPC 105 reads the triple buffer to be written next when the captured image data has been written to the triple buffer. The first determination means described in the claims refers to a function in which the VCC 104 determines whether image data has not been read from the drawing area_n in step S501.

Next, processing when the CPC 105 reads image data from the triple buffer in the video memory 3 will be described with reference to the flowchart of FIG.
As in FIG. 5, the three drawing areas constituting the triple buffer are the drawing area_0, the drawing area_1, and the drawing area_2, and the CPC 105 is in the order of the drawing area_0, the drawing area_1, the drawing area_2, the drawing area_0,. The image data is sequentially read from the three drawing areas. The same applies to the definition of the variable n.

  When the CPC 105 reads image data from the triple buffer in the video memory 3, that is, when reading image data from the drawing area_n (any one of the drawing area_0, the drawing area_1, and the drawing area_2) of the triple buffer. In FIG. 6, it is determined whether or not the VCC 104 is writing in the drawing area_n (step S601). If writing is in the drawing area_n (step S601: Yes), the CPC 105 reads from the same drawing area_n. Therefore, the VCC 104 instructs the CPC 105 to read the drawing area_n−1. When the CPC 105 inputs an instruction from the VCC 104, the image data stored in the drawing area_n−1 is read again (step S603). That is, image data in the same drawing area as the drawing area_n−1 that has been read at the time of the previous reading is continuously read.

  Thereafter, the CPC 105 does not increment n, and determines whether reading of one frame (or one field) is completed (step S605). If the reading is not completed (step S605: No), the process returns to step S601 again to determine whether or not the next drawing area is being written and the same processing is executed.

  On the other hand, when the VCC 104 has not written to the drawing area_n (step S601: No), the CPC 105 reads image data from the drawing area_n (step S602). Then, the CPC 105 increments n (step S604), returns to step S601 again, determines whether writing to the next drawing area is in progress, and executes the same processing.

  Thereafter, while reading is not finished (step S605: No), steps S601 to S605 are repeatedly executed, and the CPC 105 sequentially reads image data from the drawing area_0 to the drawing area_2. In the above-described series of loop processing, when it is determined that reading has been completed (step S605: Yes), reading of an image for one frame (or one field) is completed, but thereafter an image of the next frame (or field) is completed. The same process is repeated to read out.

As described above, the CPC 105 reads the image data of the same triple buffer again when the triple buffer to be read next is written by the VCC 104 when the reading of the image data from the triple buffer is completed. Do. The second determination means described in the claims refers to a function in which the CPC 105 determines whether image data is not written in the drawing area_n based on the input from the VCC 104 in step S602.
Moreover, although the flow of FIG.5 and FIG.6 mentioned above shall represent the flow of the image process for 1 frame (or field), it is not limited to this.

Next, the processing in the VCC 104 and the CPC 105 described with reference to FIGS. 5 and 6 will be specifically described with reference to FIGS.
FIG. 7 is a diagram showing the capture and display timings in setting 1 of FIG. 2, and is an example when the capture video frame period is shorter than the display frame period.

  In FIG. 7, at time t101 to t103, the CPC 105 reads out and displays the image data of the drawing area_0. On the other hand, at time t102 to t103, the VCC 104 writes the captured image data in the drawing area_2.

  Since the drawing area_0 to be written next by the VCC 104 is not read by the CPC 105 at the time t103, the determination in step S502 of FIG. 5 is No, and the VCC 104 is captured in the drawing area_0 from the time t103 to t104. Write image data.

  Since the drawing area_1 to be read next by the CPC 105 is not written by the VCC 104 at the same time t103, the determination in step S602 in FIG. 6 is No, and at time t103 to t105, the CPC 105 starts the image data from the drawing area_1. Is read.

  Since the drawing area_1 to be written next by the VCC 104 is read by the CPC 105 at time t104, the determination in step S502 of FIG. 5 is Yes, and the VCC 104 is captured in the next one cycle (time t104 to t106). Do not do. The VCC 104 writes the captured image data in the drawing area_1 at the timing of the next frame period (t106 to t108).

  Thus, when the captured video frame period is shorter than the display frame period, the VCC 104 stops capturing in the next one period when the writing process of the VCC 104 catches up with the reading process of the CPC 105.

  FIG. 8 is a diagram illustrating the capture and display timings in setting 1 of FIG. 2, and is an example in which the capture video frame period is longer than the display frame period.

  In FIG. 8, at time t201 to t203, the VCC 104 writes the captured image data in the drawing area_0. On the other hand, from time t202 to t203, the CPC 105 reads image data from the drawing area_2.

  Since the drawing area_0 to be read out next by the CPC 105 is not written by the VCC 104 at the time t203, the determination in step S602 in FIG. 6 is No. From time t203 to t204, the CPC 105 receives image data from the drawing area_0. read out.

  Since the drawing area_1 to be written next by the VCC 104 is not read by the CPC 105 at the same time t203, the determination in step S502 of FIG. 5 is No, and the VCC 104 is captured in the drawing area_1 at times t203 to t205. Write the processed image data.

  Since the drawing area_1 to be read next by the CPC 105 is written by the VCC 104 at the time t204, the determination in step S602 in FIG. 6 is Yes, and the CPC 105 draws again in the next one cycle (time t204 to t206). Image data is read from area_0. The CPC 105 reads the image data from the drawing area_1 at the timing of the next frame period (t206 to t208).

  As described above, when the capture video frame period is longer than the display frame period, when the reading process of the CPC 105 catches up with the writing process of the VCC 104, the CPC 105 captures an image from the same triple buffer as the previous period in the next period. Read data.

  FIG. 9 is a diagram showing capture and display timings in setting 2 of FIG. 2, and is an example in which the capture video frame period is shorter than the display field period. FIG. 9 shows a process for converting from the progressive system to the interlace system. For example, the process is performed when a 60 Hz progressive video signal is converted into a 50 Hz PAL video signal.

  In FIG. 9, the VCC 104 captures image data captured in the drawing area_0 from time t301 to t303, in the drawing area_1 from time t303 to t305, in the drawing area_2 from time t305 to t307, and in the drawing area_0 from time t307 to t308. Write.

  On the other hand, the CPC 105 reads the image data from the drawing area_0 to the 1st field data from time t304 to t306, and from the drawing area_1 to the 2nd field data from time t306 to t309.

  At time t308, since the drawing area_1 to be written next by the VCC 104 is read by the CPC 105, the VCC 104 does not capture in the next cycle (time t308 to t310). The VCC 104 writes the captured image data in the drawing area_1 at the timing of the next frame period (t310 to t312).

  Also in FIG. 9, as in FIG. 7, when the write processing of the VCC 104 catches up with the read processing of the CPC 105, the VCC 104 stops capturing in the next one cycle.

  FIG. 10 is a diagram showing capture and display timings in setting 3 of FIG. 2, and is an example when the capture field period is longer than the display frame period. FIG. 10 shows a process for converting from the interlace system to the progressive system. For example, the process is performed when a 50 Hz PAL video signal is converted into a 60 Hz progressive video signal.

  In FIG. 10, the VCC 104 has 1st field image data in the drawing area_0 from time t401 to t403, 2nd field image data in the drawing area_1 from time t403 to t405, and 1st field in the drawing area_2 from time t405 to t408. Capture and write image data.

  On the other hand, the CPC 105 reads image data from the drawing area_2 at times t402 to t404, from the drawing area_0 at times t404 to t406, and from the drawing area_1 at times t406 to t407.

  Since the drawing area_2 to be read next by the CPC 105 is written by the VCC 104 at the time t407, the CPC 105 reads the image data from the drawing area_1 again in the next cycle (time t407 to t409). The CPC 105 reads the image data from the drawing area_2 at the timing of the next frame period (t409 to t411).

  In FIG. 10, as in FIG. 8, when the reading process of the CPC 105 catches up with the writing process of the VCC 104, the CPC 105 reads the image data from the same triple buffer as the previous period in the next period.

  FIG. 11 is a diagram showing capture and display timings in setting 4 of FIG. 2, and is an example when the capture field period is shorter than the display field period. FIG. 11 shows a process for converting an interlace video format, for example, a process for converting a 60 Hz NTSC video signal into a 50 Hz PAL video signal.

  In FIG. 11, the VCC 104 has 1st field image data in the drawing area_0 from time t501 to t503, 2nd field image data in the drawing area_1 from time t503 to t505, and 1st field in the drawing area_2 from time t505 to t507. The image data of 2nd field is captured and written in the drawing area_1 at times t507 to t508.

  On the other hand, the CPC 105 reads the image data from the drawing area_0 to the 1st field data from time t504 to t506, and from the drawing area_1 to the 2nd field data from time t506 to t509.

  Since the drawing area_1 to be written next by the VCC 104 is read by the CPC 105 at the time t508, the VCC 104 does not capture in the next cycle (time t508 to t510). The VCC 104 writes the captured image data in the drawing area_1 at the timing of the next field cycle (t510 to t512).

  After the time t510, when the CPC 105 reads the image data captured by the VCC 104 until the time t519 at which the capture is stopped again, the 1st field and the 2nd field are reversed. In addition, the capture stop in the VCC 104 is in units of one field, and capture does not stop for two consecutive fields.

  Also in FIG. 11, as in FIG. 7, when the write processing of the VCC 104 catches up with the read processing of the CPC 105, the VCC 104 stops capturing in the next one cycle.

  FIG. 12 is a diagram showing the capture and display timings in the setting 6 or 8 in FIG. 2, and is an example in which the capture video frame period is shorter than the display frame period. FIG. 12 shows a process for converting an interlace video format, for example, a process for converting a 60 Hz NTSC video signal into a 50 Hz PAL video signal.

  In FIG. 12, the VCC 104 continuously captures the 1st field and 2nd field image data in the drawing area_0 from time t601 to t603, and continuously captures the 1st field and 2nd field image data in the drawing area_1 from time t603 to t604. And capture. On the other hand, the CPC 105 continuously reads the image data of the 1st field and the 2nd field from the drawing area_2 at times t602 to t605.

  At time t604, the drawing area_2 to be written next by the VCC 104 has been read by the CPC 105, so the VCC 104 does not capture in the next period (time t604 to t606). The VCC 104 writes the captured image data in the drawing area_2 at the timing of the next frame period (t606 to t608).

  Unlike the case shown in FIG. 11, in FIG. 12, since writing to and reading from the triple buffer is performed in units of frames, the image data captured by the VCC 104 does not reverse the 1st field and the 2nd field when the CPC 105 reads it out. . Further, the capture stop in the VCC 104 is in units of two fields, and the capture is stopped continuously for one frame.

  In FIG. 12, as in FIG. 7, when the write processing of the VCC 104 catches up with the read processing of the CPC 105, the VCC 104 stops capturing in the next one cycle.

  Note that the capture and display timing is the same regardless of which of the settings 6 or 8 in FIG. 2 is selected. However, in the setting 8, the 1st field and the 2nd field are alternately arranged on the video memory 3 to 1 Since the images are stored as one image, the resolution can be made higher than when setting 6 is used, particularly when a still image is displayed.

  On the other hand, in the setting 6, the 1st field and the 2nd field are stored separately on the video memory 3, which is suitable for displaying a moving image with intense motion. In this embodiment, as a storage method in the video memory 3, either a method for storing each field in a different region or a method for alternately storing each line in one region can be selected. And select the appropriate method.

  FIG. 13 is a diagram showing capture and display timings in setting 4 of FIG. 2, and is an example when the capture field period is longer than the display field period. FIG. 13 shows a process for converting an interlace video format, for example, a process for converting a 50 Hz PAL video signal into a 60 Hz NTSC video signal.

  In FIG. 13, the VCC 104 has 1st field image data in the drawing area_0 at times t701 to t703, 2nd field image data in the drawing area_1 at times t703 to t705, and 1st field in the drawing area_2 at times t705 to t708. Capture and write image data.

  On the other hand, the CPC 105 displays the image as the 2nd field data from the drawing area_2 at the times t702 to t704, the data from the drawing area_0 to the 1st field at the times t704 to t706, and the data from the drawing area_1 to the 2nd field at the times t706 to t707. Read data.

  Since the drawing area_2 to be read out next by the CPC 105 is written by the VCC 104 at the time t707, the CPC 105 reads the image data again from the drawing area_1 as the data of the 1st field in the next cycle (time t707 to t709). . The CPC 105 reads the image data as data of the 2nd field from the drawing area_2 at the timing of the next field cycle (t709 to t711).

  After time t707, the image data read by the CPC 105 until the time t718 at which the same triple buffer is continuously read again is obtained by reversing the 1st field and the 2nd field from the image captured by the VCC 104.

  Also in FIG. 13, as in FIG. 8, when the reading process of the CPC 105 catches up with the writing process of the VCC 104, the CPC 105 reads the image data from the same triple buffer as the previous period in the next period.

  FIG. 14 is a diagram illustrating capture and display timings in the setting 6 or 8 in FIG. 2, and is an example in which the capture video frame period is longer than the display frame period. FIG. 14 shows a process for converting an interlace video format, for example, a process for converting a 50 Hz PAL video signal into a 60 Hz NTSC video signal.

  In FIG. 14, the VCC 104 includes 1st field and 2nd field image data in the drawing area_0 from time t801 to t803, 1st field and 2nd field image data in the drawing area_1 from time t803 to t805, and from time t805 to t807. The image data of the 1st field and the 2nd field is continuously captured in the drawing area_2, and the image data of the 1st field and the 2nd field is continuously captured in the drawing area_0 from time t807 to t810.

  On the other hand, the CPC 105 displays image data of the 1st field and 2nd field from the drawing area_2 at times t802 to t804, image data of the 1st field and 2nd field from the drawing area_0 from time t804 to t806, and the drawing area at times t806 to t808. The image data of the 1st field and the 2nd field are sequentially read from _1 to 2nd field, and the image data of the 1st field and the 2nd field are sequentially read from the drawing area_2 from time t808 to t809.

  At time t809, the drawing area_0 to be read out next by the CPC 105 is written by the VCC 104. Therefore, the CPC 105 again outputs the image data of the 1st field and 2nd field from the drawing area_2 in the next one cycle (time t809 to t811). Read continuously. The CPC 105 continuously reads the image data of the 1st field and the 2nd field from the drawing area_0 at the timing of the next frame period (t811 to t813).

  Also in FIG. 14, as in FIG. 8, when the reading process of the CPC 105 catches up with the writing process of the VCC 104, the CPC 105 reads image data from the same triple buffer as the previous period in the next period.

  As described above, in this embodiment, the image data captured by the VCC 104 is sequentially written in the three drawing areas (triple buffers) configured on the video memory 3 and the image data is sequentially read by the CPC 105, and the writing process by the VCC 104 is performed by the CPC 105. When catching up with the reading process by the CPC 105, the capture is stopped for one cycle. Conversely, when the reading process by the CPC 105 catches up with the writing process by the VCC 104, the same drawing area is continuously read so that the drawing area by the CPC 105 During the reading process from the VCC, the VCC 104 does not write to the drawing area, and tearing can be prevented.

  7 to 14, in the conversion from the progressive method to the interlace method, the conversion from the interlace method to the progressive method, the conversion from the NTSC format to the PAL format, and the conversion from the PAL format to the NTSC format. Then, an operation for enlarging or reducing the image occurs.

  Therefore, as shown in FIG. 15, the CPC 105 calculates the coordinates (x, y) of the display data from the coordinates (X, Y) displayed in the display plane area, and the CPC 105 calculates the position of the coordinates (x, y). Image data needs to be read from the triple buffer.

If Sx is an X-direction enlargement / reduction correction coefficient, and Sy is an Y-direction enlargement / reduction correction coefficient, the CPC 105 performs the following calculations (1) and (2) to display the coordinates (x, y) of the display data. Ask for.
x = X × Sx (1)
y = Y × Sy (2)

  However, when the captured image is an interlaced 2nd field image, the origin of the image is different from the origin of the original image of one frame. Is performed, image data having coordinates different from the coordinates that should be read out is read out from the CPC 105.

  Similarly, even when an image to be displayed is an interlaced 2nd field image, the origin of the image is different from the origin of the display image of one frame, and therefore the enlargement / reduction is performed with reference to the origin of the image of the 2nd field. When the processing is performed, image data having coordinates different from the coordinates that should be originally read is read from the CPC 105.

  Further, as described above with reference to FIGS. 11 and 13, when the captured 1st field image is displayed as the 2nd field, or when the captured 2nd field image is displayed as the 1st field, the origin of the 1st field image is also displayed. Since the origin of the image in the 2nd field is different from that of the 2nd field, image data having coordinates different from the coordinates to be read out is read out from the CPC 105.

  In the following, with respect to a method for correcting the coordinate after enlargement / reduction to be a coordinate to be originally displayed even when the captured image or the displayed image is an interlaced 2nd field image, FIGS. Will be described with reference to FIG.

  In FIG. 16A, when the VCC 104 captures an interlaced image in the field unit and writes it in the triple buffer on the video memory 3, the size of the image written in the field unit in the y-axis direction is 1 of the original image. / 2.

  At this time, the y coordinate y0 of the origin of the original image coincides with the origin of the image of the 1st field, but does not coincide with the origin of the image of the 2nd field. If the origin of the coordinates of the 2nd field is set to 0, y0 becomes a position of -0.5. That is, the coordinate y ′ based on the origin y0 of the original image is obtained by y ′ = y + 0.5.

Therefore, in the formula (2), by substituting y for y ′, a calculation formula for performing enlargement / reduction with the origin y0 of the original image as a reference is obtained.
y ′ = Y × Sy (3)
Here, substituting y ′ = y + 0.5 into the expression (3) yields the expression (4), and the CPC 105 performs correction by adding −0.5 from the calculation result according to the expression (2) to thereby obtain the origin y0 of the original image. Enlargement and reduction can be performed on the basis of.
y = Y × Sy−0.5 (4)

  The expression (4) is, for example, an address (x, y) at which the CPC 105 reads image data from the drawing area_1 when displaying the image data of the 2nd field captured at time t403 to t405 in FIG. 10 at time t406 to t407. Is used to calculate

  On the other hand, in FIG. 16B, when the CPC 105 displays an interlaced image, the size of the display image for each field in the Y-axis direction is ½ of the display image of one frame.

  At this time, the Y coordinate Y0 of the origin of the display image of one frame coincides with the origin of the image of the first field, but does not coincide with the origin of the image of the second field. If the origin of the coordinates of the 2nd field is set to 0, Y0 becomes a position of -0.5. That is, the coordinate Y ′ with reference to the origin Y0 of the display image of one frame is obtained by Y ′ = Y + 0.5.

Therefore, in the equation (2), by substituting Y for Y ′, a calculation equation for performing enlargement / reduction based on the origin Y0 of the display image of one frame is obtained.
y = Y ′ × Sy (5)
Here, if Y ′ = Y + 0.5 is substituted into equation (5), equation (6) is obtained, and the CPC 105 performs one-frame display by performing correction by adding 0.5 to the Y coordinate in the calculation according to equation (2). Enlargement and reduction can be performed with reference to the origin Y0 of the image.
y = (Y + 0.5) × Sy (6)

  The expression (6) is, for example, an address (x) from which the CPC 105 reads image data from the drawing area_1 when displaying the image data captured at time t303 to t305 in FIG. 9 as image data of the 2nd field at time t306 to t309. , Y).

When the CPC 105 reads and displays the 2nd field image captured by the VCC 104 as a 2nd field image, the CPC 105 performs both the correction related to the y coordinate in the expression (4) and the correction related to the Y coordinate in the expression (6). Enlargement / reduction conversion is performed using equation (7).
y = (Y + 0.5) × Sy−0.5 (7)

  For example, when the 2nd field image data captured at time t503 to t505 in FIG. 11 is displayed as the 2nd field image data at time t506 to t509, the CPC 105 reads the image data from the drawing area_1. Used to calculate the address (x, y).

  FIG. 17 is a functional configuration diagram illustrating functions when the CPC 105 performs coordinate conversion for enlargement / reduction. In FIG. 17, reference numeral 11 denotes an x-coordinate conversion unit that performs coordinate conversion for obtaining the x-coordinate from the X-coordinate, and specifically performs the calculation of equation (1).

  Reference numeral 12 denotes a first offset correction unit that adds offset_1 to the Y coordinate. Offset_1 is set to +0.5 only when the display image is an interlace method and a 2nd field is displayed, otherwise offset_1 = 0. It becomes. The correction by the first offset correction unit 12 corresponds to the correction performed by equation (6).

  The first offset correction unit 12 determines whether the display image from the CRT controller 110 is an image of a progressive system, an interlace system 1st field, or an interlace system 2nd field.

  Reference numeral 13 denotes a y-coordinate conversion unit that performs coordinate conversion for obtaining the y-coordinate from the Y-coordinate, and specifically performs the calculation of equation (2). Reference numeral 14 denotes a second offset correction unit that adds offset_2 to the calculation result of the y-coordinate conversion unit, and only when the captured image is an interlaced image and a 2nd field image, offset_2 is −0.5. In other cases, offset_2 = 0. The correction by the second offset correction unit 14 corresponds to the correction performed by the equation (4).

  The second offset correction unit 12 determines whether the image captured from the VCC 104 is an image of the progressive method, the interlace method 1st field, or the interlace method 2nd field.

  The coordinate correction method performed by the CPC 105 has been described above. However, the above correction method can be used not only when performing enlargement / reduction processing but also when performing other coordinate transformations such as tilt correction and distortion correction. is there.

If the function for obtaining the coordinate x of the display data from the coordinate X displayed in the display plane area is Fx, and the function for obtaining the coordinate y of the display data from the coordinate Y displayed in the display plane area is Fy, the CPC 105 performs the function. The coordinate transformation is generally expressed by the equations (8) and (9).
x = Fx (X, Y) (8)
y = Fy (X, Y) (9)

When correction using offset_1 and offset_2 is performed on the equations (8) and (9), equations (10) and (11) are obtained.
x = Fx (X, Y + offset_1) (10)
y = Fy (X, Y + offset_1) + offset_2 (11)
In the above-described enlargement / reduction processing, Fx (X, Y) = X × Sx and Fy (X, Y) = Y × Sy.

  In the present embodiment, when the captured image or the display image is an interlaced 2nd field image, the CPC 105 performs offset conversion by offset_1 or offset_2, thereby performing coordinate conversion based on the original one frame image. This makes it possible to display image data of accurate coordinates that should be displayed.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, in the present embodiment, three drawing areas are provided as triple buffers in the video memory area. However, it is also possible to provide four or more drawing areas to sequentially write and sequentially read captured image data.

  The present invention is suitable for use in an image processing apparatus that outputs a display video at a different period from a capture video.

It is a block diagram which shows the structure of the image processing apparatus which concerns on one Embodiment of this invention. It is a figure which shows the correspondence of the capture and display mode in VDP1 of FIG. 1, and the increment of a triple buffer. It is a figure which shows the function of each drawing mode shown in FIG. FIG. 3 is a diagram showing a captured video storage area in a video memory 3 in each mode shown in FIG. 2. 5 is a flowchart showing processing when the VCC 104 writes captured image data in a triple buffer in the video memory 3. 4 is a flowchart showing processing when the CPC 105 reads out image data from a triple buffer in the video memory 3. FIG. 3 is a diagram illustrating capture and display timings in setting 1 of FIG. 2, and is an example when a captured video frame period is shorter than a display frame period. FIG. 3 is a diagram showing capture and display timings in setting 1 of FIG. 2, and is an example when a captured video frame period is longer than a display frame period. FIG. 4 is a diagram showing capture and display timings in setting 2 of FIG. 2, and is an example in a case where a captured video frame period is shorter than a display field period. FIG. 4 is a diagram illustrating capture and display timings in setting 3 of FIG. 2, and is an example in which a capture field cycle is longer than a display frame cycle. FIG. 6 is a diagram illustrating capture and display timings in setting 4 of FIG. 2, and is an example in which a capture field period is shorter than a display field period. It is a figure which shows the timing of the capture and display in the setting 6 or 8 of FIG. 2, and is an example in case a capture video frame period is shorter than a display frame period. It is a figure which shows the timing of the capture and display in the setting 4 of FIG. 2, and is an example in case a capture field period is longer than a display field period. It is a figure which shows the timing of the capture and display in the setting 6 or 8 of FIG. 2, and is an example in case a capture video frame period is longer than a display frame period. It is a figure which shows the coordinate transformation performed by CPC105. It is a figure which shows the positional relationship of the origin of the image of 1 frame, and the image of 1st field and 2nd field in an interlace system. It is a functional block diagram which shows the function at the time of performing coordinate conversion of expansion / reduction by CPC105.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... VDP (image processing apparatus), 2 ... CPU, 3 ... Video memory, 11 ... X coordinate conversion part, 12 ... 1st offset correction part, 13 ... y coordinate conversion part, 14 ... 2nd offset correction part, DESCRIPTION OF SYMBOLS 101 ... CPU interface module, 102 ... VRAM interface module, 103 ... VDU, 104 ... VCC (image writing means), 105 ... CPC (image reading means), 106 ... DPU, 107 ... OSD plane controller, 108 ... PDC, 109 ... DAC, 110 ... CRT controller, 111 ... clock generator.

Claims (3)

Image writing means that captures input digital video data and sequentially writes the image data captured in the first cycle to the three or more image storage areas through the three or more image storage areas;
Image reading means for sequentially reading out the image data in a second cycle from the three or more image storage areas through the three or more image storage areas;
When the image writing means finishes writing to one of the three or more image storage areas, the other one of the three or more image storage areas to be written next by the image writing means is the image reading means. Determining means for determining whether reading is in progress,
When the determination unit determines that the image storage area is being read by the image reading unit, the image writing unit stops capturing the digital video data, and the image is stored in the next first cycle. Without writing image data to the storage area
The determination means further determines whether the image storage area to be read next by the image reading means is being written by the image writing means when the image reading means finishes reading from the image storage area. Judgment,
When the determination means determines that the image storage area to be read next by the image reading means is being written by the image writing means, the image reading means immediately before the next second period. An image processing apparatus that reads image data from the read image storage area again. The image writing means captures input interlaced video data in units of frames and writes it to the image storage area, and stores it in a separate area within the image storage area for each field, or The image processing apparatus according to claim 1, wherein it is possible to select whether to store each line alternately in one area in the image storage area. An image writing procedure that captures input digital video data and sequentially writes the image data captured in the first cycle to the three or more image storage areas in the three or more image storage areas;
An image reading procedure for reading out the image data sequentially in a second cycle from the three or more image storage areas and circulating through the three or more image storage areas;
When the writing to one of the three or more image storage areas is completed in the image writing procedure, the other one of the three or more image storage areas to be written next in the image writing procedure is the image reading procedure. And a determination procedure for determining whether reading is in progress,
When the determination procedure determines that the image storage area is being read by the image reading procedure, the image writing procedure stops capturing the digital video data, and the image is stored in the next first cycle. Without writing image data to the storage area
The determination procedure further determines whether the image storage area to be read next in the image reading procedure is being written by the image writing procedure when reading from the image storage area is completed in the image reading procedure. Judgment,
When it is determined in the determination procedure that the image storage area to be read next in the image reading procedure is being written in the image writing procedure, the image reading procedure is performed immediately before in the next second cycle. An image processing method of reading image data from the read image storage area again.

Images