JP2001092429A - Frame rate converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frame rate converter which frame-rate-converts video signals at an arbitrary ratio using a more simple constitution. SOLUTION: Inputted video signals are written into any one of first to third picture memories 104 (a bank A) to 106 (a bank C) by an input bank switcher 102. The write-in memory bank is specified by a write-in control circuit 112 which determines whether to increment a memory bank to be written-in next or not based on input and output vertical synchronizing signals. The video signals written in each picture memory are outputted by selecting an appropriate bank by an output bank switcher 110. A read-out memory bank is specified by a read-out control circuit 114 which determines whether to increment a memory bank to be written-in next or not based on the input and output vertical synchronizing signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame rate converter for converting an input video signal having a predetermined frame rate into a desired frame rate and outputting the converted signal.

[0002]

2. Description of the Related Art There are various types of specifications for video image signals and graphics signals (hereinafter simply referred to as video signals or image signals) such as personal computers (PCs). Generally, VESA (Video E
Electronics standard associations (hereinafter referred to as VESA standard signals) are widely known, but even VESA standard signals alone can have dozens of formats when combined with image size and frame frequency. Also, for example, ATSC-DTV (Advanced Television System Commit
tee Digital TeleVision) has a total of 18 signal standards.

On the other hand, in an output side device such as a display device or a storage device, or an in-station video processing device such as an editing device, an image format to be processed is generally specified in many cases. Therefore, in order to process various signals as described above by the device, it is necessary to convert the signal format into a format that can be processed by the device. For that purpose, an apparatus capable of mutually converting these various video signals is desired.

A conventional example of such a frame rate conversion apparatus will be described with reference to FIGS. Here, a frame rate conversion device that outputs a non-interlaced input video signal at a frame rate frequency different from the input in order to display a video on a fixed pixel display device such as a liquid crystal display panel or a plasma display panel will be described. I do. FIG. 10 is a conceptual diagram for explaining the operation of the frame rate conversion device. The frame rate conversion device is controlled independently of the input and output ports (Input Controller, Output Controller)
The video data (Input Data) input from the input port at a certain rate is temporarily stored in the image memory (Frame
Store Memory) and output from the output port at the requested frame rate (Output Data). That is, the frame rate converter converts the synchronization of the video signal by independently performing the operation of writing the video signal to the image memory and the operation of reading the video signal.

The image memory used at this time is generally a VRAM (Video-RAM) constituted by a multi-port memory, but any memory capable of storing digital signals can be stored as long as the input or output access speed is sufficient. Can be used. For example, SDRAM (S
An asynchronous dynamic RAM (Synchronous Dynamic RAM) is a single-port memory that has only one input / output port.
t-In First-Out) or the like as an I / O buffer, it is possible to pseudo-operate as a dual port memory such as a VRAM.
The image memory may be configured by the AM.

FIGS. 11A to 11C are diagrams for specifically explaining the operation of the frame rate conversion apparatus shown in FIG. 10, and in each of the figures, data i0 to i8 are shown.
Indicates image data for one frame of the raster scan structure, and the horizontal axis indicates time. FIG. 11 (A)
Is an example of down-rate conversion from 5 frames to 4 frames. For every 5 input frames, 1 frame (frame i
4) is discarded and four frames are output. FIG.
(B) is an example of up-rate conversion from three frames to four frames, and four frames are output by repeating one frame (frames i2, i5, i8) extra for three input frames.

FIG. 11 (C) shows an equal-size conversion, and the input frame rate and the output frame rate are the same. In this example of constant rate conversion, a case is shown where the initial phase of the output image is different even though the frame rate is the same. Here, the frame rate ratio between input and output is an integer ratio, but in general, when performing frame rate conversion, the conversion ratio often does not become an integer ratio. In many cases, the initial phase difference between input and output images is not uniquely determined.

As described above, the frame rate conversion is performed under various conditions. It is important that the frame is not switched in the middle of one screen (one frame) image in any case. . what if,
If this condition is not satisfied in the process of frame rate conversion and a picture at a different time switches from the middle of one screen, the picture will appear discontinuous, or in the moving picture, the picture will be jagged in the time direction. You will see it.

Such a state is called so-called memory overtaking, and occurs because the speed of writing an image to the image memory is different from the speed of reading an image from the image memory. There are two types of overtaking depending on whether the write address overtakes the read address or the read address overtakes the write address.
In either case, pictures of different frames are displayed on the same output screen, and this boundary is recognized as an error. FIGS. 12A and 12B show states of input / output data and memory access when the write address passes the read address and when the read address passes the write address, respectively.

As a method of preventing such overtaking, for an interlaced image, a method of controlling a read frame using an image memory for four fields so as not to read field data for which writing has not been completed, for example, There is a method disclosed in Japanese Patent Application Laid-Open No. 10-200783, in which the necessary readout control is performed by reducing the required image memory capacity to three fields. Further, for example, Japanese Patent Application Laid-Open No. 7-203383 discloses a method of switching frames by predicting in advance a discontinuous point at which overtaking will occur, based on an input and output vertical synchronization signal.

In Japanese Patent Application Laid-Open No. 11-18082, by using three frame memories and performing writing and reading for different frames, the overtaking occurs for the frame being read. And writing and reading are performed appropriately while converting the frame rate. Specifically, when sequentially reading frames in which data has been written, when writing to the read target frame is not completed, the contents of the previous frame are read, and the read target frame is overwritten with newer data. If it is determined that the frame is read, the frame to be read is determined so that the content of the next frame is read. The determination of the writing frame is the same.

[0012]

However, in most of the various methods described above, the target video signal is an interlace signal, and the method is directly applied to a non-interlace signal represented by a computer graphic signal. It is a method that can not do.

In the method of predicting the overtaking and avoiding the overtaking, it is necessary to know in advance from the frame interval of writing and reading whether the conversion is the up-rate conversion or the down-rate conversion before performing the frame synchronizing operation. Or the input (for writing) vertical synchronizing signal or the output (for reading) vertical synchronizing signal deviates in time for some unexpected reason, or the vertical synchronizing frequency fluctuates (the speed of writing to or reading from the memory increases. In the case where the time is slowed down or slowed down, it cannot be predicted, and during that time, the image is disturbed.

In the case of such a prediction method, when the mode is switched by the input source signal itself, and when the output refresh frequency is switched, for example, the preparation time for the prediction is changed for a while after the switching. In many cases, overtaking of the memory occurs during that time, and there is a problem that an image cannot be displayed normally. To cope with this problem, for example, the latest normally written one-frame video is saved, and the video is frozen or blacked out (blanking the picture) until normal operation is restored. However, in any case, there is a problem that an image cannot be correctly output during that time.

[0015] Further, in terms of hardware, a separate CPU for prediction is required, and other hardware is required, which has caused a cost increase. Furthermore, since the ratio between the frame rates of the input video signal and the output video signal is considered only in a limited combination to some extent, there is a problem that a failure occurs in a ratio of an unexpected combination.

In the method of using three frame memories and performing writing and reading on different frames, when writing a video signal, one frame memory is used as a writing target frame memory from the three frame memories. When the video signal is read out, the process of selecting the memory is performed as a frame memory to be read out.
The process of selecting one frame memory from one frame memory must always be performed, and there is a problem that the control circuit becomes complicated. In particular, when such a frame rate conversion device is formed on a semiconductor device,
It is preferable to reduce the number of gates used even a little,
There is a demand for a simpler control circuit.

Therefore, an object of the present invention is to provide a frame rate conversion device for converting a non-interlaced video signal of a predetermined frame rate into a non-interlaced video signal of an arbitrary phase at an arbitrary frame rate ratio with a simpler configuration. To provide.

[0018]

In order to solve the above-mentioned problems, a frame rate conversion apparatus according to the present invention has a storage capacity capable of storing image data of a predetermined unit, and is cyclically arranged in a predetermined order. When writing new image data to be written into the image memory unit, the ordered first to third image memory units and the sequentially input image data for each predetermined unit are written in the image memory unit. Writing memory selecting means for selecting one of the image memory means which has written the image data for each image or the image memory means which is arranged next to the image memory means; and the new image data to be written is stored in the selected image memory means. Image writing means for writing image data for each predetermined unit based on a synchronization signal of the input image data, and a predetermined unit for sequentially outputting the image data. When reading out new image data for each predetermined unit of image data from the image memory unit, the image memory unit that immediately read out the image data for each predetermined unit or the image data unit and the ordering unit Reading memory selecting means for selecting any one of the image memory means, and image reading for reading out the image data for each of the predetermined units stored in the selected image memory means based on a desired output synchronization signal. Means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a frame rate converter according to the present invention will be described with reference to FIGS.

First, the configuration of the frame rate conversion device according to the present embodiment will be described. FIG. 1 is a block diagram illustrating a configuration of a frame converter 100 according to the present embodiment. The frame rate conversion device 100 includes an input bank switch 102, a first image memory (bank A) 10
4. Second image memory (bank B) 106, third image memory (bank C) 108, output bank switch 11
0, write control circuit 112, read control circuit 114
And a bank setting circuit 116.

First, the configuration of each part of the frame rate conversion device 100 will be described. Input bank switch 10
2 extracts a video signal for each frame from a video signal input to the frame rate conversion device 100 based on a control signal input from the writing control circuit 112. In addition, the video signal for each extracted frame is selectively output to any of the first image memory 104 to the third image memory 108 based on the bank designation signal input from the write control circuit 112.

The first image memory 104 to the third image memory 108 are image storage units each configured as a so-called bank (bank A to bank C) in the memory unit. Each bank has a capacity capable of recording a video signal for one frame, and the input bank switch 10
The video signal for each frame, which is selectively input by step 2, is recorded based on the control signal input from the write control circuit 112. The recorded video signal is reproduced based on the control signal input from the read control circuit 114 and output to the output bank switch 110.

The output bank switch 110 receives a signal from one of the first image memory (bank A) 104 to the third image memory (bank C) 108 based on a bank designation signal input from the read control circuit 114. A video signal for each frame reproduced and output is selectively read. Further, based on the control signal input from the read control circuit 114, a series of video signals are assembled from the read video signals for each frame, and output from the frame rate conversion device 100 as output video signals.

The write control circuit 112 controls the writing of the video signal input to the frame rate conversion device 100 to the first to third image memories 104 to 108 via the input bank switch 102. Specifically, the write control circuit 112 outputs a control signal for extracting a signal for each frame from the input video signal based on a vertical synchronization signal of the input video signal, and a video signal for each frame. Bank to record (first to third
Of the three image memories 104 to 108) is generated, and the input bank switch 102
Output to The write control circuit 112 also controls the video signal selected by the input bank switch 102 so that the video signal is appropriately recorded in the first image memory (bank A) 104 to the third image memory (bank C) 108. It controls the recording of data for each bank.

The read control circuit 114 outputs the first image memory (bank A) 104 to the third image memory (bank C) so that a video signal having a frame rate required by the frame rate converter 100 is output. 108 and the output bank switch 110. More specifically, the read control circuit 114 stores the video signals for each frame for assembling the output video signal in the first image memory (bank A) 104 to the third image memory (bank C) 1
The reproduction of data for each of these banks is controlled so as to be appropriately selected and read out from step 08. Further, the read control circuit 114 controls the control signal for assembling the output video signal from the signal for each frame based on the vertical synchronization signal of the input output video signal, and the bank (first
To the third three image memories 104 to 108) are generated and output to the output bank switch 110.

The bank setting circuit 116 is a circuit for initializing a video signal writing bank and a video signal reading bank when power is turned on or reset. The bank setting circuit 116 controls the states of the vertical synchronization signal of the input video signal and the vertical synchronization signal of the output synchronization signal,
And detecting whether or not the video signal writing bank and the video signal reading bank are in the state to be initialized based on the state of the signal such as the power supply. A signal designating a bank as an initial state is output to the circuit 112 and the read control circuit 114, respectively. The frame rate conversion device 100 has such components.

In the frame rate conversion apparatus 100 having such a configuration, in order to perform a desired frame rate conversion, how to select a write bank and a read bank of a video signal based on their relationship is described. It becomes important. Hereinafter, a method of selecting a write bank and a method of selecting a read bank, which are mainly performed in the write control circuit 112 and the read control circuit 114, will be described in detail.

First, the configuration and operation of the write control circuit 112 will be described in detail. Write control circuit 11
In 2, the video signals for each frame that are sequentially input are selectively written into three banks A to C (first to third three image memories 104 to 108). Basically, the selection method is to sequentially write parameters to the banks A to C by cyclically incrementing the parameters indicating the banks. For example, in the case of down-rate conversion for reducing the frame rate, the video of the bank to be written is If the signal has not been read yet, writing is performed successively in the same bank, and the frame is substantially thinned out.

The processing of the write control circuit 112 will be described in detail. FIG. 2 is a state transition diagram for explaining a method of processing for selecting a bank in which an input video signal is written in the write control circuit 112. First, when a reset signal RESET is input from the bank setting circuit 116, such as when power is turned on or a reset is applied, the write control circuit 112 sets the internal state to the initial status S201. In this state,
First image memory (bank A) 1 as a writing bank
04 is selected.

In this state, while the write bank increment signal INC_WBANK is not input (in the present embodiment, while INC_WBANK = 0), the state S201 is maintained, and the first image memory (bank A) is used as a write bank. 104 continues to be selected. The write bank increment signal INC_WBANK becomes valid (in the present embodiment, INC_WBANK
= 1), the writing control circuit 112 shifts the state to the state S202, and selects the second image memory (bank B) 106 as a writing bank.

In the state S202, similarly to the state S201, the write bank increment signal INC_W
While BANK = 0, the state S202 is maintained, and the second image memory (bank B) 106 is continuously selected as a writing bank. Then, when the write bank increment signal INC_WBANK = 1, the write control circuit 112 shifts the state to the state S203, and selects the third image memory (bank C) 108 as the write bank.

Similarly, in state S203, state S
Similarly to 201 and S202, the state S203 is maintained while the write bank increment signal INC_WBANK = 0, the third image memory (bank C) 108 is continuously selected as a write bank, and the write bank increment signal INC_WBANK = 1. The write control circuit 112 shifts the state to the state S201 and sets the first image memory (bank A) 10 as a write bank.
Select 4. The write control circuit 112 sequentially selects the bank in which the video signal is to be written by such a control method.

Next, a method of generating a write bank increment signal INC_WBANK for performing such control in the write control circuit 112 will be described. FIG. 3 is a diagram showing a specific example of a circuit for generating the write bank increment signal INC_WBANK in the write control circuit 112. As shown in FIG. 3, the write bank increment signal generation circuit 300 includes D flip-flops (D-FFs) 301 and 3.
02, 309, NOR elements 302, 304, and an RS flip-flop (RS-FF) 308 are connected as shown.

In such a circuit, the D-FF 301
The NOR element 302 detects an edge of the vertical synchronizing signal Fp_w of the input write video signal and generates a write set signal setW having a pulse width corresponding to the write clock Ck_w width. This light set signal setW
Is a signal at which a transition of a frame of a video signal to be written is detected. Also, the D-FF 303 and the NOR
The element 304 detects the edge of the vertical synchronization signal Fp_r of the input read video signal, and
Write reset signal reset having a pulse width of k_w width
Generate W. This write reset signal resetW
Is a signal that detects a changing eye of a frame of a video signal to be read.

By setting the write set signal setW and the write reset signal resetW as the set signal and the reset signal of the RS-FF 308, respectively, as shown in the figure, the signal shows the relationship between the write bank and the read bank of the video signal. When the high level, the bank next to the write bank is the read bank,
When low, the signal Q_wr indicating that the bank next to the read bank is a write bank, in other words, the bank next to the write bank is not in a read state.
te is generated. This is based on the fact that the frame rate conversion apparatus 100 has three banks, and as described above, the writing bank is set to be one ahead of the reading bank in the initial state.

Then, the signal Q_write and the write set signal setW are connected to the D-FF 309 as shown in the figure.
The write bank increment signal I which is a signal for outputting the state of the signal Q_write in synchronization with the write set signal setW, and which serves as a control signal for the state transition of the write control circuit 112 as described above.
NC_WBANK is generated. As described above, when the signal Q_write is at the low level, it indicates that the bank next to the write bank is not in the read state, that is, it is a writable bank. Therefore, when the write set signal setW is generated, the signal The fact that Q_write is at the low level means that the write bank may be incremented.

Next, such a write control circuit 112
Will be collectively described with reference to FIG. First, as an initial state, an arbitrary bank, for example, the first image memory (bank A) 104 is selected (step ST401). Then, the vertical synchronizing signal of the input video signal is observed, and the head of the video signal frame is detected (step ST402). When the head of the frame is detected, writing of the input video signal to the previously selected bank is started. (Step ST403).

That is, the input bank switch 102 and the first image memory (bank A) 104 to the third image memory (bank C) 108 are controlled to sequentially read signals for each pixel, and And the write address is sequentially incremented (step ST404). Each time a signal for one pixel is stored, it is detected whether the input and storage of an image for one frame has been completed (step ST405), and if not completed, the process of step ST404 is repeated.

In step ST405, if the input and storage of the image for one frame has been completed, the write bank increment signal INC_WBANK described above with reference to FIG. 3 is referred to (step ST40).
6) In the case of 0, the write bank is incremented (step ST407), and in the case of 1, the write bank is not incremented (step ST408). That is, the write bank increment signal INC_WB
When ANK is 0, the bank for writing the signal of the next frame is selected as the next bank. When it is 1, the bank for writing the input video signal is continuously selected as the bank for writing the signal of the next frame. I do. In any case, the process returns to step ST402 to detect the head of the next frame, and thereafter, repeats the processing from step ST403.

Next, the configuration and operation of the read control circuit 114 will be described in detail. Read control circuit 11
Reference numeral 4 selectively reads and outputs a video signal for each frame from three banks A to C (first to third three image memories 104 to 108). The selection method is basically to sequentially read the banks A to C by cyclically incrementing the parameter indicating the bank. For example, in the case of up-rate conversion for increasing the frame rate, the bank to be read is read. If the video signal has not yet been written, or is being written, the same bank is read continuously, and processing for substantially adding a frame is performed.

The processing of the read control circuit 114 will be described in detail with reference to FIG. FIG. 5 is a state transition diagram of a process in the read control circuit 114 for selecting a bank from which an output video signal is read. First,
When a reset signal RESET is input from the bank setting circuit 116, for example, when power is turned on or a reset is applied, the read control circuit 114 sets the internal state to the initial status S501. In this state, the third image memory (bank C) 108 is selected as a read bank.

In this state, while the read bank increment signal INC_RBANK is not input (in the present embodiment, while INC_RBANK = 0), the state S501 is maintained, and the third image memory (bank C) is used as a read bank. 108 continues to be selected. The read bank increment signal INC_RBANNK becomes valid (in the present embodiment, INC_RBANNK).
= 1), the read control circuit 114 shifts the state to the state S502, and selects the first image memory (bank A) 104 as a read bank.

In state S502, similarly to state S501, read bank increment signal INC_R
While BANK = 0, the state S502 is maintained, and the first image memory (bank A) 104 is continuously selected as a read bank. Then, when the read bank increment signal INC_RBANK = 1, the read control circuit 114 shifts the state to the state S503, and selects the second image memory (bank B) 106 as the read bank.

Similarly, in the state S503, the state S
Similarly to 501 and S502, the state S503 is maintained during the read bank increment signal INC_RBANK = 0, the second image memory (bank B) 106 is continuously selected as the read bank, and the read bank increment signal INC_RBANK = 1. The read control circuit 114 shifts the state to the state S501, and sets the third image memory (bank C) 10 as a read bank.
Select 8. The read control circuit 114 sequentially selects the bank from which the video signal is read by such a control method.

Next, a method of generating the read bank increment signal INC_RBANK for performing such control in the read control circuit 114 will be described. FIG. 6 is a diagram showing a specific example of a circuit for generating the read bank increment signal INC_RBANK in the read control circuit 114. As shown in FIG. 6, the read bank increment signal generation circuit 600 includes D flip-flops (D-FF) 601, 6
02, 609, NOR elements 602, 604 and an RS flip-flop (RS-FF) 608 are connected as shown.

In such a circuit, the D-FF 601
The NOR element 602 detects the edge of the vertical synchronization signal Fp_r of the input read video signal, and generates a read set signal setR having a pulse width equal to the width of the read clock Ck_r. This read set signal setR
Is a signal at which a transition of a frame of a video signal to be read is detected. In addition, D-FF 603 and NOR
The element 604 detects the edge of the vertical synchronization signal Fp_w of the input write video signal, and
read reset signal reset having a pulse width of k_r width
Generate R. This read reset signal resetR
Is a signal at which a transition of a frame of a video signal to be written is detected.

By setting the read set signal setR and the read reset signal resetR as the set signal and the reset signal of the RS-FF 608 as shown in the figure, the signal indicates the relationship between the read bank and the write bank of the video signal. When the high level, the bank next to the read bank is the write bank,
A signal Q_rea indicating that the bank next to the write bank is a read bank at the low level, in other words, the bank next to the read bank is not in a write state.
d is generated. This is because the frame rate conversion apparatus 100 has three banks, and as described above, the writing bank is set to be one ahead of the reading bank in the initial state. .

By inputting the signal Q_read and the read set signal setR to the D-FF 609 as shown in the figure, the signal Q_read outputs a state of the signal Q_read in synchronization with the read set signal setR.
A read bank increment signal INC serving as a state transition control signal of the read control circuit 114 as described above.
_RBANK is generated. As described above, the signal Q_
When read is at a low level, it indicates that the bank next to the read bank is not in a write state, that is, it is a readable bank. Therefore, when the read set signal setR is generated, the signal Q_read is said to be at a low level. This means that the read bank may be incremented.

Next, such a read control circuit 114
Will be collectively described with reference to FIG. First, as an initial state, one of the write banks 1
The previous bank, that is, the third bank in the present embodiment.
Image memory (bank C) 108 is selected (step ST701). Then, the vertical synchronizing signal of the input output video signal is observed, the head of the frame of the output video signal is detected (step ST702), and when the head of the frame is detected, reading of the video signal from the previously selected bank is started. (Step ST703).

That is, the first image memory (bank A)
By controlling the 104-third image memory (bank C) 108 and the output bank switch 110, the signal for each pixel is sequentially read and the read address is sequentially incremented (step ST704). Each time a signal for one pixel is stored, it is detected whether or not reproduction and output of an image for one frame have been completed (step ST705). If not completed, the process of step ST704 is repeated.

If it is determined in step ST705 that the reproduction and output of one frame of image have been completed, the read bank increment signal INC_RBANNK described above with reference to FIG. 6 is referred to (step ST70).
6) In the case of 0, the read bank is incremented (step ST707), and in the case of 1, the read bank is not incremented (step ST708). That is, the read bank increment signal INC_RB
If ANK is 0, the next bank is selected as the bank from which the signal of the next frame is read. If it is 1, the bank from which the input video signal is read is continuously selected as the bank for writing the signal of the next frame. . In any case, the process returns to step ST702 to detect the head of the next frame, and thereafter, repeats the processing from step ST703.

Next, the overall operation of the frame rate converter 100 having such a configuration will be described. First, the input video signal is written into any of the first image memory 104 (bank A) to the third image memory 108 (bank B) by the input bank switch 102.
The write control circuit 11 determines which bank is to be written.
It is determined by the bank designation signal from the second. As described above with reference to FIG. 2, the write memory bank determines whether or not to increment the next memory bank to be written based on the input vertical synchronization signal and the output vertical synchronization signal. Are specified sequentially.

The read operation is almost the same as the write operation. The image signals written in the first image memory 104 (bank A) to the third image memory 108 (bank B) are output from the output bank switch 110 by appropriately selecting one of the banks. Which bank is read from is determined by a read bank designation signal from the read control circuit. The write memory bank is sequentially specified as described above by determining from the input vertical synchronization signal and the output vertical synchronization signal whether or not to increment the next memory bank to be written.

Such a frame rate conversion device 100
A more detailed operation of the first embodiment and a state where the frame rate conversion is actually performed will be described with reference to FIGS. The frame rate conversion includes down-rate conversion in which the output frame rate is lower than the input frame rate, up-rate conversion in which the output frame rate is higher than the input frame rate, and equal-size conversion in which the input frame rate and the output frame rate are the same. .
However, according to the frame rate conversion apparatus 100 of the present embodiment, any conversion can be handled without changing any parameters or algorithms.

FIG. 8 is a diagram showing the operation of "5 → 4 conversion" in which the frame rate is down-converted from 5 input frames to 4 output frames. FIG. 8A shows the write bank increment signal shown in FIG. The signal Q_write and the write bank increment signal INC_WBANK in the generation circuit 300 are represented by (B), the frame period of the input write video signal, the write set signal setW and the write reset signal reset in the write bank increment signal generation circuit 300 shown in FIG.
tC, (C) the frame period of the video signal to be read, set read signal setR and read reset signal resetR in the read bank increment signal generation circuit 600 shown in FIG. 6, and (D) the read shown in FIG. Bank increment signal generation circuit 600
And (E) show an access state to the first to third image memories 104 to 108, respectively.

As shown in FIGS. 8B and 8C, in the write bank increment signal generation circuit 300 and the read bank increment signal generation circuit 600 shown in FIGS. A write set signal setW and a read reset signal resetR signal are generated based on the synchronization signal, and a read set signal setR and a write reset signal resetW signal are generated in synchronization with a frame boundary of an output video signal, that is, a vertical synchronization signal. Then, based on these signals, as shown in FIGS. 8A and 8D, a signal Q_write indicating that the next bank of the write bank is not in the read state and the next bank of the read bank are set in the read state. Is generated, a signal Q_read is generated.

Further, these signals Q_write, Q
Based on _read, a write bank increment signal INC_WBANK (shown simply as INC in the figure) as shown in FIG. 8A and a read bank increment signal INC_RB as shown in FIG.
ANK (indicated simply by INC in the figure) is generated.
As a result, as shown in FIG. 8E, the write bank and the read bank of the video signal are controlled.

As shown in FIG. 8 (E), in most of the periods, both the write bank and the read bank are cyclically incremented, and the written video signals are sequentially read. However, during a period from the start of writing the frame i4 to the bank A to the end of writing, reading of one frame is not completed, and the write reset signal resetW signal is not generated. Therefore, the signal Q_write is maintained at a high level, and the write bank increment signal INC_WBANK is not valid in synchronization with the write set signal setW immediately before writing the frame i5.
Therefore, the write bank is not incremented, and the frame i5 is written to the same bank A as the frame i4. As a result, the video signal of frame i4 is erased. By repeating such an operation, frames are discarded at a rate of one frame for every five input frames.

As described above, the frame rate conversion device 10
At 0, in the case of such a down-rate conversion of the frame rate, the read bank is always incremented for each output frame, and the write bank stalls the increment of the bank in accordance with the frame rate ratio. Thus, the frame rate can be down-converted to a desired rate. Then, at this time, the write bank and the read bank as seen at a certain time always access different banks, so that memory overtaking does not occur.

FIG. 9 is a diagram showing the operation of “3 → 4 conversion” for up-conversion of the frame rate from three input frames to four output frames. Is the same as FIG. 8 described above. And
Also in the case of this up-conversion, as shown in FIG. 9E, in most of the periods, both the write bank and the read bank are cyclically incremented, and the written video signals are sequentially read.

However, during the period from the start of reading frame i-1 from bank B to the end of reading, writing for one frame has not been completed, and no read reset signal resetR signal has been generated. Therefore, the signal Q_read is maintained at the high level, and the read bank increment signal INC_RBANK is not valid in synchronization with the read set signal setR immediately before the next frame is read. Therefore, the read bank is not incremented, and the same bank B, that is, the frame i-
One video signal is read. This operation is performed for frame i
This is also performed at the time of readout of No. 2, and by repeating such an operation, a frame is added at a rate of one frame for every three input frames.

As described above, the frame rate converter 10
In the case of 0, in such an up-rate conversion of the frame rate, the write bank is always incremented for each input frame, and the read bank stalls the increment of the bank according to the frame rate ratio. Thus, the frame rate can be up-converted to a desired rate. Then, at this time, the write bank and the read bank at a certain time always access different banks, so that memory overtaking does not occur.

As described above, the frame rate conversion apparatus 100 of this embodiment has three frame memories and controls the write access bank and the read access bank at a certain time to be always different from each other.
The cause of overtaking between the write address and the read address has been eliminated. Therefore, desired frame rate conversion can be appropriately performed. This bank control does not require overtaking prediction and can be controlled only from the input vertical synchronizing signal and the output vertical synchronizing signal, so that the circuit configuration can be extremely simplified. As a result, a significant reduction in circuit cost can be realized as compared with the related art.

Further, it is not necessary to know in advance whether the frame rate conversion is up-rate conversion, down-rate conversion, or equal-rate conversion (no prediction is necessary). A response is possible. In addition, the operation of the frame rate conversion itself,
Even if the input / output image frames have a temporal initial phase shift, the output image does not break down, and the conversion ratio between the input frame and the output frame is not limited. Can do it.

Further, by combining the frame rate conversion device 100 of the present embodiment with a pixel number converter, an image format converter capable of converting to an arbitrary frame rate and an arbitrary number of pixels can be realized.

[0066]

As described above, according to the present invention, a non-interlaced video signal having a predetermined frame rate is converted into a non-interlaced video signal having an arbitrary phase at an arbitrary frame rate ratio with a simpler configuration. A rate conversion device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a frame rate conversion device according to an embodiment of the present invention.

FIG. 2 is a state transition diagram for explaining a method of selecting a bank in which an input video signal is written in a write control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 3 is a diagram illustrating a specific example of a circuit for generating a write bank increment signal INC_WBANK in a write control circuit of the frame rate conversion device illustrated in FIG. 1;

FIG. 4 is a flowchart for explaining a processing flow in a write control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 5 is a state transition diagram for explaining a method of selecting a bank from which a video signal to be output is read in the read control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 6 is a diagram showing a specific example of a circuit for generating a read bank increment signal INC_RBANK in the read control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 7 is a flowchart for explaining a processing flow in a read control circuit of the frame rate conversion device shown in FIG. 1;

FIG. 8 is a diagram for explaining an operation of “5 → 4 conversion” in which frame rate down conversion from five input frames to four output frames is performed in the frame rate conversion device shown in FIG. 1; is there.

FIG. 9 is a diagram for explaining an operation of “3 → 4 conversion” in which frame rate up conversion is performed from three input frames to four output frames in the frame rate conversion device shown in FIG. 1; is there.

FIG. 10 is a conceptual diagram illustrating the operation of a conventional frame rate conversion device.

FIG. 11 is a diagram for specifically explaining the operation of the frame rate conversion device shown in FIG. 10;

FIG. 12 is a diagram showing the state of input / output data and memory access when the write address overtakes the read address and when the read address overtakes the write address in the frame rate conversion device.

[Explanation of symbols]

100: frame rate converter, 102: input bank switcher, 104, 106, 108: image memory, 1
10: output bank switch 112: write control circuit 114: read control circuit 116: bank setting circuit 300: write bank increment signal generation circuit 301, 303, 309 D-flip-flop
302, 304: NOR element, 308: RS flip-flop, 600: Read bank increment signal generation circuit, 601, 603, 609 ... D flip-flop, 602, 604: NOR element, 608: RS flip-flop

Claims (8)

[Claims] 1. A first to third image memory means each having a storage capacity capable of storing a predetermined unit of image data and being cyclically arranged in a predetermined order, and a predetermined unit sequentially inputted When writing new image data to be written of the image data for each unit into the image memory unit, the image data is written in the image memory unit immediately before the predetermined unit, or the image data is written next to the image memory unit. Writing memory selecting means for selecting one of the image memory means, and the selected image memory means is provided with image data for each new predetermined unit to be written, based on a synchronization signal of the input image data. Means for writing image data to be written into the memory, and image data for each predetermined unit to be sequentially output from the image memory means. At the time of reading, the read memory selecting means for selecting any one of the image memory means that immediately before read out the image data of each predetermined unit or the image memory means to be ordered next to the image memory means, A frame rate conversion device comprising: image reading means for reading out the image data for each of the predetermined units stored in the image memory means based on a desired output synchronization signal. 2. The image memory device according to claim 1, wherein said write memory selecting means writes said immediately preceding image data for each predetermined unit when said image memory means to be ordered next is reading at least data. 2. The frame rate conversion device according to claim 1, wherein when the image data is not being read, the image memory means to be ordered next is selected. 3. The image memory according to claim 1, wherein said read memory selecting means reads said image data of a predetermined unit immediately before said next sequential image memory means at least when data is being written. 3. The frame rate conversion device according to claim 2, wherein a means is selected, and when writing is not being performed, the image memory means to be ordered next is selected. 4. The frame rate converter according to claim 3, wherein the image data for each predetermined unit is image data for each frame. 5. A writing memory selecting means for writing image data for each frame to an image memory means different from the image memory means from which the image reading means is performing reading. 5. The frame rate converter according to claim 4, wherein said image memory means is selected. 6. The image processing apparatus according to claim 1, wherein said write memory selecting means sets a signal indicating a frame boundary of image data for each frame which is sequentially input and written to said image memory means, as a set signal, and sequentially reads out image data for each frame from said image memory means. When the signal indicating the relationship between the writing and the reading in which the signal indicating the boundary of the frame of the data is the reset signal is in the predetermined first state, the image memory means which has written the image data of the predetermined unit immediately before the first state. 6. The frame rate conversion device according to claim 5, wherein said selecting step selects said next ordered image memory means when said signal is in a predetermined second state. 7. The read memory selecting means, wherein the image data for each frame is read from image memory means different from the image memory means to which the image writing means has performed writing. 5. The frame rate converter according to claim 4, wherein said memory means is selected. 8. A read-out memory selecting means, wherein a reset signal is a signal indicating a frame boundary of image data of each frame which is sequentially inputted and written into the image memory means, and the image-by-frame image read out sequentially from the image memory means. When the signal indicating the relationship between the writing and the reading in which the signal indicating the boundary of the data frame is the set signal is in the predetermined first state, the image memory means which has read the image data of the predetermined unit immediately before is selected. 8. The frame rate conversion device according to claim 7, wherein said image memory means to be ordered next is selected in a predetermined second state.