JP2000278519A - Image enlarging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image enlarging device capable of enlarging images at a low cost in an image display device provided with a frame memory for double frame conversion. SOLUTION: The frame memory 4 for the double frame conversion performs output as the image data of parallel two phases so as to double the number of the frames per unit time of image data and a storage circuit 5 tentatively stores the image data of the two phases. A selection circuit 6 appropriately selects data from the image data of the two phases outputted from the frame memory 4 for the double frame conversion and the image data of the two phases outputted from the storage circuit 5 and outputs them as the two sets of the image data of the two phases. An enlarging interpolation circuit 3 enlarges the image data of the two phases and outputs them as the image data of the two phases.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image enlarging apparatus for enlarging a digital video image.

[0002]

2. Description of the Related Art In an image display device such as a television receiver or a projector, an image enlargement / reduction device is used to display an image in an enlarged or reduced size. A general image scaling device is, as shown in FIG.
A reduction interpolation circuit 1 is provided in a stage preceding the frame memory 2, and an enlargement interpolation circuit 3 is provided in a stage subsequent to the frame memory 2.

Some image display devices have a frame memory different from the frame memory of the image enlargement / reduction device. One example is a liquid crystal projector. In a liquid crystal projector, it is necessary to drive the liquid crystal panel with an alternating current in order to prevent burn-in of the liquid crystal panel, and the polarity of the video signal may be inverted for each frame. In this case, flicker of the displayed image causes a problem. Therefore, the number of frames per unit time is doubled by using a frame memory for double frame conversion so that flicker does not become a problem.

FIG. 4 shows a configuration in a case where an image enlargement / reduction device shown in FIG. 3 is provided in an image display device provided with a frame memory for double frame conversion. In FIG. 4, the output of the enlargement interpolation circuit 3 is input to a frame memory 4 for double frame conversion. Frame memory 4 for double frame conversion
Is output as parallel two-phase image data in order to double the number of frames per unit time of the input image data. When the pixels of the frame output from the enlargement interpolation circuit 3 are 1, 2, 3, 4,... In order, the pixels 1, 3, 5,.
However, from the lower phase in the figure, the pixels 2, 4, 6,... Are output in pairs as pixels (1, 2, 3), (3, 4), (5, 6).

[0005]

As shown in FIG. 4, when an image display device provided with a frame memory 4 for double frame conversion is provided with an image enlargement / reduction device, the image display device has two frame memories. However, the circuit scale becomes large, and it is difficult to realize the circuit at low cost.
In the above example, the image enlarging / reducing device in which the reduction interpolating circuit 1 is provided in the preceding stage of the frame memory 2 has been described.
The same applies to an image enlargement apparatus that does not have the reduction interpolation circuit 1 but only enlarges an image. Also, in the above example,
Although the case where the frame memory for double frame conversion 4 outputs as parallel two-phase image data in order to double the number of frames has been described, there may be a case where the frame memory 4 outputs more multi-phase image data.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and an image display apparatus having a frame memory for double frame conversion for increasing the number of frames is provided.
It is an object of the present invention to provide an image enlargement device capable of realizing image enlargement at a low cost by reducing a frame memory.

[0007]

SUMMARY OF THE INVENTION According to the present invention, there is provided an image enlarging apparatus for enlarging an image, in which the number of frames per unit time of input image data is increased. A frame memory for double-frame conversion (4) for outputting as parallel multi-phase image data, and at least one storage circuit (5) for temporarily storing the multi-phase image data output from the frame memory for double-frame conversion. ), And multi-phase image data output from the frame memory for double frame conversion and multi-phase image data output from the storage circuit, and the input data is selected to select the multi-phase image data. A selection circuit (6) that outputs the multi-phase image data output from the selection circuit and outputs the multi-phase image data as multi-phase image data. There is provided an image enlarging apparatus characterized by being configured with an interpolation circuit (3).

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image enlargement device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of the image enlargement device of the present invention, and FIG. 2 is a diagram for explaining the principle of the enlargement operation by the image enlargement device of the present invention.

In this embodiment, an image enlargement / reduction device will be described as an image enlargement device. In this embodiment, a case is shown in which the frame memory for double frame conversion 4 outputs as parallel two-phase image data in order to double the number of frames per unit time. In FIG. 1, a reduction interpolation circuit 1 is provided in a stage preceding the frame memory 4 for double frame conversion. As shown in FIG. 4, when the double-frame conversion frame memory 4 is used merely for doubling the number of frames per unit time, the double-frame conversion frame memory 4 includes a write enable WE and a read enable WE. It is not necessary to supply the RE to execute the enable processing for each pixel.

In the present invention, the frame memory 4 for double frame conversion is used as a frame memory for time axis conversion for enlarging (or reducing) an image instead of the frame memory 2 in FIGS. Therefore, the write enable WE and the read enable RE are supplied from the control circuit 10 to the frame memory 4 for double frame conversion, and the enable process is executed in pixel units. Note that the control circuit 10 controls the reduction interpolation circuit 1 and the expansion interpolation circuit 3 when supplying a clock to each section of the circuit or changing the reduction ratio or the enlargement ratio, but these are not shown here. ing.

When the image is reduced, the following operation is performed. The reduction interpolation circuit 1 performs predetermined filtering based on the reduction ratio on the input digital video image data to generate reduced data, or invalidates the write enable WE from the control circuit 10 to perform double frame conversion. By stopping the writing of data to the frame memory 4, the image is reduced. Note that, when only the image is enlarged without being reduced, the reduction interpolation circuit 1 does not operate, and the double frame conversion frame memory 4 writes the input data as it is. Alternatively, the reduction interpolation circuit 1 may not be provided.

From the two phases which are the outputs of the frame memory 4 for double frame conversion, pixels are output as a pair as described above. In the present invention, a storage circuit 5 for temporarily storing output data of the double frame conversion frame memory 4 and a selection circuit 6 are provided between the double frame conversion frame memory 4 and the enlargement interpolation circuit 3. By providing the storage circuit 5 and the selection circuit 6, the enlargement interpolation circuit 3
The data is supplied as it is in a plurality of phases, and the enlargement interpolation circuit 3 can directly perform the enlargement processing on the data in the plurality of phases. In addition, from the output of the double frame conversion frame memory 4 to the output of the enlargement interpolation circuit 3, all operate at the same clock frequency. In the present embodiment, the double-frame conversion frame memory 4 outputs two-phase image data. For example, since bilinear interpolation is used, four-phase image data is supplied to the enlargement interpolation circuit 3. The phase of the image data output from the selection circuit 6 differs depending on the interpolation method.

Here, referring to FIG.
However, the principle by which enlargement processing can be directly performed on data of a plurality of phases will be described. FIG. 2 shows the case of two phases, but the principle is the same in other plural phases. FIG. 2 shows the operation of 5/3 times as an example. In FIG. 2, (A) shows the principle for multiplying the data by 5/3. The upper part shows input data, and the lower part shows output data. Here, the simplest (bilinear interpolation) two-point interpolation is shown. Since five output data are obtained for three input data, the input data is sequentially denoted by i1, i2, i3, i1 ', i2', i3 ',
i1 "..., and output data in order of o1, o2, o3, o
4, o5, o1 ', o2', o3 ', o4', o5 ',
o1 "...

FIG. 2B shows from which input data the one-phase output data o1, o2, o3... Shown in the lower part of FIG. 2A are obtained. As shown in FIG. 2A, for example, output data o1 and o2 are generated from input data i1 and i2, and output data o3 and o4 are
Generated from input data i2, i3. As described above,
From the double frame conversion frame memory 4, the pixels are output in pairs. Frame memory 4 for double frame conversion
Are two-phase data as shown in FIG. In FIG. 2B, the upper data corresponds to data from the upper phase in the figure of the double frame conversion frame memory 4, and the lower data corresponds to data from the lower phase in the figure. However, as described later, the two-phase data shown in FIG. 2B is not used as it is.

Since the pixels are also output as a pair from the enlargement interpolation circuit 3, the enlargement interpolation circuit 3 outputs
(A) As shown in the lower part of FIG.
Two-phase data as shown in (D) must be output. In FIG. 2D, the upper data corresponds to the data from the upper phase in the drawing of the enlargement interpolation circuit 3, and the lower data corresponds to the data from the lower phase in the drawing.

For example, to obtain the output data o1, FIG.
As shown in FIG. 2B, two-phase input data i1 and i2 are required. To obtain output data o2, two-phase input data i1 and i2 are required as shown in FIG. 2B. That is, to obtain two-phase output data o1 and o2,
As indicated by the arrows, two-phase input data i1, i2
Is required. That is, FIG.
2D required to obtain the two-phase output data shown in FIG.
The set of input data for a phase is shown.

Next, FIG.
To obtain two-phase output data shown in (D), a new
Indicates which input data is required. For example,
Consider two-phase output data o3 and o4 shown in FIG. In order to obtain two-phase output data o3 and o4, FIG.
As shown in (C), input data i2 and i3 are required. Among them, the input data i2 has already been used as the two-phase input data i1 and i2 at the previous timing (that is, one clock before), so it is not necessary to newly read out the data here. The data used at the previous timing may be held. On the other hand, input data i3
Is the data that is required for the first time when obtaining the two-phase output data o3 and o4, so it is necessary to newly read out the data here. Since the input data is paired in two phases, the data to be newly read out is two-phase input data i3, i1 'as shown in FIG.

Further, in order to obtain two-phase output data o5 and o1 'shown in FIG. 2D, input data i3, i1' and i2 'are required as shown in FIG. 2C. . Among them, the input data i3 is data that has already been used at the immediately preceding timing (that is, one clock before), and the input data i1 ′ is the output data o3
o4 to obtain the two-phase input data i3
It is the input data i2 'that needs to be newly read out because it is included in i1'. Since input data is paired in two phases, data to be newly read out is two-phase input data i2'i3 'as shown in FIG.

Based on such a concept, data newly required at the timing to obtain the two-phase output data shown in FIG. 2D is as shown in FIG. 2E. In FIG. 2E, a blank indicates that it is not necessary to newly read data at that timing, and that data used at one or more previous timings may be used.

To summarize the above operation, in order to obtain a two-phase output data by enlarging using two-phase input data,
It can be seen that the relationship shown in FIG. Also in FIG. 2F, a blank indicates that it is not necessary to newly read data at that timing, and that data used at one or more previous timings may be used. As can be seen from FIG. 2 (F), the two-phase input data necessary for obtaining the two-phase output data output at a constant rate is read from the double frame conversion frame memory 4 at a constant timing. It is necessary to temporarily store the read data and supply it to the enlargement interpolation circuit 3 instead of supplying the data to the enlargement interpolation circuit 3. In addition, as shown in FIG.
It is necessary to appropriately select the input data of the phase and supply it to the enlargement interpolation circuit 3. The storage circuit 5 and the selection circuit 6 in FIG. 1 are required for this.

Returning again to FIG. 1, the operation of the enlargement processing after the double frame conversion frame memory 4 will be described. A read enable RE is supplied from the control circuit 10 to the double frame conversion frame memory 4 to control data reading. As described above, the read enable RE is enabled when new data is read at a certain timing, and the read enable RE is disabled when new data is not read at a certain timing.

The two-phase data read from the double frame conversion frame memory 4 is input to the storage circuit 5. The storage circuit 5 includes, for example, three cascade-connected D flip-flops 51, 52, and 53. How many D flip flips are provided depends on the enlargement ratio and how many types of enlargement ratios are realized. That is, since the number of D flip flips is appropriately set depending on the enlargement ratio and how many types of enlargement ratios are realized, the number is one or more.

Further, since the storage circuit 5 is for temporarily storing input data, the storage circuit 5 is not limited to the D flip-flip which is a register, but may be a memory such as a buffer. . In FIG. 1, the D flip flips 51 to 53 are shown as one block for convenience, but a D flip flip is actually provided for each phase.

The two-phase data read from the double frame conversion frame memory 4 and the D flip flips 51 to
The two-phase data stored and delayed by 53 are input to the selection circuit 6. The selection control signal SEL is input from the control circuit 10 to the selection circuit 6, and the selection circuit 6
Is used to select the input data as appropriate and expand the interpolation circuit 3
To enter. The selection circuit 6 may select the two-phase data from the double frame conversion frame memory 4 and the D flip-flops 51 to 53 as a pair and input the pair to the enlargement interpolation circuit 3, or may select one of the two-phase data 1 One of the two data may be selected, and one of the other two-phase data may be selected and input to the enlarged interpolation circuit 3 as new two-phase data. The selection circuit 6 appropriately selects the input data according to the enlargement ratio. In the present embodiment, the output of the selection circuit 6 is
As described in (C), two sets of two-phase data (ie, 4
Phase).

The two sets of two-phase data thus selected are input to the enlargement interpolation circuit 3. The upper part of FIG. 2F is an example of two-phase data output from the frame memory 4 for double frame conversion. The enlargement interpolation circuit 3 performs predetermined filtering based on the enlargement ratio on the input two sets of two-phase data to generate enlarged data. Here, for convenience, the enlargement interpolation circuit 3 is shown as one block, but actually, a circuit (for example, an interpolation filter) that performs enlargement processing on one set of data in two sets of two-phase data And a circuit (for example, an interpolation filter) for performing an enlargement process on the other set of data. Then, from the enlargement interpolation circuit 3, as shown in the lower part of FIG.
The expanded two-phase data is output.

As described above, according to the image enlargement apparatus of the present invention, in the image display device provided with the frame memory 4 for double frame conversion, the frame memory 4 for double frame conversion is converted into a time axis for image enlargement. Can be used as a frame memory. Moreover, the multi-phase image data output from the double frame conversion frame memory 4 can be directly expanded. Therefore, the circuit scale can be significantly reduced. When the image is enlarged in the vertical direction by the image enlargement device after the image is enlarged in the horizontal direction by the image enlargement device of the present invention, the capacity of the line memory in the image enlargement device in the vertical direction can be reduced. In the case of two-phase output, the capacity of the line memory is halved.

[0027]

As described above in detail, the image enlarging apparatus according to the present invention increases the number of frames of input image data per unit time, so that double frame conversion is output as parallel multi-phase image data. Frame memory for
At least one storage circuit for temporarily storing the multi-phase image data output from the double frame conversion frame memory, and the multi-phase image data output from the double frame conversion frame memory and output from the storage circuit. And a selection circuit for selecting the input data and outputting the input data as the multi-phase image data, and expanding the multi-phase image data output from the selection circuit to generate the multi-phase image data. Since the image processing apparatus is provided with the enlargement interpolation circuit that outputs the data, the image can be enlarged at low cost by reducing the frame memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the principle of the enlargement operation according to the present invention.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a block diagram showing another conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reduction interpolation circuit 3 enlargement interpolation circuit 4 frame memory for multiplication frame conversion 5 storage circuit 6 selection circuit 10 control circuit 51 to 53 D flip-flop

Claims (1)

[Claims] 1. An image enlarging apparatus for enlarging an image, comprising: a frame memory for double frame conversion for outputting parallel multi-phase image data in order to increase the number of frames of input image data per unit time; At least one storage circuit for temporarily storing the multi-phase image data output from the frame memory for frame conversion; and the multi-phase image data output from the frame memory for double frame conversion and output from the storage circuit. A multi-phase image data, and a selection circuit that selects these input data and outputs the multi-phase image data as a multi-phase image data. An image enlargement device comprising: an enlargement interpolation circuit that outputs as image data.