JPH0944117A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device capable of easily realizing the double magnification of image data in the horizontal direction. SOLUTION: A setting means 2 discriminates the resolution of image data 1 from horizontal and vertical synchronizing signals H and V, supplies a control signal 21 to a clock circuit 3 and decides by this control signal whether two kinds of clocks supplied to an odd number pixel sampling circuit 41 and an even number pixel sampling circuit 42 are selected from second clocks OCLK 2 and ECLK2 each having the same frequency as that of a dot clock DCLK and the same phase as that of another or first clocks OCLK1 and ECLK1 each having a frecpency half that of the clot clock DCLK and having a phase reverse to that of another.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, such as a liquid crystal display device, which displays image data by sampling a plurality of pixels, and controls a sampling clock.
In particular, the present invention relates to an image display device that doubles an image in the horizontal direction.

[0002]

2. Description of the Related Art A conventional image display device (not shown), for example, a liquid crystal display device needs to sample image data for one line, and if it is composed of N pixels in the horizontal direction, it has N pixels. Image data for one minute is held, sampling is performed N times for each line, and I
Because of the performance of C, sampling is performed at a frequency that is a fraction of the actual dot clock, so the sampling circuit is divided into a plurality of blocks and time division is performed.

However, the method of supplying the sampling clock to these sampling circuits is fixed regardless of the resolution of the image, and even when only half of the image data for one line, that is, two pixels of N pixels are displayed. The sampling operation had to be performed N times.

[0004]

As described above, it is necessary to sample the image data of two pixels in the cycle of one pixel, and the sampling is performed with a clock twice as fast as the original dot clock frequency. However, since the sampling data for two times for one pixel must have the same value, sampling must be performed at a point where the image data does not change during the period of one cycle of the twice high speed clock.

This corresponds to points A and C shown in FIG. 3, but at such a sampling point, the image data D is unstable because it is close to the changing period of the image data D. Sampling may not be performed normally and a stable display image may not be obtained.

Therefore, an object of the present invention is to provide an image display device for stably sampling image data of two pixels in a cycle of one pixel.

[0007]

In order to solve the above-mentioned problems, an image display device of the present invention provides image data output based on a horizontal synchronizing signal and a vertical synchronizing signal, and a horizontal synchronizing signal of this image data. And setting means for detecting the resolution by the vertical synchronizing signal and setting whether to display the same size or double size display, the first clock having a half frequency of the dot clock when the same size display is set by the setting means, A clock circuit that generates a second clock having the same frequency as the dot clock when the display unit sets the double display, and an odd number of the image data based on the first clock and the second clock generated by the clock circuit. An odd pixel sampling circuit for sampling pixels and an even image of the image data based on the first clock and the second clock generated by the clock circuit. An even pixel sampling circuit, a display means for displaying the image data sampled by the even pixel sampling circuit and the odd pixel sampling circuit, and the odd pixel sampling circuit for displaying the image data on the display means. And a control means for controlling the even pixel sampling circuit.

In order to solve the above-mentioned problems, the image display device of the present invention is provided with a digital circuit for digitally converting the above-mentioned image data. It is characterized in that sampling is performed by a circuit and an even pixel sampling circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an image display device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram (A) of an image display device according to an embodiment of the present invention, a time chart (B) of a normal display and a time chart (C) of a double display.

FIG. 2 is a block diagram of a clock circuit of an image display device according to an embodiment of the present invention.

An image display device according to an embodiment of the present invention is
As shown in FIG. 1A, the resolution is detected by the image data 1 output based on the horizontal synchronizing signal H and the vertical synchronizing signal V, and the horizontal synchronizing signal H and the vertical synchronizing signal V of this image data 1. , And setting means 2 for setting whether to display at the same size or twice, the first clocks OCLK1 and ECLK1 having half the frequency of the dot clock DCLK when the display at the same size is set by the setting means 2, and the setting means 2. The clock circuit 3 for generating the second clocks OCLK2, ECLK2 having the same frequency as the dot clock DCLK when the double display is set, and the first clocks OCLK1, ECLK1 and the second clock O generated by the clock circuit 3.
An odd pixel sampling circuit 41 for sampling odd pixels of the image data 1 based on CLK2, ECLK2, and a first clock OCLK1, E generated by the clock circuit 3.
An even pixel sampling circuit 42 for sampling even pixels of the image data 1 based on CLK1 and the second clocks OCLK2, ECLK2, and the even pixel sampling circuit 4
2 and the display means 6 for displaying the image data 1 sampled by the odd pixel sampling circuit 41, and the display means 6
To display image data 1 on the odd pixel sampling circuit 4
Control means 5 for controlling the 1 and even pixel sampling circuits 42
It is composed of

In the operation of the image display device according to the embodiment of the present invention, as shown in FIG. 1A, the odd pixel sampling circuit 41 and the even pixel sampling circuit 42 are operated by the clock circuit 3.
The image data 1 is held at the rising edges of the clocks OCLK and ECLK of the dot clock DCLK, and the clock circuit 3 outputs the dot clock DCLK to the frequency dividing circuit 31 as shown in FIG.
The control signal 21 output from the setting means 2 is input to the selection circuit 32 and the inverting circuit 33, respectively, and the dot clock DCLK is converted into a half frequency, and the selection circuit 32 has the same frequency as the dot clock DCLK by the control signal 21. 2nd clocks OCLK2, ECLK2 or a first clock OCLK having a frequency half that of the dot clock DCLK
1, ECLK1 is output, and the inversion circuit 33 controls inversion / non-inversion of the clock ECLK to the even pixel sample circuit 42 by the control signal 21.

As for the clocks OCLK and ECLK output from the clock circuit 3, the output of the clock circuit 3 becomes "H" level when displaying at the same size, and the first clock OCL is output.
When K1 and ECLK1 are transmitted and the double display is performed, the output of the clock circuit 3 becomes "L" level and the second clock O
Send out CLK2 and ECLK2.

Therefore, in the case of the equal size display in which the output of the clock circuit 3 becomes "H" level, the first clock ECLK1
Is the dot clock DCL, as shown in FIG.
The frequency is half that of K and the phase is opposite to that of the first clock OCLK1.

Further, in the case of double display in which the output of the clock circuit 3 becomes "L" level, the second clock ECLK2 is
As shown in (C) of FIG. 2, the dot clock DCLK has the same frequency as the second clock OCLK2 and the same phase,
The same image data 1 is sampled in adjacent pixels and displayed twice in the horizontal direction.

The image display device according to one embodiment of the present invention includes a digital circuit for digitally converting the image data 1. After the digital conversion of the image data 1 by this digital circuit, the odd pixel sampling circuit 41 and the even pixel sampling circuit are used. The circuit 42 may perform sampling.

[0018]

As described above, according to the image display device of the present invention, when the image data for two pixels is sampled at the cycle of one pixel, the image data during the display period of one pixel does not change. Sampling can be performed for a period of time, which has the effect of obtaining stable image data.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an image display device according to an embodiment of the present invention (A), a time chart (1), and a time chart (B) for equal-size display
It is a time chart (C) of double display.

FIG. 2 is a configuration diagram of a clock circuit of the image display device according to the embodiment of the present invention.

FIG. 3 is a time chart of image data by a conventional image display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 image data 2 setting means 3 clock circuit 5 control means 6 display means 21 setting means (control signal) 31 frequency dividing circuit 32 selection circuit 33 inversion circuit 41 odd pixel sampling circuit 42 even pixel sampling circuit OCLK1, ECLK1 first clock OCLK2 ECLK2 Second clock

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 7/30 H04N 7/133 Z

Claims (2)

[Claims] 1. Image data output based on a horizontal synchronizing signal and a vertical synchronizing signal, and a resolution is detected by the horizontal synchronizing signal and the vertical synchronizing signal of this image data, and the display is set to equal size display or double size display. Setting means, a first clock having a half frequency of the dot clock when the display is set to the same size display, and a second clock having the same frequency as the dot clock when the display is set to double display by the setting means. A clock circuit that generates an odd pixel of the image data based on the first clock and the second clock generated by the clock circuit, the first clock generated by the clock circuit, An even pixel sampling circuit for sampling an even pixel of the image data based on a second clock, and the even pixel sampling circuit And display means for displaying the image data sampled by the odd pixel sampling circuit, and control means for controlling the odd pixel sampling circuit and the even pixel sampling circuit so as to display the image data on the display means. An image display device characterized by the above. 2. A digital circuit for digitally converting the image data, wherein the digital data is digitally converted by the digital circuit, and then sampled by the odd pixel sample circuit and the even pixel sample circuit. The image display device described.