JPH08140019A - Picture display device - Google Patents

Abstract

PURPOSE: To display various kinds of video signals on a liquid crystal panel with simple circuit constitution by changing the frequency of reference clock signals in a PLL circuit corresponding to the inputted video signals in an oscillation frequency control circuit, inputting to a liquid crystal panel control signal generation circuit and generating respective timing signals corresponding to the inputted video signals. CONSTITUTION: This device is provided with only a PLL circuit 2 for generating the reference clock signals in synchronism with the horizontal synchronizing signals of the video signals, the oscillation frequency control circuit 4 for controlling the frequency of the reference clock signals generated in the PLL circuit 2 and the liquid crystal panel control signal generation circuit 6 for generating the respective timing signals required for displaying pictures on the liquid crystal panel 10. The frequency of the reference clock signals generated in the PLL circuit 2 is changed corresponding to the inputted video signals in the oscillation frequency control circuit 4, and inputted to the liquid crystal panel control signal generation circuit 6, the respective timing signals corresponding to the inputted video signals are generated and the video signals are displayed on the liquid crystal panel 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying video signals on a liquid crystal panel such as a television and a computer.

[0002]

2. Description of the Related Art In recent years, as computer equipment has become more sophisticated, image display equipment for displaying the video signal has also become more sophisticated. Among them, there is an increasing demand for image display devices capable of displaying video signals of various frequencies, so-called multi-scan image display devices. As a conventional image display device, a cathode ray tube (Cathode Ray T
The image display device using a Cube (hereinafter referred to as “CRT”) is mainly used, but CR is used because the CRT is used for the image display unit.
There was a limit to the miniaturization of the device due to the physical limitation of T and the like.
An image display device using a liquid crystal panel as an image display unit has been proposed in order to remove this limitation and reduce the size of the device.

FIG. 3 is a block diagram showing the configuration of an example of a multi-scan type image display device using a liquid crystal panel.

In the image display device shown in FIG. 3, the scanning frequency conversion circuit 26 is used to display video signals of various frequencies on the liquid crystal panel 10. The scanning frequency conversion circuit 26 is a circuit that converts a video signal of various scanning frequencies into a constant scanning frequency, and is generally composed of an analog-digital conversion circuit, a memory circuit, and a digital-analog conversion circuit (all are not shown). No).

The video signal is input to the scanning frequency conversion circuit 26 and the sync separation circuit 1, and the horizontal sync signal (HD) and the vertical sync signal (VD) are separated from the video signal. The synchronization signal is input to the first PLL circuit 21 and generates a first reference clock signal synchronized with the synchronization signal.
The oscillation frequency of the first reference clock signal changes according to the frequency of the synchronization signal. The first reference clock signal is input to the write control signal generation circuit 22, and the scanning frequency conversion circuit 26 digitally converts the video signal to generate a write control signal for writing in the memory circuit.

The second PLL circuit 23 reads data from the memory circuit and generates a second reference clock signal for generating a signal for controlling the liquid crystal panel 10.
Unlike the first reference clock signal, the second reference clock signal is a signal having a constant oscillation frequency even if the frequency of the synchronization signal changes. The second reference clock signal is a read control signal generation circuit 24 and a liquid crystal panel control signal generation circuit 25.
Is input to In the read control signal generation circuit 24, a read control signal for reading data from the memory circuit in the scanning frequency conversion circuit 26 and converting the data into an analog signal to generate an analog video signal is generated. The liquid crystal panel control signal generation circuit 25 generates a control signal for displaying a video signal on the liquid crystal panel 10 based on the second reference clock signal.

The control signal includes a vertical scanning start signal for controlling the start of vertical scanning of the liquid crystal panel 10, a vertical scanning clock signal for performing vertical scanning, and a start of horizontal scanning. Horizontal scanning start signal for
There is a horizontal scan clock signal for performing horizontal scanning (neither signal is shown). The video signal input to the liquid crystal panel 10 is sampled at a timing synchronized with the horizontal scanning clock signal and displayed on each pixel of the liquid crystal panel 10.

FIG. 4 is a timing chart for explaining the operation of the scanning frequency conversion circuit 26. The write control signal generated by the write control signal generation circuit 22 is a signal synchronized with the synchronizing signal of the input video signal, and the transmission frequency is made to match the frequency of the dot clock signal of the video signal. Then, analog-digital conversion is performed at the timing of the dot clock signal of the video signal, and the data is written in the memory circuit. On the other hand, the read control signal generated by the read control signal generation circuit 24 is
It is a signal of a constant frequency that does not depend on the frequency of the synchronizing signal of the input video signal or the frequency of the dot clock signal.
Then, since the data of the memory circuit is read at this constant frequency and the digital-analog conversion is performed, the video signal output from the scanning frequency conversion circuit 26 has a constant scanning frequency regardless of the scanning frequency of the original video signal. Become.

As described above, by converting the scanning frequency of the video signal into a constant frequency, the video signals of various scanning frequencies can be displayed on the liquid crystal panel 10.

[0010]

However, in the image display device shown as an example of the conventional technique, the scanning frequency conversion circuit is used to display the video signal on the liquid crystal panel,
In addition, there is a problem that two sets of PLL circuits are required.

The present invention has been made in view of the above circumstances, and is an image display device for displaying a video signal on a liquid crystal panel, such as a television or a computer, which has a simple circuit configuration without using a scanning frequency conversion circuit. Is intended to provide.

[0012]

In order to solve the above problems, the present invention is the only PLL in an image display device using a liquid crystal panel that generates a reference clock signal in synchronization with a horizontal synchronizing signal of a video signal. A circuit, an oscillation frequency control circuit for controlling the frequency of the reference clock signal generated in the PLL circuit, and a liquid crystal panel control signal generation circuit for generating each timing signal necessary for displaying an image on the liquid crystal panel. Then, the frequency of the reference clock signal generated by the PLL circuit is changed by the oscillation frequency control circuit in accordance with the input video signal and is input to the liquid crystal panel control signal generation circuit. The video signal is displayed on the liquid crystal panel by generating the timing signal.

[0013]

With the above-described structure, the present invention can simplify the circuit structure and reduce the cost in an image display device for displaying a video signal on a liquid crystal panel such as a television or a computer.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image display apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the arrangement of an image display device according to an embodiment of the present invention. In FIG. 1, 1
Is a sync separation circuit that separates a horizontal sync signal (HD) and a vertical sync signal (VD) from a video signal, 2 is a PLL circuit that generates a reference clock signal that is synchronized with the sync signal, and 3 is a sync separation circuit 1. The video signal mode determination circuit 4 for determining the scanning frequency of the video signal input from the horizontal synchronization signal and the vertical synchronization signal, 4 controls the frequency division ratio of the PLL circuit 4 by the control signal from the video signal mode determination circuit 3. And an oscillation frequency control circuit 5 for controlling the oscillation frequency of the reference clock signal transmitted by the PLL circuit 4.
A waveform shaping circuit that corrects the phases of the horizontal synchronizing signal and the vertical synchronizing signal in accordance with the reference clock signal, and 6 is a liquid crystal panel control signal generating circuit that generates a control signal for displaying a video signal on the liquid crystal panel 10.

The operation of the image display device having the above structure will be described below. The video signal mode determination circuit 3
By using a clock signal (not shown) having a constant oscillation frequency different from the reference clock signal oscillated by the PLL circuit 2,
The period of the horizontal synchronizing signal and the vertical synchronizing signal is measured to determine the type of the input video signal. Then, a control signal indicating the type of video signal is sent to the oscillation frequency control circuit 4.

When the oscillation frequency control circuit 4 receives the control signal from the video signal mode determination circuit 3, it sets the frequency division ratio of the PLL circuit 2 according to preset data. As a result, the PLL circuit 2 oscillates the reference clock signal according to the type of the input video signal.

The horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) separated from the video signal by the sync separation circuit 1 are input to the waveform shaping circuit 5, where the phase and the reference clock signal oscillated by the PLL circuit 2 are set. The waveform is modified so that The liquid crystal panel control signal generation circuit 6 includes a waveform shaping circuit 5
The horizontal scanning start signal and the horizontal scanning necessary to drive the liquid crystal panel 10 based on the horizontal synchronizing signal (HD ′) and the vertical synchronizing signal (VD ′) whose phases are adjusted by the reference clock signal oscillated by the PLL circuit 2. Control signals such as a clock signal, a vertical scanning start signal, and a vertical scanning clock signal (none of which are shown) are generated.

In the embodiment, the type of the input video signal is automatically determined by the video signal mode determination circuit 3, but it is determined by the user and the oscillation frequency control circuit 4 is manually operated. You may make settings.

FIG. 2 is a timing chart for explaining the relationship between the scanning frequency of the video signal and the horizontal scanning clock signal in order to explain the operation of the image display device of the present invention when the scanning frequency of the video signal is different.

FIG. 2A is a timing chart when a video signal having a horizontal scanning frequency of fa and a horizontal pixel number of 640 dots is input. In this case, when the video signal mode determination circuit 3 determines that the input video signal has a horizontal scanning frequency of fa and the number of pixels in the horizontal direction is 640 dots, the oscillation frequency of the PLL circuit 2 is set to this video signal. In order to set the frequency according to the above, a control signal is sent to the oscillation frequency control circuit 4 to set the frequency division ratio of the PLL circuit 2.

By setting the oscillation frequency of the PLL circuit 2 to a frequency corresponding to the input video signal, the control signal of the liquid crystal panel 10 generated by the liquid crystal panel control signal generation circuit 6 also corresponds to the video signal, In the case of FIG. 2A, the horizontal scanning clock signal serving as a reference for sampling the video signal for displaying an image on the liquid crystal panel 10 has a period t so that it becomes 640 clocks during the video period.
It becomes a signal that is a.

Therefore, since the video signal is sampled 640 times, which is the same as the number of dots during the video period, all the dots can be displayed when the number of pixels in the horizontal direction of the liquid crystal panel 10 is 640 dots.

On the other hand, in FIG. 2B, the horizontal scanning frequency is fb.
3 is a timing diagram when a video signal having 640 dots in the horizontal direction is input. In this case, when the video signal mode determination circuit 3 determines that the input video signal has a horizontal scanning frequency of fb and the number of pixels in the horizontal direction is 640 dots, the frequency division ratio of the PLL circuit 2 is changed to PL.
Since the oscillation frequency of the L circuit 2 is set to the frequency corresponding to this video signal, the control signal of the liquid crystal panel 10 generated by the liquid crystal panel control signal generation circuit 6 also corresponds to the video signal, and the horizontal scanning clock signal is cycled. Becomes tb.

In this case as well, since the video signal is sampled 640 times, which is the same as the number of dots during the video period, all the dots can be displayed when the number of horizontal pixels of the liquid crystal panel 10 is 640 dots.

As described above, in the embodiment of the present invention, in the image display device using the liquid crystal panel, the division ratio of the PLL circuit is switched according to the type of the input video signal to change the reference clock signal. It is possible to display various types of video signals on the liquid crystal panel by controlling the oscillation frequency of the liquid crystal panel and controlling the frequency of the control signal of the liquid crystal panel generated by the liquid crystal panel control signal generating circuit.

[0027]

As described above, according to the present invention, in an image display device for displaying a video signal on a liquid crystal panel such as a television or a computer, a reference clock signal is generated in synchronization with a horizontal synchronizing signal of the video signal. A unique PLL circuit, an oscillation frequency control circuit for controlling the frequency of the reference clock signal generated by the PLL circuit, and a liquid crystal panel control signal generation for generating each timing signal necessary for displaying an image on the liquid crystal panel. The oscillation frequency control circuit according to the input video signal.
By changing the frequency of the reference clock signal generated in the circuit and inputting it to the liquid crystal panel control signal generating circuit, and generating each timing signal according to the input video signal, the video signal of the television or computer etc. The above-mentioned configuration has an excellent effect that various types of video signals can be displayed on the liquid crystal panel with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image display device according to an embodiment of the present invention.

FIG. 2 is a timing diagram illustrating a relationship between a scanning frequency of a video signal and a horizontal scanning clock signal for explaining the operation of the image display device of the present invention.

FIG. 3 is a block diagram showing a configuration of an example of an image display device using a conventional liquid crystal panel.

FIG. 4 is a timing chart for explaining the operation of the scanning frequency conversion circuit of the conventional image display device.

[Explanation of symbols]

 1 Sync separation circuit 2 PLL circuit 3 Video signal mode determination circuit 4 Oscillation frequency control circuit 5 Waveform shaping circuit 6 Liquid crystal panel control signal generation circuit 10 Liquid crystal panel

Claims (1)

[Claims] 1. An image display device for displaying a video signal on a liquid crystal panel, comprising: a phase locked loop circuit (hereinafter referred to as a PLL circuit) for generating a reference clock signal in synchronization with a horizontal sync signal of the video signal. An oscillation frequency control circuit for controlling the frequency of the reference clock signal generated by the PLL circuit, and a liquid crystal panel control signal generation circuit for generating each timing signal necessary for displaying an image on the liquid crystal panel, The oscillation frequency control circuit changes the frequency of the reference clock signal generated in the PLL circuit in accordance with the input video signal and inputs it to the liquid crystal panel control signal generation circuit, and each timing signal in accordance with the input video signal. An image display device which displays a video signal on a liquid crystal panel by generating