JP3070333B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device such as an auto-scan type display monitor, and more particularly to an on-screen character generation circuit for displaying the image on the image display device.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing details of a display character generator 4 in a conventional image display device.
41 is a display character generation IC, 42 is a display character generation clock generator to be supplied to the display character generation IC 41,
H and V are a horizontal synchronizing signal and a vertical synchronizing signal.

Next, the operation will be described. In order to perform character display in synchronization with an input signal input to the image display device, the horizontal synchronizing signal H and the vertical synchronizing signal V included in the input signal are input to the display character generating IC 41, and the control signal CC is used. Perform control.

On the other hand, a basic clock C ′ necessary for generating a display character is generated by a display character generation clock generator 42. The basic clock C ′ supplied from the display character generation clock generator 42 is equal to the dot clock of the pixels forming the display character.

Here, the display character generating IC 41 will be briefly described. The display character generation IC 41 has a built-in character generator ROM in which character data such as alphabets and numerals are stored in advance. Should be specified.

On the other hand, the character data stored in the character generator ROM is, as shown in FIG.
The constituent unit of one character is 12 dots wide by 18 dots high with one vertical width d _V and horizontal width d _H as one dot. For example, here, “01” in the figure indicates the storage address of the character data “1”. That is, when the character data “1” is to be displayed, the storage address “0” is displayed.
The first character can be specified.
This is performed by the control signal CC in FIG. Control signal CC
Is provided by a control unit (corresponding to that shown in FIG. 1 described later) that controls the entire image display device.

The character data designated for display by the control signal CC is synchronized with a clock C '(hereinafter referred to as a dot clock, which is equal to the basic clock as described above) output from the display character generating clock generator 42. Then, the display character generation IC is read out from the character generator ROM one dot at a time and displayed as display character data.
41. This state is shown in FIG. In this figure, f _{C ′} is the frequency of the dot clock C ′, t
_{C ′} is a cycle, t _{C ′} = 1 / f _{C ′} , and corresponds to the width d _{H of} one dot.

Here, the dot clock is a horizontal synchronizing signal ("H" in FIG. 6) inputted to the display character generating IC 41.
Is synchronized to. Now, it is assumed that the frequency f _C of the dot clock C ′ is constant. For example, the frequency of the horizontal synchronization signal H input to the display character generation IC 41 is f _H
Then, the maximum number of horizontal characters n _H that can be displayed during one horizontal period is

[0009]

(Equation 1)

(However, the horizontal blanking period is not considered here for the sake of convenience.) FIG. 9 shows a timing relationship between a display character and a horizontal period signal.

Next, consider the case where the frequency f _H of the horizontal synchronizing signal H input to the display character generation IC 41 is increased. The frequency of the horizontal synchronizing signal H at this time is f _H ^′ . At this time, the maximum number of horizontal characters n _H ^′ that can be displayed in one horizontal period is equal to the frequency f _C of the dot clock C ′.

[0012]

(Equation 2)

[0013] The equation (1), Comparing expression (2), as described above, or it is f _H <f _H ^'
Accordingly , n _H > n _H ^′ , and when the frequency f _H of the horizontal synchronization signal H increases, the number of characters that can be displayed in the horizontal direction decreases.

For example, if f _H ^′ = 2f _H , then, from [Equation 1] and [Equation 2],

[0015]

(Equation 3)

And the frequency f _C of the dot clock C ′
Is constant, if the frequency of the horizontal synchronizing signal H is doubled, the number of display characters is halved (see FIG. 8).

[0017]

Since the conventional image display device is configured as described above, when the frequency of the horizontal synchronizing signal H of the input signal is high, the displayed characters become large, and the display screen is not displayed. However, there is a problem that the required number of characters cannot be displayed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a simple circuit configuration, so that the required number of characters can be obtained regardless of whether the frequency of the horizontal synchronizing signal in the input signal is low or high. It is an object of the present invention to obtain an image display device capable of displaying the image.

[0019]

According to the first aspect of the present invention, a signal including a video signal and a synchronizing signal is used as an input signal. A deflection processing unit for generating a deflection voltage, and a frequency of a horizontal synchronization signal among the synchronization signals included in the input signal.
Detecting the wave number, comprising means for setting a certain threshold value, a control unit for controlling each unit according to the frequency of the synchronization signal,
A video signal processing unit for processing a video signal included in the input signal, and generating a character in synchronization with a frequency of the synchronization signal;
Including an IC for generating display characters, and having a frequency higher than the threshold value.
When the horizontal synchronization signal of the wave number is input,
A switching signal is generated by a control unit that controls the switching signal.
Based on the frequency of the input horizontal sync signal
For dividing the frequency by half (period is twice) (for example,
A flip-flop) and an input horizontal synchronization signal
(For example, a selector) for switching one line and one line
Display character data and store them in the line memory.
A double-speed conversion circuit that reads out character data with a double-speed clock
By providing, according to the change of the frequency of the synchronization signal
To control the reading of characters to adjust the frequency of the synchronization signal.
Synchronize and superimpose text on images
Those having a that display character generator.

The invention according to claim 2 of the present invention provides :
A signal including a video signal and a synchronization signal is used as an input signal.
A deflection voltage is generated according to the frequency of the synchronization signal in the force signal.
A deflection processing unit to generate the synchronization signal and the synchronization signal included in the input signal.
The frequency of the horizontal sync signal is detected from the
Means for setting a value of the synchronizing signal.
And a control unit that controls each unit, and is included in the input signal.
A video signal processing unit for processing a video signal;
Display character generation IC that generates characters in synchronization with frequency
And a horizontal sync signal having a frequency higher than the threshold
When pressed, the control unit that controls
Generating a switching signal, and based on the switching signal,
The frequency of the clock signal input to the character generation IC
(For example, flip)
Input to the display character generation IC.
Means for switching clock signals (eg, selectors)
By providing, according to the change of the frequency of the synchronization signal
To control the reading of characters to adjust the frequency of the synchronization signal.
Synchronize and superimpose text on images
Display character generator.

Further, the invention according to claim 3 of the present invention provides:
The display character generator is one of the synchronization signals included in the input signal.
Only when the frequency of the horizontal synchronizing signal is higher than a certain value, a double-speed conversion circuit that operates to double-speed display character data and a display character data selection unit that performs output switching are provided.

[0022]

According to the present invention, a certain point is set with respect to the frequency of the horizontal synchronizing signal of the input signal, and when the frequency of the horizontal synchronizing signal is higher than that point, the horizontal synchronizing signal supplied to the display character generating circuit is set. Reduce the frequency of the sync signal,
When the frequency of the horizontal synchronization signal is lower than a certain point, the frequency of the input horizontal synchronization signal is supplied to the circuit of the display character generator as it is. Regardless of whether the frequency of the signal is high or low, the number of displayed characters can be displayed substantially uniformly.

The frequency of the character-generating horizontal synchronizing signal is switched by a horizontal synchronizing signal switching circuit. By the operation according to the present invention, the display character data generated in synchronization with the horizontal synchronizing signal once converted to the low half frequency is doubled by the double speed conversion circuit, and the horizontal frequency returns to the original frequency. In addition, the display character generation clock switch
Cuts the cycle of the clock supplied to the display character generation IC.
Can be replaced.

[0024]

【Example】

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a main part of an image display device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input signal processing unit for processing an externally input signal, that is, an input signal including a synchronization signal and a video signal; a synchronization signal processing unit 2, a video signal processing unit 3, and display character generation. And a controller 4. Reference numeral 6 denotes a power supply (voltage) for deflecting an electron beam of a CRT display tube (not shown) based on the horizontal synchronization signal H and the vertical synchronization signal V supplied from the input signal processing unit 1. A deflection processing unit 7 for energizing the deflection coil is a power generation unit for supplying power to each unit. The synchronization signal processing unit 2 of the input signal processing unit 1
The synchronization signal is separated into a horizontal synchronization signal H and a vertical synchronization signal V. The video signal processing unit 3 processes a video signal among the input signals so that the video signal can be displayed. The display character generation unit 4 generates characters to be displayed so as to be superimposed on the video signal, for example, characters indicating adjustment items for adjusting an image displayed on the image display device. The control unit 5 controls all the elements (including other processing units not shown in FIG. 1) constituting the image display device.

Next, this operation will be described. In the image display device, the input signal includes a synchronization signal and a video signal, and both are processed separately in the image display device (FIG. 1). In the signal form input to the image display device, if the video signal and the synchronizing signal are mixed, the synchronizing signal among the input signals in the input signal processing unit 1 in the image display device is converted by the synchronizing signal processing unit 2. The signal is separated into a horizontal synchronization signal HS and a vertical synchronization signal VS.

The horizontal synchronizing signal HS and the vertical synchronizing signal VS extracted by the synchronizing signal processing section 2 are input to the deflection processing section 6, and the deflection processing section 6 uses the synchronization signal based on the synchronization signals.
Generates deflection voltage. At the same time, the second horizontal synchronizing signal and the vertical synchronizing signals H and V completely synchronized with the input signal are supplied from the deflection processing unit 6 to the display character generation unit 4. The operation principle of display character generation in the display character generation unit 4 is the same as that described in the related art.

The display character data output from the display character generator 4 is output to the video signal processor 3, where it is superimposed on the video signal input to the image display device and output to the cathode of the CRT display tube. You. Thus, the characters are superimposed and displayed on the output image.

Here, the principle of making the number of characters that can be displayed substantially constant irrespective of the frequency of the horizontal synchronization signal H of the input signal, which is the object of the present invention, will be described.

In FIG. 1, if the frequency of the horizontal synchronizing signal HS obtained by the synchronizing signal processing unit 2 from the input signal input to the image display device is f _H1 , the second horizontal synchronizing signal output from the deflection processing unit 6 The frequency of the signal H is equal to f _H1 . That is, the horizontal synchronization signal H input to the display character generator 4
Is f _H1 .

On the other hand, the frequency of the dot clock C 'input to the display character generation IC 41 is f _C' . Incidentally, the image display device according to the embodiment of the present invention is an auto scan type display monitor. For example, the frequency of the horizontal synchronizing signal H of the input signal is 15 kHz _Z ≦ H ≦ 90 kHz.
Display can be made corresponding to _Z. That is, the horizontal pull operable range is 15kH _Z ~90kH _Z.

Since the image display device according to the present invention is capable of displaying a wide range as described above, it is possible to display any horizontal synchronizing signal H at any frequency.
In order to make the number of possible characters almost constant, when a high frequency of the horizontal synchronizing signal H is input, the frequency is reduced to one half and input to the display character generation IC 41, and the display character generation IC 41 is displayed. An apparently low frequency is input to the IC 41. In other words, apparently horizontal
The period of the period signal H is increased so that many characters are generated.
You.

In the image display device of the present invention, a certain point is set with respect to the frequency of the horizontal synchronizing signal H in the synchronizing signal of the input signal, and the frequency of the horizontal synchronizing signal H of the input signal is set to the above-mentioned value. If it is lower than the point, it operates in the same manner as the display character generation operation of the conventional image display device. If it is higher than a certain point, the frequency of the input horizontal synchronizing signal H is divided by two, and accordingly Operate to generate display characters.

The determination as to whether the frequency of the horizontal synchronizing signal of the input signal is high or low with respect to a certain point is as follows.
The determination is made by the control unit 5 in the image display apparatus of FIG. 1 and the control signals CA, CB, CC, and CD shown in FIG. 2 are displayed, and the display character generation IC 41, the double speed conversion circuit 43, the horizontal frequency signal It is supplied to the switching circuit 45 and the display character data selection section 46.

FIG. 2 shows the display character generator 4 of FIG.
3 is a configuration block diagram of a main part showing the details of FIG. In FIG. 2, the display character generation IC 41 and the display character generation clock generation unit 42 are the same as those in FIG. 6, 43 is a double speed conversion circuit for converting display character data at double speed, 44 is a horizontal synchronizing signal frequency dividing circuit, 45 Is a horizontal synchronizing signal switching circuit for switching the frequency of the horizontal synchronizing signal for character generation, and 46 is a display character data selection unit which is an output switching circuit.

If the frequency f _H1 of the horizontal synchronization signal H of the input signal input to the image display device is higher than the value set in the image display device, the display character generation IC 41 includes
{frequency of the horizontal synchronizing signal = (1/2) f _H1} horizontal synchronizing signal H 'in which the f _H1 in one half the horizontal synchronizing signal switching circuit 4
5 is selected and input. At this time, the maximum number n _H1 of display characters in the horizontal direction is given by the following equation from [Equation 1].

[0036]

(Equation 4)

Here, since the horizontal synchronizing signal H 'input to the display character generation IC 41 is divided by half, the display character data output from the display character generation IC 41 is (1). / 2) are synchronized to ^{_{f H '{= (1/2)}} f H1}. However, since the frequency of the horizontal synchronization signal H input to the image display device is f _H (= f _H ^′ ), f _H
In order to synchronize the display characters with the image signal having the frequency of the horizontal synchronization signal H, the horizontal synchronization signal H of the display character data is used.
The frequencies match the f _H (i.e. f _H ^'), i.e. it is necessary to return the a divided based and doubled.

Therefore, the control signal CB (FIG. 2) given from the control unit 5 in FIG.
The double-speed conversion circuit 43 operates so as to double-convert the display character data output from C41. Here, the control signal CB is a selection signal for enabling or disabling the double speed conversion circuit 43. Next, the double speed conversion circuit 43 will be described. The double-speed conversion circuit 43 includes a one-line memory (F
IFO), and data written in synchronization with a clock in the line memory can be read out in synchronization with another certain clock.

When applied to the present embodiment, in FIG. 2, the signals for controlling the writing to the line memory of the double speed conversion circuit 43, that is, the write address reset signal -WR (active low) and the write clock signal WC are , The horizontal synchronizing signal H ′ output by the horizontal synchronizing signal switching circuit 45 and the dot clock C ′ output by the display character generating clock generator 42.
Is equivalent to

On the other hand, a signal for controlling reading from the line memory, that is, a read address reset signal-
RR and read clock signal RC correspond to H equal to the horizontal synchronizing signal input to the image display device according to the embodiment of the present invention, and read clock C output by display character generating clock generator 42, respectively. ing.

Now, as described above, it is assumed that a horizontal synchronizing signal (= frequency f _H1 ) having a frequency higher than the set value is input to the image display device. Accordingly, in FIG. 2, the display character generation IC 41 has H '= 1/2 selected by the horizontal synchronization signal switching circuit 45 by the control signal CA.
H is input, and on the other hand, the double speed conversion circuit 43 is selected to be enabled by the control signal CB. At this time, the maximum number of display characters (n _H1 ) output from the display character generation IC 41 in the horizontal direction is obtained from [Equation 4].

[0042]

(Equation 5)

Is given by Now, IC for display character generation
The display character data output from 41 is sequentially written to the line memory in synchronization with the write dot clock C ′ (the write address is reset at the timing of the horizontal synchronization signal H ′). At this time, the frequency of the horizontal synchronization signal H ′ is, as described above, the input signal f _H1.
(１ ／) f _H1, which is one half of

Next, in FIG. 2, the frequency (1/2) f
Double speed conversion circuit 4 at the timing of _H1 and dot clock C '
The display character data written in the line memory No. 3 is sequentially read out in synchronization with the read clock C (the read address is reset at the timing of H).

Regarding the read operation, the read clock C (clock frequency f _C = clock frequency) having twice the frequency of the dot clock C ′ (clock frequency f _{C ′} ) at the time of writing is used.
2f _{C ′} ), the read display character data has twice the frequency of writing, that is, 2H ′ (= 2H _C ).
f _H1 ), which is equal to the frequency of the horizontal synchronization signal H input to the image display device. That is, it is synchronized with the image signal.

As described above, among the signals input to the image display device, the frequency of the horizontal synchronizing signal H is set to the half horizontal synchronizing signal H ', and the display character generating IC 4 is synchronized with this.
1 to generate display character data,
As a result, the frequency of the horizontal synchronizing signal H 'is doubled by reading out the display character data at twice the speed, that is, the operation is returned to the state before the frequency was reduced to half.

FIGS. 3A to 3C are timing charts showing the concept of the above operation. FIG. 3A shows a horizontal synchronizing signal H and display character data input to the image display device.
FIG. 3B shows the horizontal synchronizing signal H 'frequency-divided by half according to the operation of the embodiment of the present invention, and display character data generated in synchronization with the horizontal synchronizing signal H'. FIG. 3C shows the present invention. The horizontal synchronizing signal H restored to the frequency equal to the input signal by the double speed conversion operation of the embodiment and the display character data subjected to the double speed conversion are shown.

Assuming that the number of display characters at this time is N, the number read from the line memory is still N, provided that the number written to the line memory is N. The above is
The frequency of the horizontal synchronization signal H input to the image display device is
The circuit operation at a point higher than a predetermined point has been described. On the other hand, when the frequency of the horizontal synchronization signal H input to the image display device is lower than a certain point, the same operation as the display character generation operation of the conventional image display device has been described above. Assuming that the frequency of the horizontal synchronizing signal H is f _H2 , in FIG. 2, the horizontal synchronizing signal H ′ input to the display character generation IC 41 is equal to H, and its frequency is equal to f _H2 .

The number of display characters in that case will be described below. When the frequency of the horizontal synchronizing signal H is f _H2 lower than a certain point, the maximum number n _H2 of display characters in the horizontal direction is given by the following equation from [Equation 1].

[0050]

(Equation 6)

On the other hand, the maximum number n _H1 of display characters in the horizontal direction when the frequency of the horizontal synchronizing signal H of the input signal is f _H1 higher than a certain point is given by the following equation.

[0052]

(Equation 7)

Here, the frequency f _H1 of the horizontal synchronizing signal higher than a certain point is about twice the frequency f _H2 of the horizontal synchronizing signal lower than a certain point, as shown in the following equation.

[0054]

(Equation 8)

If [Equation 7] is satisfied, [Equation 7] can be rewritten as follows.

[0056]

(Equation 9)

That is,

[0058]

(Equation 10)

According to the present invention, the same number of display characters can be obtained regardless of whether the frequency of the horizontal synchronizing signal H input to the image display device is low or high.

In the above embodiment, a ceramic oscillator, a crystal oscillator, an LC oscillator, an RC oscillator or the like can be used for the generation of the basic clock of the display character generation clock generator 42.

The circuits shown in FIGS. 4A to 4C can be used as the horizontal synchronizing signal switching circuit 45 in the first embodiment. That is, FIG. 4A shows the flip-flop circuit FF, the NAND gates G1 to G3, and the inverter G4.
FIG. 4B shows a combination of the flip-flop circuit FF and the selector circuit SEL, and FIG. 4C shows a combination of the analog switch circuit SW. In each of FIGS. 4A to 4C, the horizontal synchronizing signal H is halved by the flip-flop circuit FF to be a horizontal synchronizing signal H 'having a half cycle, and the control signal CA outputs H.
And H ′.

[Embodiment 3] In Embodiments 1 and 2,
The horizontal synchronization signal H supplied to the display character generation IC 41 is
According to the frequency of the horizontal synchronizing signal H of the input signal, half
To supply to the display character generation IC 41
Display the signal as it is without frequency division IC 41 for character generation
In some cases, this is divided into half at the frequency of all the input horizontal synchronizing signals H, and the cycle of the clock supplied to the display character generation IC 41 is switched instead. Is also good. FIG. 5 shows a block diagram thereof. In this figure, reference numeral 47 denotes a display character generation clock switching unit, where a read clock C and a dot clock C ′ are provided.
Have made a choice.

[0063]

As described above, according to the present invention, a signal including a video signal and a synchronizing signal is used as an input signal, and a deflection processing unit for generating a deflection voltage according to the frequency of the synchronizing signal among the input signals; The synchronization signal included in the input signal
In other words, the frequency of the horizontal sync signal is detected and a certain threshold is set.
And means for constant, and a control unit which controls the respective units in accordance with the frequency of the synchronizing signal, a video signal processing unit for processing a video signal included in the input signal, the frequency of the synchronizing signal
Includes a display character generation IC that generates characters synchronously.
Horizontal sync signal with a frequency higher than the threshold
In this case, a switching signal is sent from a control unit that controls the above-described units.
Generated and input horizontal synchronization based on this switching signal
Divide the frequency of the signal by half (frequency is doubled)
(Eg, flip-flop) and input
Means for switching the horizontal synchronization signal (for example, select
) And display character data for one line,
Reads the display character data stored in the memory with the double-speed clock.
A double-speed conversion circuit for outputting the synchronization signal.
Character reading is controlled according to the change in wave number to
Character superimposed on the image in synchronization with the frequency of the
Since the display character generating section is provided, the number of characters can be displayed substantially uniformly regardless of whether the frequency of the horizontal synchronization signal is high or low. The present invention also provides a display
Display character is generated because the clock switching unit for character generation is provided.
The cycle of the clock supplied to the IC
Wear.

The switching of the horizontal synchronization signal can be easily performed by the horizontal synchronization signal switching circuit in accordance with the frequency of the horizontal synchronization signal in the input signal. Furthermore, since the display character data is double-speed converted by the double-speed conversion circuit only when the frequency of the horizontal synchronization signal is higher than a predetermined value, the structure is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an image display device according to the present invention.

FIG. 2 is a block diagram showing details of a display character generator in the embodiment of FIG. 1;

FIG. 3 is a timing chart showing the concept of display character generation according to the present invention.

FIG. 4 is a block diagram of a horizontal synchronizing signal switching circuit showing a second embodiment of the image display device according to the present invention.

FIG. 5 is a block diagram of a display character generating portion showing a third embodiment of the image display device according to the present invention.

FIG. 6 is a block diagram showing a conventional display character generator.

FIG. 7 is a conceptual diagram showing a configuration of display character data.

FIG. 8 is a timing chart showing the concept of conventional display character generation.

FIG. 9 is a timing chart showing a relationship between a display character and a horizontal synchronization signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input signal processing part 2 Synchronous signal processing part 3 Video signal processing part 4 Display character generation part 5 Control part 6 Deflection processing part 7 Power generation part 41 Display character generation IC 42 Display character generation clock generation part 43 Double speed conversion circuit 44 Horizontal synchronization signal frequency dividing circuit 45 Horizontal synchronization signal switching circuit 46 Display character data selection section

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 5/24 G06F 3/153 G09G 1/04 G09G 1/16 G09G 1/18

Claims (2)

(57) [Claims] 1. A deflection processing section for generating a deflection voltage in accordance with a frequency of a synchronization signal of a signal including a video signal and a synchronization signal as an input signal, and the synchronization signal included in the input signal. Of the horizontal sync signal frequency
Out, comprising a means for setting a certain threshold value, a control unit that controls each unit according to the frequency of the synchronization signal, a video signal processing unit that processes a video signal included in the input signal,
Display text that generates characters in synchronization with the frequency of the synchronization signal
Including a character generation IC and having a frequency higher than the threshold value.
Controls the above components when a flat sync signal is input
A switching signal is generated from the control unit, and based on the switching signal,
Divides the frequency of the input horizontal synchronization signal by half
For switching the input horizontal synchronization signal
Means, and display character data for one line.
Display character data stored in the memory
By providing a double speed conversion circuit that
According to the change of the frequency, the reading of characters is controlled to
Superimpose characters on the image in synchronization with the frequency of the synchronization signal
An image display device, comprising: a display character generation unit capable of displaying. 2. A deflection processing section for generating a deflection voltage according to a frequency of a synchronization signal among the input signals, wherein the synchronization signal included in the input signal is a signal including a video signal and a synchronization signal. Of the horizontal sync signal frequency
Out, comprising a means for setting a certain threshold value, a control unit that controls each unit according to the frequency of the synchronization signal, a video signal processing unit that processes a video signal included in the input signal,
Display text that generates characters in synchronization with the frequency of the synchronization signal
Including a character generation IC and having a frequency higher than the threshold value.
Controls the above components when a flat sync signal is input
A switching signal is generated from the control unit, and based on the switching signal,
Of the clock signal input to the display character generation IC.
Means for dividing the frequency by half and the display text
Means for switching clock signal input to character generation IC
According to a change in the frequency of the synchronization signal.
To control the reading of characters to adjust the frequency of the synchronization signal.
Synchronize and superimpose text on images
The image display apparatus characterized by having a that display character generator.