JPH113062A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate flickering of picture when a video signal of a computer is processed with resolution conversion by an oversampling method and displayed by being interpolated and magnified on a FLCD (Ferro-electricity Liquid Crystal Display). SOLUTION: Each input picture signal in Odd, Even, and previous Odd fields latched by latches 101-103 are processed with resolution conversion by using parameters at operation parts 130-133. Based on a synchronizing signal of the input picture signal, clock CLKO synchronizing with the synchronizing signal, clock CLK1 corresponding to a magnification of resolution generated from the CKLO, a timing control part 120 and a parameter generation part 110 generate the parameters. The picture signal processed with resolution conversion is stored in FiFos 140-143. An address control unit 150 writes to FiFo with CLKO, and also reads from it with CLK1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for use, for example, when a video signal including an image signal and a synchronization signal is input and displayed on a display.

[0002]

2. Description of the Related Art In recent years, personal computers have been
It has come into widespread use in applications requiring graphic display such as D and design. Along with this, the image quality of graphic displays on computer displays has been improved.
High quality is required. As a method for satisfying such a demand, 1. 1. Increase the display resolution. For example, the frame (field) frequency is increased, and the former method can obtain a finer image, and the latter method enables display with less flicker. Therefore, in the personal computer, in addition to the VGA mode having a resolution of 640 × 480, which was previously mainstream, 800 × 600, 1024 × 768, and 128
A display that can also display a high resolution SVGA mode of 0 × 1024 is becoming popular, and the vertical synchronization frequency tends to increase from 60 Hz to 70 Hz or more.

On the other hand, as a display device technology, a flat panel display using a liquid crystal or the like has attracted attention in recent years. Flat panel displays are expected to become widely used in the future in place of conventional CRTs because of their compactness and extremely low emission of electromagnetic waves as monitors for desktop computers as well as laptop and notebook computers. Is done.

As one of such flat panel displays, a display using a ferroelectric liquid crystal (FLC) (hereinafter abbreviated as FLCD) has been put to practical use. F
LC has a property called a memory property (a property that the liquid crystal is kept ON / OFF even when an electric field required for switching is removed), and by utilizing this, it is very difficult with conventional liquid crystal technology. Large screen flat display can be realized. In other words, an efficient refresh operation of the screen is performed by detecting a motion of a line where the image data to be displayed has changed, selecting the selected line, and scanning the line preferentially on the display. Even if the upper limit frequency of the entire frame rewrite (hereinafter simply referred to as the frame frequency for simplicity) tends to decrease due to the increase in the number of display lines accompanying the increase in the size and definition of the display, it is not sufficient for a computer screen. The response speed can be realized.

[0005] In the current FLCD technology, each pixel of the display can only be in either the ON state or the OFF state, so that it is basically a binary display.
Therefore, in order to obtain more display colors: 1. Perform pixel division and perform area gradation by combining sub-pixels. It is necessary to use methods such as "dither method" and "error diffusion method" to perform digital halftone processing to express pseudo halftone, individually or in combination. In the case of a display whose display changes in real time, driving of sub-pixels and digital halftone processing also require a high-speed processing speed comparable thereto. However, these techniques can be implemented by LSI using advanced semiconductor technology.

Hitherto, video signals from a workstation or a personal computer have been displayed on a high-definition FLCD in the following manner. That is, while identifying the display mode from the synchronization signal of the computer,
Separate the synchronization signal into horizontal and vertical synchronization signals. Next, based on the identified display mode, an FLCD dot clock synchronized with the computer pixel clock is reproduced using the separated horizontal synchronization signal, and the image signal is converted to an A signal using the FLCD dot clock. / D conversion. After subjecting the digital data thus obtained to gamma characteristic adjustment and halftone processing, the digital image data is transferred to the output controller of the FLCD to enable display.

Further, VGA, SVGA, X
In a display mode such as GA, based on the identified display mode, regarding the expansion in the line direction, an “oversampling method” in which the horizontal effective display area of the video signal is sampled at 1280 corresponding to the number of display line pixels of the FLCD. In the vertical direction, a digital interpolation operation is performed while maintaining the aspect ratio, and an enlarged interpolation display for displaying the entire screen is performed.

[0008]

However, when the video signal of the computer is interpolated and enlargedly displayed on the FLCD by the oversampling method, there are the following problems. That is, since the analog video signal is sampled asynchronously with the pixel clock of the host computer, a transient and steep point between pixels is sampled. At this time, the dot clock, which is the sampling clock for A / D conversion, is generated from the horizontal synchronization signal, and this horizontal synchronization signal generally contains jitter. Under the influence, jitter occurs in the dot clock. Therefore, when the image is mainly a still image, the sampling point between pixels becomes indefinite for each frame due to the jitter, and the image quality deteriorates, in which the display flickers.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide an image processing apparatus capable of obtaining an image such as a high-quality computer image enlarged and interpolated with little flicker. I do.

[0010]

According to the present invention, an identification means for identifying a mode of a video signal including an image signal and a synchronization signal based on the synchronization signal, and a first signal synchronized with the image signal. Clock generating means for generating a second pixel synchronization clock having a multiple frequency corresponding to the identified mode from the frequency of the pixel synchronization clock, and generating a parameter for resolution conversion according to the identified mode. Parameter generation means, resolution conversion means for performing resolution conversion of the image signal using the parameter at the multiple corresponding to the identified mode, memory means for storing the resolution-converted image signal, and 1
Address control means for controlling an address of the memory means so as to write an image signal in synchronization with the pixel synchronization clock and read out the image signal in synchronization with the second pixel synchronization clock.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a low-pass filter for band-limiting an input video signal, reference numeral 20 denotes an A / D converter for sampling a band-limited video signal, and reference numeral 30 denotes a system for identifying a display mode and controlling the periphery of the system. A control unit, 40 is a sync separator for separating the synchronization signal, and 50 is a delay element for adjusting the phase of the pixel synchronization clock (hereinafter, CLK0 ') by adjusting the phase of the input synchronization signal.

Reference numeral 60 denotes a PLL-0 for generating CLK0 'from the input synchronizing signal, 70 denotes a clock generator for reproducing CLK0 from the input synchronizing signal and generates an internal synchronizing signal, and 80 generates CLK1 multiplied by CLK0'. PLL-
1, 90 are P which generate CLK2 which is a multiple of CLK1.
LL-2, 100 are horizontal interpolation units for expanding the image in the horizontal direction, 200 are vertical interpolation units for expanding the image in the vertical direction, 30
Reference numeral 0 denotes a halftone processing unit for performing image processing on the digitized data, and reference numeral 400 denotes a ferroelectric liquid crystal display (hereinafter, FLCD) as a display device.

Next, the operation will be described. First, the flow of the synchronization signal will be described. Separate sync, composite sync, sync-on-green, and the like are input to the sync signal, and are sent to the sync separator 40. The sync separator 40 extracts a synchronization signal from the input signal, determines the polarity of the synchronization signal, etc.
It outputs the vertical synchronizing signal, the horizontal synchronizing signal and the polarity of these synchronizing signals to 0, and outputs the negatively converted horizontal synchronizing signal to the clock generator 70.

The system control unit 30 measures the frequency of the input synchronization signal, and identifies the display mode of the input video signal based on the result and the polarity of the synchronization signal.
PLL-0 (60), PLL based on the identification result
-1 (80), PLL-2 (90), horizontal interpolation unit 10
0, controls the peripheral systems such as the vertical interpolation unit 200 and the halftone processing unit 300.

PLL-0 (60), PLL-1 (8
0) and PLL-2 (90), in this case, Phase
Locked Loop circuit (PLL) and VCO (Voltage-contro
A clock generation circuit using an lled oscillator will be taken as an example. The system control unit 30 determines the frequency division value corresponding to the display mode and the interpolation magnification as PLL-0 (6).
0), PLL-1 (80), and PLL-2 (90).

Next, the flow of a video signal will be described.
The input video signal is input to the LPF 10 in order to remove a high-frequency noise component such as a ripple included in the signal. The band-limited video signal is input to the A / D converter 20 and is sampled for each odd and even field by CLK0. Here, the delay element 50
Is to adjust a phase shift caused by a video signal and a synchronization signal which are in phase at the time of output from the computer passing through different processing systems.
And the phase of the band-limited video signal.

The sampled digital video data is subjected to enlargement interpolation processing at a magnification determined by the system control unit 30 in the horizontal interpolation unit 100 and the vertical interpolation unit 200. Here, the horizontal interpolation unit 200 according to the present invention is used.
Will be described with reference to FIG. In FIG.
03 is a latch unit for latching input data, 110 is a parameter unit for controlling parameters of interpolation calculation, 120 is a timing control unit for controlling the timing of each module of the entire horizontal interpolation unit 100, and 130 to 133 perform interpolation calculation. Operation units, 140 to 143 are Fifos for storing interpolation operation results, 150 is an address control unit for controlling writing / reading of the Fifos, 160 and 161 are output selection units for selecting data to be output, and 170 is a synchronization signal. It is an output control unit to generate.

The input image signal includes an odd number and an even number (Od
d, Even) latched by the latch 101 and the latch 102 for each field.
Is latched. These image data are
Based on the operator of the parameter unit 110, the operation unit 130
To 133 are input as shown.

A calculation example used in the present embodiment is shown below. Here, an example of the calculation in the case where the VGA is subjected to the interpolation processing by the interpolation magnification of (8/5) times the XGA is shown. a1, a
2,..., An indicate input pixels, and b1, b2,
.., Bn indicate output pixels. b1 = a1 b2 = (1/4 + 1/8) * a1 + (1/2 + 1/8 +
1/16) * a2 b3 = a2 b4 = a3 b5 = (1/2 + 1/32) * a3 + (1/2) * a4 b6 = a4 b7 = a5 b8 = (1/2 + 1/8 + 1/16) * a5 + ( 1/4
+1/8) * a6

The parameters are sent from the parameter section 110 to the calculation sections 130 and 132 so as to perform the calculations described above. The calculated image data is Fifo-0 (14
0), Fifo-1 (141), Fifo-2 (14
2), temporarily stored in the FiFo-3 (143) and sent to the output selection units 160 and 161 respectively.

On the other hand, the input synchronizing signal is sent to the timing control unit 120, which adjusts the number of peripheral pipe processes and controls the asynchronous unit, and sends a control signal to each module. In the address control unit 150, the timing control unit 12
In response to each enable signal from 0, each FIFO-
0 (140), FiFo-1 (141), FiFo-2
(142), and control of data write / read addresses to / from the FIFO-3 (143). Output control section 170
Then, the timing of the synchronization signal and the control signal to the output selection units 160 and 161 are adjusted. CLK1 is obtained by multiplying CLK0 by (8/5) with PLL-1 (80), and
Used as a read clock for o.

FIG. 3 shows Data_Flow of the interpolation unit. a1, a2,..., an indicate input pixels,
Fifo-0 (140), Fifo-1 (141), F
The output pixels b1, b2,..., bn calculated in iFo-2 (142) and FiFo-3 (143) are stored by CLK0. Next, by reading the horizontal interpolation data with the multiplied CLK1, and passing the Fifo number to be selected to the output selection units 160 and 161, new horizontal interpolation data can be obtained from the output selection units 160 and 161. it can.

The vertical interpolation unit 200 performs conventional digital interpolation based on the system control unit 30 to perform enlarged interpolation. The halftone processing unit 300 receives digital video data, CLK2, and a signal from the system control unit 30, and
The digital image processing required for the LCD 400 is performed. The digital video data subjected to the halftone processing is transferred to the FLCD 400 under appropriate output line control, and displays a flicker-free high-quality magnified and interpolated computer image.

Note that the FiFo 140 according to the present embodiment is
When the resolution conversion of n / m is performed, when the minimum integer greater than or equal to the quotient of max (n, m) / min (n, m) is 1 Can be the minimum required memory capacity of (l + 1) pixels and (l + 1) lines in the vertical direction.

[0025]

As described above, according to the present invention,
It is possible to obtain an image such as a high-quality computer image or the like which is interpolated and enlarged with little flicker. In addition, by asynchronously writing and reading data to and from the memory in real time, resolution conversion can be performed at low cost with a small amount of memory without requiring a large-capacity memory such as a frame memory or line buffer. Will be able to do it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a horizontal interpolation unit of FIG. 1;

FIG. 3 is a timing chart illustrating an operation of a horizontal interpolation unit.

[Explanation of symbols]

 Reference Signs List 30 system control unit 60 PLL-0 70 clock generation unit 80 PLL-1 101 to 103 latch unit 110 parameter unit 120 timing control unit 130 to 133 arithmetic unit 140 to 143 FiFo 150 address control unit

Claims (2)

[Claims] An identification means for identifying a mode of a video signal including an image signal and a synchronization signal based on the synchronization signal, and the identification means is identified from a frequency of a first pixel synchronization clock synchronized with the image signal. Clock generating means for generating a second pixel synchronization clock having a multiple frequency corresponding to the selected mode; parameter generating means for generating a parameter for resolution conversion according to the identified mode; Resolution conversion means for performing resolution conversion of the image signal by the multiple corresponding to the identified mode; memory means for storing the resolution-converted image signal; and synchronizing with the first pixel synchronization clock. An image control circuit for controlling an address of the memory means so as to write an image signal and read the image signal in synchronization with the second pixel synchronization clock. The image processing apparatus and a less control means. 2. The memory means according to claim 1, wherein when performing resolution conversion of n / m, if a minimum integer equal to or larger than a quotient of max (n, m) / min (n, m) is 1, 2. The image processing apparatus according to claim 1, wherein the minimum required memory capacity is (l + 1) pixels for the vertical direction and (l + 1) lines for the vertical direction.