JP4367100B2 - Image display device - Google Patents

Description

  The present invention relates to a hold-type image display device typified by a liquid crystal display device, and more particularly to an image display device that can reduce the blur of moving images.

The image display device includes an impulse display device that emits light strongly at the moment of image writing, such as a display device using a cathode ray tube (CRT), and an active matrix display device that has a memory function for each pixel. There is a hold-type display device that holds a display until an image of the next frame is written after an image is written. As an active matrix display device, there is a liquid crystal display device using a thin film transistor (TFT). In a liquid crystal display device, an image written in a pixel is held for a certain time by a TFT and a capacitor arranged for each pixel.
Since the liquid crystal display device has a low response speed, there is a problem that an afterimage is generated when a moving image is displayed. One method of reducing this problem is to use a filter (time axis enhancement circuit) that enhances the video signal in the time axis direction.

However, in a hold-type display device such as a liquid crystal display device, even if the response speed of the liquid crystal is increased, moving image blurring due to the influence of visual system integration due to the hold display itself (hereinafter referred to as moving image blurring) is solved. I can't do it.
This problem and its solution are described in Non-Patent Document 1 below. Note that the moving image blur occurs not only in the liquid crystal display device but also in the organic matrix display device in the case of the active matrix type. Non-Patent Document 1 discloses, as a solution for moving image blurring, a first method that shortens the hold time and approaches an impulse-type display, and doubles the frame frequency of the input video signal whose frame frequency is 60 Hz by the motion compensation means. And a second method for increasing the speed to 120 Hz.
Yashiro Kurita, “Principle Degradation of Video Quality Caused by Liquid Crystal Displays and Its Improvement Method”, IEICE Technical Report EID2000-47 (2000-09), p. 13-18

  The first method requires a means for shuttering the backlight in synchronism with the video signal, and has the disadvantage that the flicker-free display that is an advantage of the hold-type display is impaired (first problem). Point). In the second method, in order to double the frame frequency, the sampling frequency of the video signal and the writing speed of the liquid crystal must be doubled, respectively, for the circuit operation speed and the connection interface between the circuits. There is a drawback (second problem) that it is a heavy burden and is difficult to implement.

  The present invention has been made in view of such a problem, and provides an image display device capable of reducing moving image blurring without impairing the advantage of hold-type display that can perform display without flickering. For the purpose. It is another object of the present invention to provide an image display device that can be easily realized with less burden on the operation speed of the circuit and the connection interface between the circuits when reducing the motion blur.

The present invention for solving the problems of the prior art described above, a plurality of pixels arranged in a matrix, use the electrical signal to the image Motogoto an active matrix type display panel that displays holding a predetermined time In the image display apparatus, a video signal having a first vertical frequency is converted to m / n times the first vertical frequency (where m is an integer of 2 or more, n is an integer of 1 or more, m> a rate conversion circuit ( 10 ′ ) that converts and outputs a second vertical frequency that satisfies the condition of n) and two adjacent video signals having the second vertical frequency that are output from the rate conversion circuit. a frame image data to emphasize the time axis emphasizing circuit the high-frequency component in the time axis direction using the (20 '), the active video signal having the second vertical frequency output from the time axis emphasis circuit And a drive circuit for displaying on Torikusu display panel (30), said rate conversion circuit includes a plurality of images to be output as a video signal of said second vertical frequency by writing a video signal having a first vertical frequency A memory (101, 102), a motion vector detection circuit (103) for detecting a motion vector using the image data output from the plurality of image memories, the image data output from the plurality of image memories and the motion First and second interpolation circuits (1041, 1042) that output image data that is a video signal having the second vertical frequency and is shifted by one frame from each other by performing motion compensation interpolation using a vector. And the time axis emphasizing circuit uses the image data output from the first and second interpolation circuits as the image data for the two adjacent frames. An image display device characterized by emphasizing high-frequency components in the axial direction is provided.

Furthermore, the present invention solves the above-described problems of the conventional technique, and the present invention solves the problems of the above-described conventional technique, and has a plurality of pixels arranged in a matrix and outputs an electric signal . in the image display device using an active matrix type display panel for displaying to hold a predetermined time image Motogoto, a video signal having a first vertical frequency, the first m / n times (where the vertical frequency, m is an integer greater than or equal to 2, n is an integer greater than or equal to 1, and the rate conversion circuit (10 ″) for converting to a second vertical frequency and satisfying the condition that m> n) and the rate conversion circuit A time axis emphasizing circuit (20 ′) for emphasizing a high frequency component in the time axis direction using image data for two adjacent frames in the video signal having the second vertical frequency outputted from the time axis, and the time axis emphasis Output from circuit And a drive circuit (30) for displaying the video signal having the second vertical frequency on the active matrix display panel, and the rate conversion circuit writes the video signal having the first vertical frequency. A plurality of image memories (101, 102) that output as video signals of the second vertical frequency, and a motion vector detection circuit (103) that detects a motion vector using image data output from the plurality of image memories; An interpolation circuit (104) for performing motion compensation interpolation using the image data output from the plurality of image memories and the motion vector, and outputting the video signal of the second vertical frequency, and the plurality of images The image data output from the memory and the image data output from the interpolation circuit are selectively output so that they are shifted from each other by one frame. First and second selectors (1051, 1052) for outputting certain image data, and the time axis emphasizing circuit outputs the image data for the two adjacent frames from the first and second selectors. There is provided an image display device characterized by emphasizing a high frequency component in a time axis direction using the image data thus obtained.

  According to the present invention, it is possible to reduce moving image blurring without impairing the advantage of hold-type display that can perform display without flicker. The present invention can be easily realized with less burden on the operation speed of the circuit and the connection interface between the circuits. Further, since a special circuit such as shuttering the backlight is not required, the cost increase is small.

  Hereinafter, an image display device of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of the image display apparatus of the present invention, FIG. 2 is a block diagram showing a specific configuration example of the frame rate conversion circuit 10 in FIG. 1, and FIG. 3 is a frame rate in FIG. 4 is a diagram for explaining the operation of the conversion circuit 10, FIG. 4 is a block diagram showing a specific configuration example of the time axis enhancement circuit 20 in FIG. 1, and FIGS. 5 and 6 are for explaining the effects of the first embodiment. FIG. 7 is a partial block diagram showing a second embodiment of the image display device of the present invention, FIG. 8 is a timing diagram for explaining the operation of the second embodiment, and FIG. 9 is a diagram of the image display device of the present invention. FIG. 10 is a block diagram showing a fourth embodiment of the image display device of the present invention, FIG. 11 is a partial block diagram showing a specific configuration example of the fourth embodiment, and FIG. The operation of the frame rate conversion circuit 11 in FIG. 10 will be described. Because of FIG, 13 is a timing chart for explaining the operation of the fourth embodiment, FIG. 14 is a diagram for explaining the moving image blurring occurs in the hold-type display.

<First Embodiment>
The first embodiment solves the first problem described above. In FIG. 1, the video signal is input to the frame rate conversion circuit 10. The frame rate conversion circuit 10 doubles the frame frequency (vertical frequency) of the input video signal and outputs it. In the first embodiment and the second and third embodiments described later, the frame frequency of the input video signal (original signal) is converted to m / n times. Here, m is an integer of 2 or more, n is an integer of 1 or more, and satisfies the condition of m> n. In the first to fourth embodiments, m = 2 and n = 1, and the frame frequency 60 Hz of the input video signal is converted to 120 Hz.
It is assumed that a 2: 1 interlaced video signal at a frame frequency of 30 Hz is previously converted into a progressively scanned video signal at a frame frequency of 60 Hz by sequential scanning conversion. The specific configuration and operation of the frame rate conversion circuit 10 will be described later.

  The video signal having a frame frequency of 120 Hz output from the frame rate conversion circuit 10 is input to the time axis enhancement circuit 20. The time axis emphasis circuit 20 emphasizes and outputs a high frequency component in the time axis direction of the input video signal. Specific configurations and operations of the frame rate conversion circuit 10 and the time axis enhancement circuit 20 will be described later. The video signal output from the time axis emphasis circuit 20 is input to the drive circuit 30, and the drive circuit 30 drives the liquid crystal panel 40 as an example of a hold type display device (display panel) to display the video signal with a frame frequency of 120 Hz. To do. The display panel is not limited to a liquid crystal panel, and may be an active matrix display panel that has a plurality of pixels arranged in a matrix and displays an electric signal by holding each pixel for a predetermined time.

The frame frequency conversion circuit 10 is configured as shown in FIG. 2 as an example. In FIG. 2, the input video signal is written in the image memories 101 and 102. From the image memories 101 and 102, image data for one frame, that is, two frames in total, are simultaneously read out at a speed twice the writing speed. However, the image data output from the image memory 102 is delayed by 1/60 second with respect to the image data output from the image memory 101.
Image data output from the image memories 101 and 102 is supplied to a motion vector detection circuit 103 and an interpolation circuit 104. As an example, the motion vector detection circuit 103 detects a motion vector between frames using a matching method. The interpolation circuit 104 performs motion compensation interpolation from the image data for two frames read from the image memories 101 and 102 and the motion vector data from the motion vector detection circuit 103, and outputs a video signal having a frame frequency of 120 Hz.

  The motion compensation interpolation in the interpolation circuit 104 performs vector movement as shown in FIG. 3 because the frame frequency conversion ratio is double. 3A shows an input video signal to the interpolation circuit 104, and FIG. 3B shows an output video signal from the interpolation circuit 104. FIG. Assume that the frame numbers of the input video signals are F1, F2, F3... And the frame numbers of the output video signals are f1a, f1b, f2a, f2b, f3a. Since the conversion from the frame F1 to the frame f1a, the conversion from the frame F2 to the frame f2a, and the conversion from the frame F3 to the frame f3a have the same time phase, no vector movement is performed. The frame f1b is vector-moved and inserted between the frames F1 and F2, and the frame f2b is vector-moved and inserted between the frames F2 and F3.

The right side of FIGS. 3A and 3B shows the movement of the object O across the frames F1 to F3 and the frames f1a to f3a. In FIG. 3 (A), the object O is moved at vector V ₁ move to the position in the frame F2 from the position in the frame F1, moves upon vector V ₂ moves to a position in the frame F3 from the position in the frame F2. In FIG. 3B, the position of the object O in the frames f1a, f2a, and f3a is the same as the frames F1, F2, and F3, respectively. To generate an image of the frame f1b may be moved to the image of the frame F1 by V _1/2, to generate an image of the frame f2b is, if moving an image of the frame F2 by V _2/2 Good.

In the example shown in FIG. 3, only the image data of the frame F1 is used when generating the frame f1b, and only the image data of the frame F2 is used when generating the frame f2b. May be. The image data of the frames F1 and F3 may be combined. In this case, for the frame f1b, F1 ′ obtained by moving the image of the frame F1 by V _1/2 and F2 ′ obtained by moving the image of the frame F2 by −V _1/2 are obtained, and F1 ′ and F2 ′ are set to 1: 1. Obtained by mixing in proportions. The frame f2b is "'seek, F2 and F3 has moved the image of the frame F3 by -V _2/2 F3"' the image of the frame F2 has been moved by V _2/2 F2 1: 1 ratio of Obtained by mixing with. The mixing ratio shown here is an example, and the present invention is not limited to this example.
As described above, when generating the frame of the output video signal, if interpolation is performed using not only one frame but also a plurality of frames, it is possible to reduce noise.

The time axis emphasis circuit 20 is configured as shown in FIG. 4 as an example. In FIG. 4, when the video signal having a frame frequency of 120 Hz output from the frame rate conversion circuit 10 is defined as fin, the video signal fin is input to the image memory 201 and output as a video signal fout delayed by one frame. The subtractor 202 subtracts the video signal fout from the video signal fin, and supplies the difference between the video signal fin and the video signal fout to the multiplier 203. Multiplier 203 multiplies the input difference by coefficient a and supplies the result to adder 204. The adder 204 adds the video signal fin and the output of the multiplier 203 and outputs the result as an output signal g. The output signal g is expressed by the following equation (1).
g = fin + a (fin−fout) (1)
The coefficient a is set according to the response characteristics of the liquid crystal. If the response is relatively fast and there are few afterimages, a is set small, and if the response is slow and there are many afterimages, a is set large.

  5 and 6 show the effects of the first embodiment. FIG. 5 shows a display state when rectangular waveforms arranged in black, white, and black are translated in the horizontal direction. FIG. 5A is a video signal having a frame frequency of 60 Hz before frame rate conversion by the frame frequency conversion circuit 10. (B) is a display state by a video signal having a frame frequency of 120 Hz after frame rate conversion by the frame frequency conversion circuit 10 and before time axis enhancement by the time axis enhancement circuit 20, and (C) is a frame frequency conversion circuit 10. This is a display state by a video signal having a frame frequency of 120 Hz after the time axis enhancement by the frame rate conversion and time axis enhancement circuit 20 by. As shown in FIGS. 5A to 5C, black, white, and black rectangular waveforms that move in parallel in the horizontal direction are displayed side by side in the time t direction.

When moving from one frame to the next and the black, white, and black rectangular waveforms move in the horizontal direction, the image is integrated into the human eye at the point where white to black and black to white are switched. Since the phenomenon of visual system integration occurs, as shown in FIGS. 5A to 5C, it seems that the video is gradually switched from black to white and from white to black, resulting in motion blur. Become. As shown in FIGS. 5A to 5C, the moving image blur due to the integration of the visual system is composed of a blur a resulting from the hold display and a blur b resulting from the response speed of the liquid crystal. In FIG. 5A with a frame frequency of 60 Hz, both blur a and blur b are large. In FIG. 5B with a frame frequency of 120 Hz, the width of the blur a is narrowed, and the moving image blur is improved. However, the blur b is not improved. In FIG. 5C in which the time axis is emphasized at a frame frequency of 120 Hz, the width of the blur b is also narrowed, and the moving image blur is further improved.
FIGS. 6A and 6B show the voltage / light response at the cross-section p indicated by the alternate long and short dash line in FIGS. 5B and 5C, respectively. By the time axis emphasis by the time axis emphasis circuit 20, the voltage / light response is corrected from (A) to (B) in FIG. 6, and the display characteristics in units of frames are improved.

Second Embodiment
In the second embodiment, the specific configuration of the frame rate conversion circuit 10 and the time axis enhancement circuit 20 in FIG. 1 is improved. Specifically, the image memory 201 in FIG. 4 is deleted, and the image memory 201 is deleted. Accordingly, the specific configuration of the frame rate conversion circuit 10 is changed. The frame rate conversion circuit and the time axis enhancement circuit in the second embodiment are referred to as a frame rate conversion circuit 10 'and a time axis enhancement circuit 20', respectively. 7, the same parts as those in FIGS. 2 and 4 are denoted by the same reference numerals, and the description thereof may be omitted as appropriate.

In FIG. 7, the image data output from the image memories 101 and 102 is supplied to the motion vector detection circuit 103 and the interpolation circuits 1041 and 1042. The interpolation circuit 1041 is substantially the same as the interpolation circuit 104 in FIG. 2, and is based on the image data for two frames read from the image memories 101 and 102 and the motion vector data from the motion vector detection circuit 103. Performs motion compensation interpolation and outputs image data of the current frame. The interpolation circuit 1042 performs motion compensation interpolation from the image data for two frames read from the image memories 101 and 102 and the motion vector data from the motion vector detection circuit 103, and outputs the image data of the previous frame. To do.
The image data output from the interpolation circuit 1041 is supplied to the subtracter 202 and the adder 204, and the image data output from the interpolation circuit 1042 is supplied to the subtracter 202.

Here, the operation timing of the frame rate conversion circuit 10 ′ will be described with reference to FIG. In FIG. 8, (A) is image data of an input video signal having a frame frequency of 60 Hz. As shown in (B) and (C), the same image data is read twice from the image memories 101 and 102 and the frame is read. The video signal has a frequency of 120 Hz. The image data output from the image memory 102 is delayed by 1/60 second with respect to the image data output from the image memory 101. For the sake of convenience, the timings of FIGS. 8B to 8F are shifted from the timing of FIG. 8A as indicated by a one-dot chain line.
The motion vector detection circuit 103 detects the motion vectors V ₁ , V ₁ , V ₂ , V ₂ ... Using the image data output from the image memories 101 and 102 as shown in FIG. As shown in FIG. 8E, the interpolation circuit 1041 outputs the frame f1b at the frame timing t1a and outputs the frame f2a at the frame timing t1b. As shown in FIG. 8F, the interpolation circuit 1042 outputs the frame f1a at the frame timing t1a and outputs the frame f1b at the frame timing t1b.

  As can be seen by comparing (E) and (F) in FIG. 8, the image data in FIG. 8 (F) is delayed by one frame at a period of 120 Hz from the image data in FIG. 8 (E). In the time axis enhancement circuit 20 ′ of the second embodiment, it is not necessary to provide the image memory 201 unlike the time axis enhancement circuit 20 of FIG. Therefore, in the second embodiment, the image memory can be reduced as compared with the first embodiment, and the cost can be reduced.

<Third Embodiment>
In the third embodiment, the frame rate conversion circuit 10 ′ of the second embodiment is further simplified, and the frame rate conversion circuit in the third embodiment is referred to as a frame rate conversion circuit 10 ″. 2, 4, and 7 are assigned the same reference numerals, and descriptions thereof may be omitted as appropriate.
The image data output from the image memories 101 and 102 is supplied to the motion vector detection circuit 103, the interpolation circuit 104, and the selectors 1051 and 1052. The image data output after the motion compensation interpolation by the interpolation circuit 104 is supplied to the selectors 1051 and 1052.
The image data output from the selector 1051 is supplied to the subtracter 202 and the adder 204, and the image data output from the selector 1052 is supplied to the subtracter 202.

The selectors 1051 and 1052 select the “0” side at the frame timing t1a in FIG. 8 and the “1” side at the frame timing t1b. As described with reference to FIG. 3, generation of an interpolated image with vector movement is limited to the frames f 1 b, f 2 b... Since only one of the selectors 1051 and 1052 is provided at one frame timing, a simplified configuration as shown in FIG. 9 can be achieved.
In the third embodiment, selectors 1051 and 1052 are required as compared with the second embodiment, but since only one of the interpolation circuits 104 has a relatively large circuit scale, the cost can be further reduced. Is possible.

<Fourth embodiment>
The fourth embodiment solves the first and second problems described above. With reference to FIG. 14, the generation of moving image blur in the hold type display device and the principle of reduction thereof will be described again. 14 does not perform time axis enhancement as described with reference to FIGS. 5 and 6, and only the blur a resulting from hold display ignoring the blur b resulting from the response speed of the liquid crystal has occurred. Is illustrated.
FIG. 14 shows a display state when rectangular waveforms arranged in black, white and black are translated in the horizontal direction. Note that the frame frequency of the video signal (original signal) is 60 Hz, such as the NTSC system. In FIG. 14, (A) shows the case where the frame frequency is set to 60 Hz as the original signal, and (B) shows a frame frequency which is a suitable example of the fourth embodiment described later as 90 Hz which is 3/2 times the original signal. In this case, (C) is described in Non-Patent Document 1 described above, and is a case where the frame frequency is 120 Hz which is twice the original signal as in the first to third embodiments described above. As shown in FIGS. 14A to 14C, black, white, and black rectangular waveforms that move in parallel in the horizontal direction are displayed side by side in the time t direction.

  When moving from one frame to the next and the black, white, and black rectangular waveforms move in the horizontal direction, the image is integrated into the human eye at the point where white to black and black to white are switched. Since the phenomenon of integration of the visual system occurs, as shown in FIGS. 14A to 14C, it seems that the display is gradually switched from black to white and from white to black. Accordingly, the moving image blur having the width shown in each of FIGS. 14A to 14C occurs. As can be seen from FIGS. 14A to 14C, the moving image blur width decreases as the frame frequency increases. At the frame frequency of 120 Hz in FIG. 14C, as described in Non-Patent Document 1, the same effect as the 50% duty intermittent display can be obtained. At the frame frequency of 90 Hz in FIG. 14B, the same effect as the intermittent display with about 67% duty can be obtained.

  As can be seen from the above description, the higher the frame frequency, the closer to the impulse-type display, and the moving image blur is further reduced. However, even if the frame frequency is increased to an integral multiple exceeding twice, the response speed of the liquid crystal is limited, and the effect of increasing the frame frequency is diminished. Therefore, the higher the frame frequency, the better. At present, the most mainstream WXGA pixel count is 1280 dots × 768 lines, and if the sampling frequency for the effective video period is calculated ignoring the blanking period, the sampling frequency is 118 MHz when the frame frequency is 120 Hz. The sampling frequency of 118 MHz is a very heavy burden on the operation speed of the circuit and the connection interface between the circuits (for example, between the frame rate conversion circuit and the drive circuit). Therefore, setting the frame frequency to 120 Hz is accompanied by difficulty in realization, and is difficult to adopt as an actual product.

  Therefore, in the fourth embodiment, the frame frequency (vertical frequency) that can effectively reduce motion blur and can be adopted as an actual product has been intensively studied. In the fourth embodiment, the frame frequency of the input video signal (original signal) is converted to m / n times. Here, m is an integer of 3 or more, n is an integer of 2 or more, and the condition that m> n and m / n is not an integer is satisfied. Preferable examples of m and n are m = 3 and n = 2. In the fourth embodiment described in detail below, m = 3 and n = 2, and the frame frequency 60 Hz of the input video signal is converted to 90 Hz. The inventor has confirmed through experiments that the moving image blur can be sufficiently effectively reduced at 90 Hz without setting the frame frequency to 120 Hz described in Non-Patent Document 1 described above. Considering the display operation capability of the display panel, the converted frame frequency is preferably 100 Hz or less.

  When the frame frequency is 90 Hz, the same effect as the intermittent display with a duty of about 67% is obtained as described above, which corresponds to the case where the shutter period is about 33%. This shutter period is about 5.56 ms in terms of time. This is a significant improvement in the response speed of the liquid crystal. Further, when the frame frequency is 90 Hz, the sampling frequency of the video signal is 1.5 times the sampling frequency of the original signal, and may be about 88.5 MHz. This sampling frequency of about 88.5 MHz is a value sufficiently realizable for the operation speed of the current integrated circuit (IC) and for the connection interface between the circuits.

  By the way, a liquid crystal panel of 1280 dots × 720 lines (so-called 720P format) is often used. In this case, the sampling frequency at the frame frequency of 90 Hz is about 82.9 MHz, which is easy to realize and can be adopted as an actual product. If the frame frequency is 120 Hz, the sampling frequency is 110.6 MHz. It is preferable that the sampling frequency of the video signal after frame frequency conversion (frame frequency × number of vertical lines × number of horizontal pixels) is 100 MHz or less. If the sampling frequency is 100 MHz or less, there is no problem in terms of the operation speed of the integrated circuit and the connection interface between the circuits.

  An example of the overall configuration of the fourth embodiment is as shown in FIG. In FIG. 10, the frame rate conversion circuit 11 receives a video signal which is a progressive scanning signal with a frame frequency of 60 Hz. The frame rate conversion circuit 11 converts the frame frequency of the input video signal to 3/2, that is, converts it to 90 Hz and outputs it. A video signal having a frame frequency of 90 Hz is input to the time axis enhancement circuit 21. The time axis emphasis circuit 21 emphasizes the input video signal with respect to the time axis and outputs it. Specific configurations and operations of the frame rate conversion circuit 11 and the time axis enhancement circuit 21 will be described later. The video signal output from the time axis emphasis circuit 21 is input to the drive circuit 31, and the drive circuit 31 drives a liquid crystal panel 41 as an example of a hold type display device (display panel) to display a video signal having a frame frequency of 90 Hz. To do.

  As an example, the frame rate conversion circuit 11 and the time axis enhancement circuit 21 are configured as shown in FIG. In FIG. 11, a video signal having a frame frequency of 60 Hz is input to image memories 111 to 113. Image data for one frame is written in the image memories 111 to 113 at a writing frequency of 60 Hz, and is simultaneously read out at a reading frequency of 90 Hz, which is 3/2 times the speed of the input video signal. However, the image data output from the image memory 112 is delayed by 1/60 second with respect to the image data output from the image memory 111, and the image data output from the image memory 113 is output from the image memory 111. The image data is delayed by 2/60 seconds.

The image data read from the image memories 111 to 113 is input to the motion vector detection circuit 114 and the interpolation circuits 1151 and 1152. The motion vector detection circuit 114 detects a motion vector between frames based on the image data for three frames from the image memories 111 to 113 using a matching method or the like. The interpolation circuits 1151 and 1152 perform motion compensation interpolation using the image data for three frames from the image memories 111 to 113 and the motion vector detected by the motion vector detection circuit 12.
The image data output from the interpolation circuit 1151 is supplied to the subtractor 212 and the adder 214, and the image data output from the interpolation circuit 1152 is supplied to the subtractor 212. The time axis enhancement circuit 21 of the fourth embodiment is substantially the same as the time axis enhancement circuit 20 ′ of the second embodiment.

  The motion compensated interpolation in the interpolation circuits 1151 and 1152 performs vector movement as shown in FIG. 12 because the frame frequency conversion ratio is 3/2 times. 12A shows input video signals to the interpolation circuits 1151 and 1152, and FIG. 12B shows output video signals from the interpolation circuits 1151 and 1152. Assume that the frame numbers of the input video signals are F1, F2, F3... And the frame numbers of the output video signals are f1, f2a, f2b, f3. Since the conversion from the frame F1 to the frame f1 and the conversion from the frame F3 to the frame f3 have the same time phase, no vector movement is performed. The frame f2a is vector-moved and inserted between the frames F1 and F2, and the frame f2b is vector-moved and inserted between the frames F2 and F3.

On the right side of FIGS. 12A and 12B, the movement of the object O across the frames F1 to F3 and the frames f1 to f3 is shown. In FIG. 12 (A), the object O is moved at vector V ₁ move to the position in the frame F2 from the position in the frame F1, moves upon vector V ₂ moves to a position in the frame F3 from the position in the frame F2. In FIG. 12B, the position of the object O in the frames f1 and f3 is the same as that in the frames F1 and F3, respectively. The position of the object O in the frame F2 is indicated by a broken line. To generate an image of the frame f2a may be moved to the image of the frame F2 by -V _1/3, to generate an image of the frame f2b is caused to move the image of the frame F2 by V _2/3 That's fine.

In the example shown in FIG. 12, when generating the frames f2a and f2b, only the image data of the frame F2 is used, but the image data of the frames F1 and F3 may be synthesized. In this case, for the frame f2a, F1 ′ obtained by moving the image of the frame F1 by V ₁ × 2/3 and F2 ′ obtained by moving the image of the frame F2 by −V ₁ × 1/3 are obtained, and F1 ′ and F2 ′ are obtained. It is obtained by mixing at a ratio of 1: 2. Also, for the frame f2b, F2 ″ obtained by moving the image of the frame F2 by V ₂ × 1/3 and F3 ′ obtained by moving the image of the frame F3 by −V ₂ × 2/3 are obtained, and F2 ″ and F3 ′ are set to 2 Obtained by mixing at a ratio of: 1.
The mixing ratio shown here is an example, and the present invention is not limited to this example. As described above, when the frame of the output video signal is generated, if interpolation is performed by adding not only the closest frame but also a frame adjacent thereto, an effect is obtained that noise can be reduced.

Here, the operation timing of the frame rate conversion circuit 11 will be described with reference to FIG. In FIG. 13, (A) is image data of an input video signal having a frame frequency of 60 Hz. Image data is read from the image memories 113 to 111 as shown in (B) to (D), and the frame frequency is 90 Hz. The video signal. For convenience, the timings of FIGS. 13B to 13F are shifted from the timing of FIG. 13A as indicated by the alternate long and short dash line.
As can be seen from FIGS. 13E and 13F, the image data output from the interpolation circuit 1152 is delayed by one frame from the image data output from the interpolation circuit 1151 at a frame frequency of 90 Hz. It has become. Thereby, in the fourth embodiment, it is not necessary to provide an image memory in the time axis emphasis circuit 21 as in the second embodiment.

As another example of the fourth embodiment, m / n is 4/3 times to convert the frame frequency to 80 Hz, m / n is 5/4 times to convert the frame frequency to 75 Hz, or m / n is For example, the frame frequency may be converted to 72 Hz by 6/5 times. According to the fourth embodiment, compared with the case where the means for shuttering the backlight described in Non-Patent Document 1 is used, it does not give an unstable factor to the display panel, which is advantageous. Further, as described above, the fourth embodiment does not place a heavy burden on the circuit operation, and is extremely effective in practical use.
As still another example of the fourth embodiment, the frame rate conversion circuit 11 and the time axis emphasis circuit 21 are configured to have a single interpolation circuit by using a selector as in the third embodiment of FIG. You can also.

1 is a block diagram showing a first embodiment of an image display device of the present invention. FIG. 2 is a block diagram illustrating a specific configuration example of a frame rate conversion circuit 10 in FIG. 1. It is a figure for demonstrating operation | movement of the frame rate conversion circuit 10 in FIG. It is a block diagram which shows the specific structural example of the time-axis emphasis circuit 20 in FIG. It is a figure for demonstrating the effect by 1st Embodiment. It is a figure for demonstrating the effect by 1st Embodiment. It is a partial block diagram which shows 2nd Embodiment of the image display apparatus of this invention. It is a timing diagram for demonstrating operation | movement of 2nd Embodiment. It is a partial block diagram which shows 3rd Embodiment of the image display apparatus of this invention. It is a block diagram which shows 4th Embodiment of the image display apparatus of this invention. It is a partial block diagram which shows the specific structural example of 4th Embodiment. It is a figure for demonstrating operation | movement of the frame rate conversion circuit 11 in FIG. It is a timing diagram for demonstrating the operation | movement of 4th Embodiment. It is a figure for demonstrating the moving image blurring which generate | occur | produces by hold type | mold display.

Explanation of symbols

10, 11 Frame rate conversion circuit 20, 21 Time axis enhancement circuit 30, 31 Drive circuit 40, 41 Liquid crystal panel (display panel)
101, 102, 111-113 Image memory 103, 114 Motion vector detection circuit 104, 1041, 1042, 1151, 1152 Interpolation circuit
1051, 1052 selector

Claims (2)

A plurality of pixels arranged in a matrix in an image display device using an active matrix type display panel for displaying holding a predetermined time an electrical signal to the image Motogoto,
A video signal having a first vertical frequency is m / n times the first vertical frequency (where m is an integer of 2 or more, n is an integer of 1 or more, and a condition of m> n is satisfied). A rate conversion circuit for converting to a second vertical frequency and outputting,
A time axis emphasizing circuit for emphasizing a high frequency component in the time axis direction using image data for two adjacent frames in the video signal having the second vertical frequency output from the rate conversion circuit;
A drive circuit for displaying the video signal having the second vertical frequency output from the time axis emphasizing circuit on the active matrix display panel ;
The rate conversion circuit
A plurality of image memories for writing a video signal having the first vertical frequency and outputting the video signal as the second vertical frequency;
A motion vector detection circuit for detecting a motion vector using image data output from the plurality of image memories;
The image data output from the plurality of image memories and the motion vector are used for motion compensation interpolation, and the second vertical frequency video signal that is shifted by one frame from each other is output. First and second interpolation circuits,
The time axis emphasis circuit is
An image display device characterized by emphasizing a high frequency component in a time axis direction using image data output from the first and second interpolation circuits as image data for two adjacent frames . In an image display device using an active matrix display panel having a plurality of pixels arranged in a matrix and displaying an electric signal for each pixel for a predetermined time,
A video signal having a first vertical frequency is m / n times the first vertical frequency (where m is an integer of 2 or more, n is an integer of 1 or more, and a condition of m> n is satisfied). A rate conversion circuit for converting to a second vertical frequency and outputting,
A time axis emphasizing circuit for emphasizing a high frequency component in the time axis direction using image data for two adjacent frames in the video signal having the second vertical frequency output from the rate conversion circuit;
A drive circuit for displaying the video signal having the second vertical frequency output from the time axis emphasizing circuit on the active matrix display panel;
The rate conversion circuit
A plurality of image memories for writing a video signal having the first vertical frequency and outputting the video signal as the second vertical frequency;
A motion vector detection circuit for detecting a motion vector using image data output from the plurality of image memories;
An interpolation circuit for performing motion compensation interpolation using the image data output from the plurality of image memories and the motion vector, and outputting the video signal of the second vertical frequency;
First and second output image data having a relationship shifted by one frame by selectively outputting image data output from the plurality of image memories and image data output from the interpolation circuit And a selector
The time axis emphasis circuit is
An image display device characterized by emphasizing a high frequency component in a time axis direction using image data output from the first and second selectors as image data for two adjacent frames .

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