JPH07261718A - Display system - Google Patents

Abstract

PURPOSE:To reduce the frequency band of the double speed video signal of an noninterlaced mode. CONSTITUTION:A double speed processing unit 1 converts the input video signals R, G, B of an interlaced mode into the double speed video signals WG, WG, WB of the noninterlaced mode according to a system clock SCK. A liquid crystal panel 2 has the multiple full-frame configuration of liquid crystal pixels arranged in a delta and performs the image display of the noninterlaced mode by receiving the double speed video signals according to a driving clock DCK. A clock controlling unit 3 allows the double speed precessing unit 1 and the liquid crystal panel 2 to be synchrinized by generating the system clock SCK and the driving clock DCK made to be synchronized each other on the basis of periodic components HD, VD included in the input video signals. The double speed processing unit 1 generates an interpolation video signal and also performs the offset sampling of the input video signals and the interpolation video signal to synthesizes the double speed video signal whose frequency band is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display system using an active matrix type liquid crystal panel. More specifically, the present invention relates to a video signal double-speed conversion technique that is required when a liquid crystal panel having delta pixels and having a full frame structure is non-interlaced driven.

[0002]

2. Description of the Related Art An active matrix type liquid crystal panel is capable of displaying moving images and is incorporated in a display system such as a television receiver. By the way, in the NTSC system, which is a television broadcasting standard in Japan, one screen (2
A frame) is configured and so-called interlaced driving is performed. The number of scanning lines in one frame is 525, and the frame frequency is 30 Hz. However, most of the small-sized liquid crystal television receivers currently commercialized have a horizontal scanning line number of 220 to 240 in the liquid crystal panel. This is NTSC
About half of the number of effective scanning lines in the system is used, and it has a half frame structure. Therefore, in the conventional liquid crystal television receiver, half-line driving which constitutes one screen by only one field of the video signal is performed. Although the vertical resolution is reduced in terms of image quality, since non-interlaced scanning is performed in half-line driving, the resolution is improved by about 30% compared to interlaced scanning when the number of scanning lines is the same. Taking this into consideration, the vertical resolution is reduced by 35% due to half-line driving.
It is estimated to be the degree. In a small screen of about 3 to 4 inches, the deterioration of the resolution has a small effect on the image quality.
Full line drive is strongly desired in a projection type liquid crystal television receiver that displays a large screen of 0 inch or more.
Currently, R & D is actively underway.

Recently, an active matrix type liquid crystal panel having a full frame structure, which has been prototyped recently, has nearly 480 pixels in the vertical direction, and can sufficiently display frame information contained in a video signal. By the way, in a full-color liquid crystal panel, pixels in a delta arrangement are generally adopted in order to improve color resolution. FIG. 9 shows an example of the delta array.
The three primary color pixels are arranged in the order of R, G, B along the row direction. The individual pixels are arranged at a predetermined pitch D.
In the adjacent rows, the set of R, G, and B is offset by (3/2) D and is in an offset arrangement. From a different point of view, focusing on a pair of upper and lower rows, three pixels R, G and B adjacent to each other are arranged at the vertices of a triangle, which is why this is called a delta array. A gate line X is provided along each row, and a signal line Y is provided so as to be orthogonal to the gate line X. A switching transistor is provided corresponding to each pixel, and its gate electrode is connected to the gate line X, its source electrode is connected to the signal line Y, and its drain electrode is connected to the pixel electrode. Each switching transistor is selected line-sequentially via a gate line X, and a video signal divided into R, G, and B color components is written via a signal line Y.

If an attempt is made to perform interlace drive on a liquid crystal panel having a full frame structure having such a delta arrangement as in the case of a CRT picture tube, the processing of the video signal becomes complicated and it is actually very difficult. Therefore, non-interlaced driving is suitable for a delta array full frame liquid crystal panel, and so-called double speed conversion is performed to create a non-interlaced signal from an original interlaced signal. Figure 10
Shows an example of a display system equipped with a double speed processor. The video signal input for each of the three primary color components (R, G, B) is A
After being digitized by the / D converter 101, it is supplied to the double speed processor 102. Here, the double speed conversion from the interlaced signal to the non-interlaced signal is performed. Generally, an interpolated video signal is created from an input video signal, and both are combined to form a double speed video signal. As a method of creating an interpolated video signal, there are a method of interpolating in a field using a line memory, a method of interpolating out of a field using a field memory, and a method of selectively using the two according to the motion of an image. Also, it is necessary to digitize the input video signal once and perform digital signal processing using some kind of memory. Double speed video signal is D / A converter 1
It is supplied to the analog processing circuit 104 in the subsequent stage via 03. This analog processing circuit performs gamma correction and brightness correction, for example. Thereafter, the double-speed video signal is passed through the inverting amplifier / buffer 105 to the liquid crystal panel 10
6 and non-interlaced driving is performed. As described above, this liquid crystal panel is an active matrix type having a delta array of pixels and a full frame structure.
A / D converter 101, double speed processor 102, D /
The A converter 103 operates according to the system clock output from the memory controller 107. On the other hand, the liquid crystal panel 106 operates according to the drive clock supplied from the timing generator 108. The memory controller 107 receives the horizontal synchronization signal HD and the vertical synchronization signal V based on the reference clock signal CK1 supplied from the oscillator 109.
The system clock described above is output in synchronization with D. On the other hand, the timing generator 108 has another oscillator 110.
The drive clock described above is output according to the reference clock signal CK2 input from the. A pair of oscillators 109 and 110
Are independent of each other.

[0005]

The problem to be solved by the invention will be briefly described with reference to FIG. Conventionally, the liquid crystal panel 106 and the double speed processor 102 (for example, ED
TV processing circuits) have been developed as completely independent components. Therefore, as shown in the figure, the clock signals used for both operations are often asynchronous with each other. When the double speed processor 102 and the liquid crystal panel 106 are controlled to operate asynchronously with each other, the required operating band of the analog processing circuit 104 and the inverting amplifier / buffer 105 interposed therebetween is determined according to the horizontal resolution of the liquid crystal panel 106. I will end up. For example, in a delta array color liquid crystal panel in which 800 pixels are horizontally arranged and 400 pixels are vertically arranged,
0 × 2/3 (delta arrangement) × 3/4 (aspect ratio) =
A horizontal resolution of 400 lines can be realized. The video signal according to this horizontal resolution has a band of 5 MHz or more, but becomes a band of 10 MHz or more after the double speed processing. Therefore, the analog processing circuit 104 and the inverting amplifier / buffer 105 are
An operating band above MHz is required. It is technically and economically very difficult to produce such a wideband signal processing circuit. Even if the liquid crystal panel 106 and the double speed processor 102 are synchronized with each other, if the input video signal is sampled out regardless of the pixel arrangement of the liquid crystal panel 106 on the double speed processor 102 side, And the situation is exactly the same.

[0006]

Means for Solving the Problems In order to solve the above-mentioned problems of the conventional technique, the following means were taken. That is, the display system according to the present invention has a double speed processor and an active matrix type liquid crystal panel as a basic configuration. The double speed processor double-speeds the input video signal in the interlaced mode in accordance with a predetermined system clock and converts it into a double-speed video signal in the non-interlaced mode. The liquid crystal panel has a full frame structure and operates in response to a predetermined drive clock to receive the double-speed video signal and display a non-interlaced mode image. As a feature of the present invention, the display system includes a clock controller, which generates a system clock and a drive clock which are synchronized with each other with reference to a periodic component included in the input video signal, the double speed processor and the liquid crystal. Synchronize panel behavior. The liquid crystal panel has a full frame structure including a set of liquid crystal pixels arranged in a delta arrangement. The double speed processor has a computing means and a synthesizing means. The arithmetic means generates an interpolated video signal based on the input video signal. The synthesizing means performs offset sampling of the input video signal and the interpolated video signal in accordance with the delta arrangement to synthesize a double speed video signal having a reduced frequency band.

Preferably, the synthesizing means samples the input video signal according to the delta arrangement and writes it in one line memory, and the synthesizing means also samples the interpolated video signal at a timing offset according to the delta arrangement and the other line memory. And a means for sequentially reading the contents of both line memories to generate a double speed video signal. The arithmetic means comprises a pair of field memories for sequentially recording input video signals in field units, and an interpolating means for simultaneously reading the contents of the pair of field memories and performing a predetermined arithmetic processing to generate an interpolated video signal. On the other hand, the clock controller has means for generating a system clock synchronized with a periodic component included in the input video signal, and means for generating a synchronized drive clock supplied with the system clock.

[0008]

According to the present invention, the system clock for operation of the double speed processor is synchronized with the drive clock of the liquid crystal panel, and offset synthesis in accordance with the delta arrangement of the liquid crystal panel is performed in the synthesizer of the double speed processor to perform double speed video. Generating a signal. The offset sampling makes it possible to reduce the sampling points of the input video signal and the interpolated video signal to less than half that of the conventional case. As a result, the band of the double-speed video signal becomes 1/2 or less as compared with the conventional one. In other words, it is possible to reduce the frequency band of the analog processing circuit or the like connected to the subsequent stage of the double speed processor to ½ or less.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. Before describing the preferred embodiment, the basic principles of the present invention will be briefly described. FIG. 2 and FIG. 3 show the minimum sampling points of the video signal required to achieve the desired resolution with the delta arrangement. FIG. 2 shows the case where the system clock of the double speed processor and the drive clock of the liquid crystal panel are asynchronous. (A) shows the sampling points in the odd field, and (B) shows the sampling points in the even field. The drawing focuses on one of the RGB three primary color components contained in the video signal. When the double speed processor and the liquid crystal panel are asynchronous with each other, simple sampling as shown in FIG. 2 must be performed at a frequency according to the sampling theorem. That is, in the first row of the odd field, the original video signal is sampled along the horizontal direction at the maximum pitch of 1.5D. In the figure, the original sampled video signal is represented by a circle. Note that D represents the pixel pitch shown in FIG. Next, in the second line, 1.
The interpolated video signal is sampled at a pitch of 5D. Here, the sampled interpolated video signal is represented by a triangle. Thereafter, the original video signal and the interpolated video signal are alternately sampled row by row. The 1.5D pitch corresponds to a sampling rate of 50 ns. On the other hand, as shown in (B), in the next even field, the interpolated video signal is sampled in the first row and the original video signal is sampled in the second row. Repeat this for each line.

FIG. 3 shows sampling points when the liquid crystal panel and the double speed processor are synchronized with each other according to the present invention. (A) corresponds to the odd field and (B) corresponds to the even field. According to the delta arrangement of the pixels included in the liquid crystal panel, the original video signal (white circle) and the interpolated video signal (△
By performing the offset sampling as shown in the figure,
It is possible to reduce the number of sampling points in each field to less than half. For example, in the odd field of (A), the original video signal is sampled at a 3D pitch in the first row. Referring to FIG. 9, for example, R pixels are arranged at a 3D pitch along the same row. The original video signal may be sampled exactly in accordance with this. Returning to FIG. 3 and continuing the explanation again, in the second row, the interpolated video signal is sampled at the same 3D pitch. However, the sampling point of the original video signal is shifted by a pitch of 1.5D. This corresponds to the fact that the R pixels are shifted from each other by a pitch of 1.5D in the first and second rows, as can be understood with reference to FIG. Of course, the same applies to the G pixel and the B pixel. The original sampling points of the video signal indicated by black circles are necessary for creating the sample data of the interpolated video signal indicated by Δ but are unnecessary data for the double speed video signal.
Similarly, in the even field of (B), offset sampling according to the delta arrangement is performed to synthesize the double-speed video signal whose frequency band is halved. However, the row corresponding to the original video signal and the row corresponding to the interpolated video signal are replaced with the case of the odd field.

A preferred embodiment of the display system according to the present invention will be described in detail with reference to FIG. The display system includes a double speed processor 1, a liquid crystal panel 2, and a clock controller 3. Double speed processor 1 has a predetermined system clock SCK
According to the input video signal (R,
G, B) is double-speed processed and converted into a double-speed video signal (WR, WG, WB) in the non-interlaced mode. The input video signal is preliminarily separated into three primary color components in the preprocessing stage, and each digitized via the A / D converter 4 and input to the post-speed processor 1. The liquid crystal panel 2 operates in response to a predetermined drive clock DCK to receive the above-mentioned double speed video signal and display a non-interlaced mode image. The liquid crystal panel 2 is composed of a set of liquid crystal pixels arranged in a delta array as shown in FIG. 9 and has a full frame structure. The liquid crystal panel 2 contains, in addition to liquid crystal pixels, a vertical scanning circuit and a horizontal scanning circuit for driving the liquid crystal pixels. In addition, the double speed processor 1
The double-speed video signal (WR, WG, WB) output from is returned to the analog signal through the D / A converter 5, and then is transferred to the liquid crystal panel 2 through the analog processing circuit 6, the inverting amplifier 7, and the buffer 8. Is entered. The analog processing circuit 6 includes, for example, a brightness circuit and a gamma correction circuit.
The inverting amplifier 7 is for inverting the double-speed video signal, for example, every horizontal period in order to drive the liquid crystal panel 2 with an alternating current. The clock controller 3 generates a system clock SCK and a drive clock DCK which are synchronized with each other on the basis of the periodic components (horizontal synchronizing signal HD and vertical synchronizing signal VD) separated in advance from the input video signal. As a result, the operations of the double speed processor 1 and the liquid crystal panel 2 are synchronized. This clock controller 3 has a horizontal synchronizing signal H.
D and the system clock S synchronized with the vertical synchronization signal VD
It has a memory controller 31 that generates CK and a timing generator 32 that receives the control and generates a synchronized drive clock DCK.

The double speed processor 1 includes an arithmetic circuit 11 and a synthesis circuit 1.
Equipped with 2. The arithmetic circuit 11 receives the input video signal (R,
G, B) to generate an interpolated video signal. The synthesizing circuit 12 performs offset sampling of the original video signal and the interpolated video signal in accordance with the delta arrangement of the liquid crystal panel 2 to reduce the frequency band by half to the double speed video signal (W
R, WG, WB) is output. This offset sampling method is as described above with reference to FIG.
Since the frequency band of the double-speed video signal is halved, it is possible to reduce the operating band of the analog processing circuit 6 and the inverting amplifier 7 connected to the subsequent stage. The synthesizing circuit 12 has, for example, a means for sampling the original video signal according to the delta arrangement and writing it in one line memory, and a means for sampling the interpolated video signal at a timing offset according to the delta arrangement and writing it in the other line memory. , Means for sequentially reading the contents of both line memories to generate a double speed video signal. On the other hand, arithmetic circuit 1
A first field memory 13 and a second field memory 14 are connected to 1 and input video signals (R, G,
B) is sequentially recorded in field units. The contents of the pair of field memories 13 and 14 are simultaneously called to perform a predetermined arithmetic processing to generate an interpolated video signal.

Next, with reference to FIGS. 4 to 6, specific processing contents in the double speed processor 1 shown in FIG. 1 will be described in detail. FIG. 4A shows the input video signal recorded in the first field memory 13. In the figure, the video signal corresponding to the nth field is recorded,
It represents one of the R, G, and B components. The first field memory 13 has an address of m columns × 263 rows, and the sampled input video signal An (x, y) is recorded therein. The input video signal is converted into digital data in synchronization with the driving clock of the liquid crystal panel and stored in the first field memory 13. The sample timing along the row direction corresponds exactly to a pitch of 1.5D. The value of m is determined by the number of pixels of the liquid crystal panel. When the number of horizontal pixels is p, m is calculated by the following mathematical formula. However, t _M represents a horizontal period, and t
_E represents the horizontal effective period, and L represents the overscan amount.

[Equation 1]

Next, FIG. 4B shows an input video signal stored in the first field memory 13 and corresponding to the (n + 1) th field. Each sampled data is represented by An + 1 (x, y). In this way, the first field memory 13 sequentially records the input video signal in field units. On the other hand, the second field memory 14 stores the input video signal delayed by one field from the first field memory 13.

Next, as shown in FIG. 5, one line memory is used to take out sample data for one line from the first field memory 13. The other line memory is used to retrieve the sample data of the same line from the second field memory 14. That is, the sample data delayed by one field for the same line is stored in both line memories side by side for one horizontal period. The arithmetic circuit 11 shown in FIG. 1 performs predetermined arithmetic processing between the pair of sample data An (x, y) and An-1 (x, y) to create an interpolated video signal. For example,
An interpolation video signal can be obtained by multiplying each of An (x, y) and An-1 (x, y) by an appropriate coefficient and then adding them. In the simplest calculation, the delayed sample data An-1 (x, y) can be used as it is as an interpolation video signal. In this example, this simplest interpolation method is adopted for easy understanding.

FIG. 6 shows a synthesis circuit 1 included in the double speed processor 1.
2 represents the operation. As described above, the sample data An (x, y) stored in one line memory is treated as an original video signal, and the sample data An-1 (x, y) stored in the other line memory is interpolated. Treated as a video signal. First, even-numbered sample data are sequentially taken out from the interpolated video signal and arranged. Next, only odd-numbered sample data are sequentially taken out from the original video signal and arranged. As described above, offset sampling corresponding to the delta array can be executed,
The desired double speed video signal is obtained.

FIG. 7 is a block diagram showing a concrete configuration example of the synthesis circuit 12. The synthesizing circuit 12 includes an input gate switch 121, an output gate switch 122, and a pair of line memories 123 and 124 interposed therebetween. The input gate switch 121 receives the original video signal and the interpolated video signal from the arithmetic circuit 11, and switches the both for each field according to the field signal. The output gate switch 122 alternately switches the outputs of the first line memory 123 and the second line memory 124 according to the selection signal and outputs a double speed video signal. The first line memory 123 is of a type in which writing and reading can be performed independently, and the operation is controlled according to the write clock 1 and the read clock 1. Second line memory 12
Similarly, 4 can write and read independently, and its operation is controlled by the write clock 2 and the read clock 2.

The operation of the synthesis circuit 12 shown in FIG. 7 will be described in detail with reference to the timing chart of FIG. As shown in the figure, the original video signal latched for each line consists of a sample data string from An (1, y) to An (m, y). However, m is set to an even number here.
The first line memory 123 writes the original video signal in synchronization with the rising edge of the write clock 1.
Therefore, the first line memory 123 stores only odd-numbered sample data. The first line memory 123 reads the original video signal in synchronization with the rising edge of the read clock 1 which is twice as fast as the write clock 1. The first line memory 123 is prohibited from being read in the first half of one horizontal cycle by the read operation control signal 1, and can be read only in the latter half.

On the other hand, the interpolated video signals output from the arithmetic circuit 11 are An-1 (1, y) to An-1 (m,
y) up to the sampling data string. The second line memory 124 writes and stores the interpolated video signal in synchronization with the rising edge of the write clock 2. Therefore, only the even-numbered sample data of the interpolated video signal is written. On the other hand, the read clock 2 is twice as fast as the write clock 2, and the interpolated video signal written in the second line memory 124 is read out in synchronization with the rising edge. The second line memory 124 is controlled by the read operation control signal 2, and the first half of one horizontal period can be read, but the second half is prohibited. Output gate switch 1
22 selects the output from the second line memory 124 in the first half of one horizontal cycle in accordance with the selection signal, and also selects the first output in the second half.
The output from the line memory 123 is selected. As a result,
The output gate switch 122 can output a desired double speed video signal. In the above signal processing, the portion for performing offset sampling corresponding to the delta array is writing to the pair of line memories 123 and 124. The original video signal and the interpolated video signal are respectively supplied to the line memories 123 and 12 by two kinds of write clock 1 and write clock 2 which are 180 ° out of phase with each other in a 2-bit period.
Offset sampling is realized by writing in 4 independently.

[0020]

As described above, according to the present invention, the double-speed video signal having the frequency band reduced by performing the offset sampling of the input video signal and the interpolated video signal in accordance with the delta arrangement of the pixels included in the liquid crystal panel. Is being synthesized. As a result, in the double speed processor that performs digital processing, the system clock can be reduced to half or less of the conventional one, and the memory capacity can be suppressed to half or less. Further, in the analog processing circuit connected to the subsequent stage of the double speed processor, the operating band can be reduced, which facilitates the circuit design and contributes to the reduction of power consumption. Further, it is possible to obtain an effect that beat noise due to the fact that the double speed processing and the liquid crystal panel driving are asynchronous with each other can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific configuration example of a display system according to the present invention.

FIG. 2 is an explanatory diagram showing a conventional double speed processing method.

FIG. 3 is an explanatory diagram showing a double speed processing method according to the present invention.

FIG. 4 is a table diagram for explaining the operation of the display system shown in FIG.

FIG. 5 is a data format diagram similarly provided for explaining the operation.

FIG. 6 is a data format diagram similarly provided for explaining the operation.

7 is a block diagram showing a specific configuration example of a combining circuit incorporated in the display system shown in FIG.

FIG. 8 is a timing chart for explaining the operation of the synthesizing circuit shown in FIG.

FIG. 9 is a schematic diagram showing a delta arrangement of pixels included in a liquid crystal panel.

FIG. 10 is a block diagram showing an example of a conventional display system.

[Explanation of symbols]

 1 Double Speed Processor 2 Liquid Crystal Panel 3 Clock Controller 4 A / D Converter 5 D / A Converter 6 Analog Processing Circuit 7 Inversion Amplifier 8 Buffer 11 Arithmetic Circuit 12 Synthesis Circuit 13 First Field Memory 14 Second Field Memory 31 Memory Controller 32 Timing generator

Claims (4)

[Claims] 1. A double speed processor that double-speeds an input video signal in an interlaced mode according to a predetermined system clock and converts it into a double-speed video signal in a non-interlaced mode; and a double speed processor that operates according to a predetermined drive clock. A display system having a full frame active matrix liquid crystal panel for receiving a video signal and displaying an image in a non-interlaced mode, the display system including a clock controller, wherein a periodic component contained in the input video signal is used as a reference. As a result, the system clock and the drive clock that are synchronized with each other are generated to synchronize the operations of the double speed processor and the liquid crystal panel, and the liquid crystal panel has a full frame configuration including a set of liquid crystal pixels in a delta arrangement. The double speed processor generates an interpolated video signal based on the input video signal. And a synthesizing means for performing offset sampling of the input video signal and the interpolated video signal in accordance with the delta arrangement to obtain a double speed video signal with a reduced frequency band. 2. The synthesizing means samples the input video signal according to the delta arrangement and writes it in one line memory, and the synthesizing means samples the interpolated video signal at the same offset timing according to the delta arrangement and stores it in the other line memory. 2. The display system according to claim 1, comprising writing means and means for sequentially reading the contents of both line memories to generate a double speed video signal. 3. The pair of field memories for sequentially recording input video signals in field units, and the interpolating means for simultaneously reading out the contents of the pair of field memories and performing predetermined arithmetic processing to generate an interpolated video signal. The display system according to claim 1, wherein the display system comprises: 4. The clock controller has means for generating a system clock synchronized with a periodic component included in an input video signal, and means for generating a synchronized drive clock under the control of the system clock. The display system according to claim 1.