WO2007013718A1

WO2007013718A1 - Clock signal embedded multi-level signaling method and apparatus for driving display panel using the same

Info

Publication number: WO2007013718A1
Application number: PCT/KR2005/003620
Authority: WO
Inventors: Yong Jae Lee
Original assignee: Anapass Inc.
Priority date: 2005-07-28
Filing date: 2005-10-31
Publication date: 2007-02-01
Also published as: TW200705363A; TWI311305B

Abstract

The present invention relates a clock signal embedded multi-level signaling method and an apparatus for driving display panel using the same, wherein the method comprises steps of: converting a data to a signal having a smaller voltage than that of a predetermined reference voltage; converting a clock to a signal having a larger voltage than that of the predetermined reference voltage; and multiplexing the converted clock signal and the converted data signal by embedding the converted clock signal between the converted data signal.

Description

CLOCK SIGNAL EMBEDDED MULTI-LEVEL SIGNALING METHOD AND APPARATUS FOR DRIVING DISPLAY PANEL

USING THE SAME

Technical Field

[1] The present invention relates to a clock signal embedded multi-level signaling method and an apparatus for driving display panel using the same, and more particularly to a clock signal embedded multi-level signaling method and an apparatus for driving display panel using the same wherein a clock signal in a transmission of a display panel driving apparatus is embedded.

[2]

Background Art

[3] Recently, in addition to an increase in a popularization of portable electronic devices such as a notebook computer and a personal portable communication device, a market size of digital appliances and personal computers is constantly increased. Display apparatuses which are final connection medium between such devices and users is required to have a light weight and low power consumption. Therefore, FPDs (Rat Panel Displays) such as an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel) and an OELD (Organic Electro-Luminescence Display) are generally used instead of a conventional CRT (Cathode Ray Tube).

[4] As described above, in case of generalized FPD system, a timing controller and a driver IC for driving panel (scan driver integrated circuit and column driver integrated circuit) are required for driving a panel that is used for display. However, a large amount of a problematic wave interference caused in an electronic device by an electromagnetic wave and a radio frequency wave so-called an EMI (electromagnetic interference) or an RFI (radio frequency interference) (hereinafter commonly referred to as "EMI") is generated in a line for transmitting a data signal between the timing controller and the driver IC for driving panel.

[5] Moreover, in case of current FPD system, a large screen and a high resolution are constantly pursued, and in case of a high resolution panel in particular, since the number of a column line is from a few hundreds to two thousand, an input to the column driver integrated circuit for driving each of these lines requires a high speed data transmission technology.

[6] As described above, since an EMI standard is reinforced recently, and a technology for transmitting a signal in a high speed is far more required, a small signal differential signaling method such as an RSDS (Reduced Swing Differential Signaling) or a mini- LVDS is commonly used in an intra-panel display for connecting the timing controller and the panel resultantly.

[7] Fig. 1 is a schematic diagram illustrating an embodiment of a conventional

RSDS(Reduced Swing Differential Signaling), and Fig. 2 is a schematic diagram illustrating an embodiment of a conventional mini-LVDS(Low Voltage Differential Signaling). The RSDS and mini-LVDS both comprise one or more data signal lines to meet a required bandwidth using a separate clock signal synchronized to a data. Since only one clock signal is used, the clock signal and the data signals must be provided to match the number of the column driver integrated circuits 20 and 21 inside the panel. That is, as shown in Figs. 1 and 2, the RSDS and the mini-LVDS both employ a multidrop method.

[8] However, the multi-drop method employed by both the RSDS and the mini-LVDS is disadvantageous in that a maximum operating speed is limited due to a large load of the clock signal as well as an increase in EMI and degradation of quality of the signal such as a signal distortion due to impedance mismatch at a point where lines are split.

[9] An intra-panel interface employing a point-to-point method recently announced by

National Semiconductor Corporation is a PPDS (Point-to-Point Differential Signaling). In accordance with this method shown in Fig. 3, clock signals are transmitted to each of column driver integrated circuits 22 to solve a problem that occurs when the clock signal is shared by the column driver integrated circuit 22. Moreover, this method is characterized in that an independent data line is disposed between a timing controller and a single column driver integrated circuit 22 while a plurality of data lines are connected to a plurality of column driver integrated circuits conventionally. That is, as a serial method is employed to the PPDS as shown in Fig. 3, a single independent data line is disposed from a PPDS timing controller 12 toward the single column driver integrated circuit 22.

[10] Therefore, the impedance mismatch is reduced compared to the conventional multi-drop method employed by the RSDS and the mini-LVDS so that EMI is reduced and a low manufacturing cost is achieved by reducing the number of total signal line.

[11] However, a higher speed clock signal compared to the conventional RSDS is required, and separate clock lines are connected to all of the column driver integrated circuit respectively so that an overhead exists. Moreover, when a skew between a clock signal for sampling data and a data signal exists, an error may occur during a data sampling process. In order to prevent this, a separate circuit for compensating the skew is necessary. Therefore, the PPDS has problems different from the conventional RSDS and the mini-LVDS that should be solved.

[12] In addition, as shown in Fig. 4, a configuration wherein a column driver integrated circuit 23 receives a clock signal in a chain form has been recently proposed. Such configuration is advantageous in that an impedance mismatch due to a multi-drop of a clock line and a resulting EMI can be reduced. However, this configuration is problematic that a data sampling is failed due to a delay of a clock occurring between the column driver integrated circuit 23.

[13]

Disclosure of Invention Technical Problem

[14] As described above, the latest trend in the intra-panel interface is focused on reducing the number of signal lines and EMI component. In addition, an operating speed and a resolution of a panel are increased compared with the reduction of the number of signal lines so that a novel intra-panel interface that can solve problems such as the skew and the relative jitter occurring during a high speed signal transmission process is required.

[15]

Technical Solution

[16] It is an object of the present invention to provide a clock signal embedded multilevel signaling method and an apparatus for driving display panel using the same that are used for a signal transmission (data and clock transmission) between a timing controller and a column driver integrated circuit wherein the number of the signal line and EMI are remarkably reduced and a data sampling is accurately carried out through a restored clock.

[17] The other objects and advantages of the present invention will be described in the following and illustrated by embodiments of the present invention. In addition, the objects and advantages of the present invention is embodied by means and combination thereof disclosed in Claims.

[18] In accordance with first aspect of the present invention, there is provided a method for multi-level signaling having a clock signal embedded therein used at a transmitting terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising steps of: converting a data to a signal having a smaller voltage than that of a predetermined reference voltage; converting a clock to a signal having a larger voltage than that of the predetermined reference voltage; and multiplexing the converted clock signal and the converted data signal by embedding the converted clock signal between the converted data signal.

[19] In accordance with second aspect of the present invention, there is provided a method for multi-level signaling having a clock signal embedded therein used at a receiving terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising restoring a received signal to a clock when a voltage of the received signal is larger than that of a reference voltage and restoring the received signal to a data when the voltage of the received signal is smaller than that of the reference voltage.

[20] In accordance with third aspect of the present invention, there is provided a method for multi-level signaling having a clock signal embedded therein used at a transmitting terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising steps of: converting a data to a signal having a larger voltage than that of a predetermined reference voltage; converting a clock to a signal having a smaller voltage than that of the predetermined reference voltage; and multiplexing the converted clock signal and the converted data signal by embedding the converted clock signal between the converted data signal.

[21] In accordance with fourth aspect of the present invention, there is provided a method for multi-level signaling having a clock signal embedded therein used at a receiving terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising restoring a received signal to a data when a voltage of the received signal is larger than that of a reference voltage and restoring the received signal to a clock when the voltage of the received signal is smaller than that of the reference voltage.

[22] In accordance with fifth aspect of the present invention, there is provided a driving apparatus comprising a timing controller, a plurality of column driver integrated circuits and at least one row driver integrated circuit, wherein a differential pair is connected between the timing controller and each of the plurality of the column driver integrated circuits for transmitting a data signal and a clock signal from the timing controller to the plurality of the column driver integrated circuits and wherein the clock signal is embedded between the data signal to have a different signal magnitude from the data signal and is transmitted.

[23] In accordance with sixth aspect of the present invention, there is provided a driving apparatus comprising a timing controller, a plurality of column driver integrated circuits and at least one row driver integrated circuit, wherein a differential pair is connected between the timing controller and at least two of the plurality of the column driver integrated circuits for transmitting a data signal and a clock signal from the timing controller to the at least two column driver integrated circuits and wherein the clock signal is embedded between the data signal to have a different signal magnitude from the data signal and is transmitted. Advantageous Effects [24] As described above, in accordance with the clock signal embedded multi-level signaling method and an apparatus for driving display panel using the same of the present invention, an embodiment of a higher speed data transmission technology is achieved, and the number of lines can be reduced compared to the conventional art, thereby improving EMI characteristic. In addition, a de-skew block is not necessary, a relative jitter problem is solved while a more accurate data sampling is achieved through the restored clock and a problem of a signal delay is solved in accordance with the present invention.

[25]

Brief Description of the Drawings

[26] Fig. 1 is a schematic diagram illustrating an embodiment of a conventional

RSDS(Reduced Swing Differential Signaling).

[27] Fig. 2 is a schematic diagram illustrating an embodiment of a conventional mini-

LVDS(Low Voltage Differential Signaling).

[28] Fig. 3 is a schematic diagram illustrating an embodiment of a conventional

PPDS(Point-to-Point Differential Signaling).

[29] Fig. 4 is a schematic diagram illustrating a method for receiving a clock signal in series from a neighboring column driver integrated circuit in the RSDS wherein the column driving circuit is configured to have a chain structure.

[30] Fig. 5 is a diagram illustrating a structure of a clock embedded intra-panel display in accordance with a first embodiment of the present invention.

[31] Fig. 6 is a diagram illustrating only a transmission structure of a clock and a data between a timing controller and column driver integrated circuits of Fig. 5 for convenience of comprehension.

[32] Figs. 7 through 10 is diagrams illustrating examples of a multi-level signaling that can be used for an interface between the timing controller and the column driver integrated circuits of Fig. 5.

[33] Fig. 11 is a diagram illustrating a structure of a clock embedded intra-panel display in accordance with a second embodiment of the present invention.

[34] Fig. 12 is a diagram illustrating only a transmission structure of a clock and a data between a timing controller and column driver integrated circuits of Fig. 11 for convenience of comprehension.

[35]

Best Mode for Carrying Out the Invention

[36] The present invention will now be described in detail with reference to the accompanied drawings. The interpretations of the terms and wordings used in Description and Claims should not be limited to common or literal meanings. The inter- pretation should be made to meet the meanings and concepts of the present invention based on the principle that the inventor or inventors may define the concept of the terms so as to best describe the invention thereof. Therefore, while the present invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be effected therein without departing from the spirit and scope of the invention as defined by the appended claims.

[37] In accordance with the present invention, a conventional multi-level signaling method is applied so as to provide a novel coding method wherein a clock signal information is embedded between data signals without and instead of a separate clock signal line, thereby resolving problems of conventional technologies such an impedance mismatching due to a multi-drop of a data line and a clock line and a resulting EMI.

[38] In addition, in accordance with the present invention, the clock signal component can facilely extracted from the clock signal embedded in the data signal line using a multi-level detection method, and the clock signal component is only one-tenths of a frequency necessary for sampling of an actual data. Therefore, this plays a major role in reducing EMI of an entire system since the frequency is small, and a relative jitter or skew problem generated when the data signal and the clock signal are separate can be prevented to perform a stable operation in a high speed.

[39] [First embodiment]

[40] Fig. 5 is a diagram illustrating a structure of a clock embedded intra-panel display in accordance with a first embodiment of the present invention, and Fig. 6 is a diagram illustrating only a transmission structure of a clock and a data between a timing controller and column driver integrated circuits of Fig. 5 for convenience of comprehension. Referring to Figs. 5 and 6, a display comprises a timing controller 14, a plurality of column driver integrated circuits 24, a plurality of row driver integrated circuits 30 and a display panel 40. A driving apparatus for the display panel 40 comprises the timing controller 14, the plurality of column driver integrated circuits 24 and the plurality of row driver integrated circuits 30.

[41] The display panel 40 serves as a part for displaying an image according to a scanning signal and a data signal and may be selected from various display panels such as a LCD panel, a PDP panel and an OELD panel. The plurality of row driver integrated circuits 30 apply scan signals Sl through Sn to the display panel 40, and the plurality of column driver integrated circuits 24 applies data signals Dl through Dn to the display panel 40. The timing controller 14 transmits DATA to the plurality of column driver integrated circuits 24, and applies clocks CLK and CLK_R and start pulses SP and SP_R to the plurality of column driver integrated circuits 24 and the plurality of row driver integrated circuits 30. DATA transmitted from the timing controller 14 to the plurality of column driver integrated circuits 24 may comprises only an image data that is to be displayed on the display panel 40 or the image data and a control signal.

[42] Contrary to the conventional technology, in accordance with the first embodiment of the present invention, only one pair of differential pair is used to transmit the clock CLK and the data signal DATA from the timing controller 14 to the column driver integrated circuit 24. The clock signal CLK is embedded between the data signal DATA to have a different signal magnitude at the timing controller 14 which is a transmitting terminal and transmitted. The clock signal CLK is distinguished from the data signal DATA using the magnitude of a received signal at the column driver integrated circuit 24 which is a receiving terminal.

[43] Fig. 7 is a diagram illustrating an example of a multi-level signaling that can be used for an interface between the timing controller and the column driver integrated circuits of Fig. 5. Referring to Figs. 5 through 7, the timing controller 14 converts the data to a signal having a smaller voltage than that of a predetermined reference voltage, a clock to a signal having a larger voltage than that of the predetermined reference voltage, and embeds the converted clock signal between the converted data signal to multiplex and then transmits. In addition, values of the data signals can be obtained at the column driver integrated circuit 24 which is the receiving terminal by a differential signal processing well-known in the art, and the clock signal is distinguished using Vrefh and Vrefl. That is, when an absolute value of difference between two input signals I Vin,p - Vin,nl is smaller than a magnitude of the reference signal IVrefh - Vrefll, the two input signals are processed as the data signal. Therefore, when Vin,p is larger than Vin,n, the data values is set to 1 and when Vin,p is smaller than Vin,n, the data values is set to 0. When the absolute value of difference between the two input signals is larger than the magnitude of the reference signal (I Vin,p - Vin,nl > IVrefh - Vrefll), the two input signals are recognized as the clock.

[44] As shown in the figures, since a frequency of an actually embedded clock is lower than a transmission speed of the data, the receiving terminal generates a clock signal having the same speed as that of the data using a PLL (not shown), and the data is sampled using the same. In an aspect of an EMI of the system, the most important factor is the clock signal, and a magnitude of the EMI is known to be proportional to a magnitude and a frequency of the clock signal. Therefore, in accordance with the present invention, the frequency of the clock may be reduced to 1/10 or 1/20 of the conventional PPDS system, thereby remarkably reducing EMI.

[45] In addition, when the clock is restored from the data and the clock signal configuration shown in the figures, the clock is restored in a naturally synchronized state with the data. Therefore, when a sampling is performed using the restored clock, it is advantageous in that the data sampling may be performed more accurately compared to the conventional LVDS, mini-LVDS and PPDS.

[46] Moreover, as shown in the figures, while the number of combinations of signals that can actually be represented is four, the desired signals are two data signals and one click signal. Therefore, when an absolute value of difference between two input signals IVin,p - Vin,nl is larger than a magnitude of the reference signal IVrefh - Vrefll, the clock signal is unconditionally generated while a separate control signal or an image data may be transmitted simultaneously using sign of the two signals. When the sign is positive, it is recognized that 1 is applied, and when the sign is negative, it is recognized that 0 is applied.

[47] Fig. 8 is a diagram illustrating another example of a multi-level signaling that can be used for an interface between the timing controller and the column driver integrated circuits of Fig. 5.

[48] Referring to Figs. 5, 6 and 8, the timing controller 14 converts the data to a signal having a larger voltage than that of a predetermined reference voltage, a clock to a signal having a smaller voltage than that of the predetermined reference voltage, and embeds the converted clock signal between the converted data signal to multiplex and then transmits. In addition, the column driver integrated circuit 24 which is a receiving terminal restores a received signal to the data when a voltage of the received signal is larger than that of a reference voltage and to the clock when the voltage of the received signal is smaller than that of the reference voltage.

[49] As shown in the figures, since the clock signal does not have a concept such as 1 and 0 contrary to the data, a three multi-level is sufficient for the multi-level signaling. That is, when an absolute value of difference between two input signals IVin,p - Vin,nl is larger than a magnitude of the reference signal IVrefh - Vrefll, the two input signals are recognized as the data signal, and the data is recognized as 1 or 0 according to a sign of the data signal. On the contrary, when an absolute value of difference between two input signals I Vin,p - Vin,nl is smaller than a magnitude of the reference signal IVrefh - Vrefll, the two input signals are recognized as the clock signal. Therefore, contrary to the method of Fig. 7 which requires 3 Vx ( Vx refers to a noise margin) voltage operation due to requirement of four multi-level, the method of Fig. 8 may be operated at a low voltage of 2 Vx since three multi-levels are sufficient for the method of Fig. 8.

[50] Fig. 9 is a diagram illustrating yet another example of a multi-level signaling that can be used for an interface between the timing controller and the column driver integrated circuits of Fig. 5.

[51] In case of examples shown in Figs. 7 and 8, although the clock signal is transmitted with the data, a clock restoring circuit consisting of a DLL, a PLL or the like is required at the receiving terminal as the clock signal does not exist for every data. A column driver integrated circuit of a large LCD is not affected by an increase in an area or a current due to DLL and the like. However, in case of a column driver integrated circuit of a small LCD, these may be problematic. Moreover, when the a transmission speed of the data is not very high, it is advantageous to configure the clock restoring circuit to be simple by transmitting the clock with every data.

[52] The method shown in Fig. 9 is to resolve these problems. Although the method shown in Fig. 9 is similar to Figs. 7 and 8 in the aspect of multi-level, it differs in that the clock signal is transmitted during a period corresponding to one half of the data period. When an absolute value of difference between two input signals I Vin,p - Vin,nl is larger than a magnitude of the reference signal IVrefh - Vrefll, the two input signals are recognized as the data signal, and the data is recognized as 1 or 0 according to a sign of the data signal. On the contrary, when an absolute value of difference between two input signals I Vin,p - Vin,nl is smaller than a magnitude of the reference signal IVrefh - Vrefll, the two input signals are unconditionally recognized as the clock signal.

[53] As shown in the restored data and clock signal, the clock signal is positioned in a middle of each data transition period. The object of the clock restoring circuit is to place the clock at a most ideal position for sampling, i.e. in the middle of the data transition period, and it is obvious that the signal configuration of the present invention satisfies this. That is, the period of the data signal is halved while the length of the clock signal is configured to be identical to that of the data so that the clock signal is restored for each of the data at the receiving terminal. Through such process, the received data signal can be restored by a simple sampling circuit.

[54] In accordance with the structure shown in Fig. 9, a sign of the received data is changed only when the received data is beyond a threshold value. That is, the value is changed according to the sign of the data only when an absolute value of a difference of two input signals I Vin,p - Vin,nl is larger than a magnitude of the reference signal IVrefh - Vrefll.

[55] Contrary to this, two configurations are possible for the clock. Firstly, similar to the data, in case a polarity is changed only when an absolute value of a difference of two input signals I Vin,p - Vin,nl is smaller than a magnitude of the reference signal IVrefh - Vrefll, the data may be sampled at both a rising edge and a falling edge of the clock signal. Secondly, contrary to the above case, when case of the absolute value of the difference of the two input signals I Vin,p - Vin,nl being larger than a magnitude of the reference signal IVrefh - Vrefll and case of the absolute value of the difference of the two input signals I Vin,p - Vin,nl being smaller than a magnitude of the reference signal IVrefh - Vrefll are regarded as a transition period of the clock, the data is sampled at the rising edge of the clock signal as shown in Fig. 9.

[56] Although description has been focused on a case of the clock signal being smaller than the data signal referring to Fig. 9, embedding the clock signal to each of the data signal may be applied when the magnitude of the clock signal is larger than that of the data signal, which can be facilely understood by a person skilled in the art. Therefore, a detailed description regarding this matter is omitted.

[57] Fig. 10 is a diagram illustrating yet another example of a multi-level signaling that can be used for an interface between the timing controller and the column driver integrated circuits of Fig. 5.

[58] Referring to Fig. 10, a polarity of the clock signal follows that of a previous data.

That is, a data n-1 and the clock have the same polarity, and a tail bit of the clock is added to additionally generate a signal of a dummy data identical to the previous data signal (data n-1).

[59] A sufficient rising time and falling time can be obtained through the dummy data.

The dummy data is added to prevent the clock from being speeded up or delayed depending on a form of the previous data in case of Fig. 7. Therefore, in such case, because a possibility of generation of a jitter due to a slew rate between a transition of the data and a transition which is recognized as the clock signal is waived, it is advantageous in that a stable operation is secured in high speed transmission.

[60] That is, while a position of a zero-crossing for generating the clock signal is dependent on a value of the previous data in case of Fig. 7, it is advantageous in that zero-pattern dependent jitter is not generated in case of Fig. 10.

[61] [Second embodiment]

[62] Fig. 11 is a diagram illustrating a structure of a clock embedded intra-panel display in accordance with a second embodiment of the present invention, and Fig. 12 is a diagram illustrating only a transmission structure of a clock and a data between a timing controller and column driver integrated circuits of Fig. 11 for convenience of comprehension.

[63] Comparing the first embodiment and the second embodiment, the second embodiment employs a point-to-couple scheme while the first embodiment point- to-point scheme. Since the second embodiment is identical to the first embodiment except that the second embodiment employs the point-to-couple scheme, the multilevel signaling method that may be used for an interface between the timing controller and the column driver integrated circuit described referring to Figs. 7 through 10 may be applied to the second embodiment. However, while one differential pair is connected to one column driver integrated circuit in case of the first embodiment, one differential pair is connected to two column driver integrated circuits 25 in case of the second embodiment. Therefore, an amount of data transmitted through the differential pair in case of the second embodiment is increased to twice as much as an amount in case of the first embodiment.

[64] The display panel of the present invention described above includes various display panels wherein the clock signal embedded multi-level signaling method of the present invention can be used between the timing controller and the display driver integrated circuit (DDI) such as a TFT-LCD (TFT Liquid Crystal Display), a STN-LCD, a Ch- LCD, a FLCD (Ferroelectric Liquid Crystal Display), a PDP (Plasma Display Panel), an OELD (Organic Electro-Luminescence Display) and a FED.

[65] In addition, it is obvious that a multi-level detector used for restoration of the clock and the data of the present invention may be embodied using a common multi-level detector well-known to the skilled in the art.

[66] Moreover, a unit of the frequency f of the clock may be identical to a frequency of the data to be multiplexed, and the clock signal may be included for each of the data to be multiplexed. The frequency f of the clock may be 1/10 or 1/20 of the frequency of the data to be multiplexed. Therefore, according to the frequency f of the clock signal, a frequency of the restored clock signal may be increased using the DLL or PLL, or the restored clock signal may be used for the data sampling as is without using DLL or PLL when each of the data includes one clock signal.

Claims

[1] A method for multi-level signaling having a clock signal embedded therein used at a transmitting terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising steps of: converting a data to a signal having a smaller voltage than that of a predetermined reference voltage; converting a clock to a signal having a larger voltage than that of the predetermined reference voltage; and multiplexing the converted clock signal and the converted data signal by embedding the converted clock signal between the converted data signal.

[2] The method in accordance with claim 1, wherein the data comprises a control signal and an image data to be displayed on the display panel.

[3] The method in accordance with claim 1, wherein the data comprises only an image data to be displayed on the display panel.

[4] The method in accordance with claim 1, wherein the step of converting the data to the signal having the smaller voltage corresponds to IVrefh Vrefll > IVdoh Vdoll, and the step of converting a clock to a signal having the larger voltage corresponds to IVcoh Vcoll > IVrefh - Vrefll where Vrefh is a maximum value of the reference voltage, Vrefl is a minimum value thereof, Vdoh is a maximum voltage of the data signal converted to the smaller voltage, Vdol is a minimum voltage thereof, Vcoh is a maximum voltage of the clock signal converted to the larger voltage and Vcol is a minimum voltage thereof.

[5] The method in accordance with claim 1, wherein the display panel is an LCD, a

PDP, an OELD or a FED.

[6] The method in accordance with claim 1, wherein the converted clock signal is embedded for each of the converted data signal.

[7] The method in accordance with claim 1, wherein each of the converted clock signal is embedded per the number of N converted data signals, where N is an integer larger than 1.

[8] The method in accordance with claim 1, wherein a control signal or an image data to be displayed on the display panel is transmitted using a polarity of the clock signal converted to the larger voltage.

[9] The method in accordance with claim 1, further comprising transmitting a signal having the converted clock signal embedded between the converted data signal to one receiving terminal or two receiving terminals.

[10] The method in accordance with claim 1, wherein a polarity of the converted clock signal is set identical to that of the converted data signal immediately prior to the embedded clock.

[11] The method in accordance with claim 10, wherein a dummy bit is added immediately after the converted clock signal, where a polarity of the dummy bit is set identical to that of the converted data signal immediately prior to the embedded clock.

[12] A method for multi-level signaling having a clock signal embedded therein used at a receiving terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising restoring a received signal to a clock when a voltage of the received signal is larger than that of a reference voltage and restoring the received signal to a data when the voltage of the received signal is smaller than that of the reference voltage.

[13] The method in accordance with claim 12, wherein the data comprises a control signal and an image data to be displayed on the display panel.

[14] The method in accordance with claim 12, wherein the received signal is restored to the data when IVrefh Vrefll > IVh VlI and the received signal is restored to the clock when IVrefh Vrefll < IVh VlI, where Vrefh and Vrefl are a maximum value and a minimum value of the reference voltage, respectively, and Vh and Vl are a maximum value and a minimum value of the received signal, respectively.

[15] The method in accordance with claim 12, further comprising increasing a frequency f of the restored clock so as to be used for a data sampling.

[16] The method in accordance with claim 12, wherein the restored clock signal is used for a data sampling as is when the restored clock signal is included in each of the restored data signal.

[17] The method in accordance with claim 12, further comprising restoring a control signal or an image data to be displayed on the display panel according to a polarity of a received signal when the voltage of the received signal is larger than that of the reference voltage.

[18] A method for multi-level signaling having a clock signal embedded therein used at a transmitting terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising steps of: converting a data to a signal having a larger voltage than that of a predetermined reference voltage; converting a clock to a signal having a smaller voltage than that of the predetermined reference voltage; and multiplexing the converted clock signal and the converted data signal by embedding the converted clock signal between the converted data signal.

[19] The method in accordance with claim 18, wherein the data comprises a control signal and an image data to be displayed on the display panel.

[20] The method in accordance with claim 18, wherein the data comprises only an image data to be displayed on the display panel.

[21] The method in accordance with claim 18, wherein the step of converting a clock to a signal having the small voltage corresponds to IVrefh - Vrefll > IVcoh Vcoll, and the step of converting the data to the signal having the larger voltage corresponds to IVdoh Vdoll > IVrefh Vrefll, where Vrefh is a maximum value of the reference voltage, Vrefl is a minimum value thereof, Vcoh is a maximum voltage of the clock signal converted to the smaller voltage, Vcol is a minimum voltage thereof, Vdoh is a maximum voltage of the data signal converted to the larger voltage and Vdol is a minimum voltage thereof.

[22] The method in accordance with claim 18, wherein the display panel is an LCD, a

PDP, an OELD or a FED.

[23] The method in accordance with claim 18, wherein the converted clock signal is embedded for each of the converted data signal.

[24] The method in accordance with claim 18, wherein each of the converted clock signal is embedded per the number of N converted data signals, where N is an integer larger than 1.

[25] The method in accordance with claim 18, further comprising transmitting a signal having the converted clock signal embedded between the converted data signal to one receiving terminal or two receiving terminals.

[26] A method for multi-level signaling having a clock signal embedded therein used at a receiving terminal for a signal transmission between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising restoring a received signal to a data when a voltage of the received signal is larger than that of a reference voltage and restoring the received signal to a clock when the voltage of the received signal is smaller than that of the reference voltage.

[27] The method in accordance with claim 26, further comprising converting the received data to a control signal and an image data to be displayed on the display panel in parallel.

[28] The method in accordance with claim 26, wherein the received signal is restored to the clock when IVrefh Vrefll > IVh VlI and the received signal is restored to the data when IVrefh Vrefll < IVh VlI, where Vrefh and Vrefl are a maximum value and a minimum value of the reference voltage, respectively, and Vh and Vl are a maximum value and a minimum value of the received signal, respectively.

[29] The method in accordance with claim 26, further comprising increasing a frequency f of the restored clock so as to be used for a data sampling.

[30] The method in accordance with claim 26, wherein the restored clock signal is used for a data sampling as is when the restored clock signal is included in each of the restored data signal.

[31] A driving apparatus comprising a timing controller, a plurality of column driver integrated circuits and at least one row driver integrated circuit, wherein a differential pair is connected between the timing controller and each of the plurality of the column driver integrated circuits for transmitting a data signal and a clock signal from the timing controller to the plurality of the column driver integrated circuits and wherein the clock signal is embedded between the data signal to have a different signal magnitude from the data signal and is transmitted.

[32] The driving apparatus in accordance with claim 31, wherein the clock signal is embedded per each of the data signal.

[33] The driving apparatus in accordance with claim 31, wherein the clock signal is embedded for every N data signals, where N is an integer larger than 1.

[34] The driving apparatus in accordance with claim 31, wherein a magnitude of the data signal is smaller than a predetermined reference voltage and a magnitude of the clock signal is larger than the predetermined reference voltage.

[35] The driving apparatus in accordance with claim 34, wherein the magnitude of the data signal being smaller than the predetermined reference voltage corresponds to IVrefh Vrefll > IVdoh Vdoll, and the magnitude of the clock signal is larger than the predetermined reference voltage corresponds to IVcoh Vcoll > IVrefh - Vrefll where Vrefh is a maximum value of the reference voltage, Vrefl is a minimum value thereof, Vdoh is a maximum voltage of the data signal and Vdol is a minimum voltage thereof, Vcoh is a maximum voltage of the clock signal, and Vcol is a minimum voltage thereof.

[36] The driving apparatus in accordance with claim 34, wherein a control signal or an image data to be displayed on the display panel is transmitted using a polarity of the clock signal.

[37] The driving apparatus in accordance with claim 36, wherein the polarity of the clock signal is set identical to that of the data signal immediately prior to the clock signal.

[38] The driving apparatus in accordance with claim 37, wherein a dummy bit having a polarity identical to that of the data signal immediately prior to the embedded clock signal is added immediately after the clock signal.

[39] The driving apparatus in accordance with claim 31, wherein a magnitude of the data signal is larger than a predetermined reference voltage and a magnitude of the clock signal is smaller than the predetermined reference voltage.

[40] The driving apparatus in accordance with claim 39, wherein the magnitude of the data signal being larger than the predetermined reference voltage corresponds to IVrefh Vrefll < IVdoh Vdoll, and the magnitude of the clock signal is smaller than the predetermined reference voltage corresponds to IVcoh Vcoll < IVrefh - Vrefll where Vrefh is a maximum value of the reference voltage, Vrefl is a minimum value thereof, Vdoh is a maximum voltage of the data signal, Vdol is a minimum voltage thereof, Vcoh is a maximum voltage of the clock signal, and Vcol is a minimum voltage thereof.

[41] A driving apparatus comprising a timing controller, a plurality of column driver integrated circuits and at least one row driver integrated circuit, wherein a differential pair is connected between the timing controller and at least two of the plurality of the column driver integrated circuits for transmitting a data signal and a clock signal from the timing controller to the at least two column driver integrated circuits and wherein the clock signal is embedded between the data signal to have a different signal magnitude from the data signal and is transmitted.