JP2010087988A - Transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmitter capable of reducing power consumption. <P>SOLUTION: The transmitter 1 includes: a data conversion circuit 10; a main drive circuit 21; a sub-drive circuit 22; a main output buffer circuit 31; and a sub-output buffer circuit 32. The sub-drive circuit 22 executes the following operations: when an EN signal is a non-significant value, switches SW<SB>30</SB>and SW<SB>40</SB>are turned off; when the EN signal is a significant value, the switches SW<SB>30</SB>and SW<SB>40</SB>are turned on; when a POL signal having a defined level before a period when the EN signal is a significant value is an H level, switches SW<SB>31</SB>and SW<SB>42</SB>are turned on and switches SW<SB>32</SB>and SW<SB>41</SB>are turned off; and when the POL signal is an L level, the switches SW<SB>31</SB>and SW<SB>42</SB>are turned off and the switches SW<SB>32</SB>and SW<SB>41</SB>are turned on. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a transmission apparatus that transmits a digital signal by changing a current direction in a pair of differential transmission lines terminated by a resistor.

  As a method for transmitting and receiving a digital signal by changing the current direction in a pair of differential transmission lines terminated by a resistor, a low-amplitude differential signaling (LVDS) is known. LVDS is standardized as IEEE P1596.3, and it is generally said that digital signals can be transmitted and received at high speed, low power consumption, and low noise.

  The transmission device used in the LVDS has a first output terminal and a second output terminal connected to a differential transmission line. When the digital signal to be transmitted is at the H level, the first output terminal is differential from the first output terminal. A current signal that flows to the second output terminal via the transmission line is output, and a current signal that flows from the second output terminal to the first output terminal via the differential transmission line is output when the digital signal to be transmitted is at the L level. .

  In LVDS, when transmitting a clock signal in addition to a digital signal, it is necessary to use a differential transmission line for transmitting a clock signal separately from the differential transmission line for transmitting a digital signal. On the other hand, a technique for transmitting both a digital signal and a clock signal using a common differential transmission line is known (see Patent Document 1 and Non-Patent Document 1).

The technique described in Patent Document 1 and Non-Patent Document 1 is similar to LVDS in that a digital signal is transmitted and received by changing the current direction in a pair of differential transmission lines terminated with a resistor. The clock signal is also transmitted and received by increasing the output value of the current signal every time a certain number of bits are transmitted and received. That is, the transmission device has a binary differential output level. The receiving device detects a voltage between a pair of differential transmission lines terminated by a resistor, and determines that the voltage is a digital signal when the absolute value of the voltage is smaller than a predetermined value. When the absolute value of the voltage is larger than the predetermined value, Judged as a clock signal. If this technique is used, the number of differential transmission lines can be reduced.
International Publication No. 2007/013718 Pamphlet M. Park, et al, “AnAdvanced Intra-Panel Interface (AiPi) with Clock Embedded Multi-Level Point-to-Point Differential Signaling for Large-Sized TFT-LCD Applications,” SIDDIGEST, 43.3, pp.1502-1505 (2006) .

  However, a conventional transmitter that outputs a current signal having a binary differential output level using a common differential transmission line has a large size transistor in order to output a current signal having a large differential output level. The power consumption of the drive circuit which drives the transistor included in the output buffer circuit is large.

  The present invention has been made to solve the above-described problems, and is a transmission device that outputs a current signal having a binary differential output level using a common differential transmission line, and reduces power consumption. It is an object of the present invention to provide a transmission device capable of performing the above.

  The transmission device of the present invention has a first output terminal and a second output terminal connected to a pair of differential transmission lines terminated with a resistor, and the first output terminal and the second output terminal to the differential transmission line. A transmission device that transmits a digital signal by changing the flow direction of an output current signal, and changes the output value of the current signal when the EN signal is a significant value. A buffer circuit, a main drive circuit, and a sub drive circuit are provided.

The main output buffer circuit includes a switch SW ₁₁ provided between the first node and the first output terminal, a switch SW ₁₂ provided between the first node and the second output terminal, a second node, A switch SW ₂₁ provided between the first output terminal and a switch SW ₂₂ provided between the second node and the second output terminal. These switches SW ₁₁ , SW ₁₂ , SW ₂₁ and The SW ₂₂ is formed of a transistor, the first node is connected to the first reference potential, and the second node is connected to the second reference potential.

The sub output buffer circuit includes a switch SW ₃₁ provided between the third node and the first output terminal, a switch SW ₃₂ provided between the third node and the second output terminal, a fourth node, The switch SW ₄₁ provided between the first output terminal, the switch SW ₄₂ provided between the fourth node and the second output terminal, and provided between the third node and the first reference potential. A switch SW ₃₀ and a switch SW ₄₀ provided between the fourth node and the second reference potential. These switches SW ₃₁ , SW ₃₂ , SW ₄₁ , SW ₄₂ , SW ₃₀ and SW ₄₀ are transistors. Consists of.

The main drive circuit, a digital signal is a switch _{SW 12} and _{SW 21} to an off state with the ON state of the switch _{SW 11} and _{SW 22} when it is H level, the switch _{SW 11} and when the digital signal is at the L level SW ₂₂ is turned off and switches SW ₁₂ and SW ₂₁ are turned on.

The sub-driving circuit turns off the switches SW ₃₀ and SW ₄₀ when the EN signal is insignificant, and turns on the switches SW ₃₀ and SW ₄₀ when the EN signal is significant. Further, the sub drive circuit turns on the switches SW ₃₁ and SW ₄₂ when the POL signal whose level has already been determined by the period during which the EN signal has a significant value is at the H level, and switches SW ₃₂ and SW. ₄₁ is turned off, and when the POL signal is at L level, the switches SW ₃₁ and SW ₄₂ are turned off and the switches SW ₃₂ and SW ₄₁ are turned on.

Here, the first reference potential and the second reference potential are different from each other. For example, one is a power supply potential and the other is a ground potential. The switches SW ₁₁ , SW ₁₂ , SW ₂₁ and SW ₂₂ included in the main output buffer circuit, and the switches SW ₃₁ , SW ₃₂ , SW ₄₁ , SW ₄₂ , SW ₃₀ and SW ₄₀ included in the sub output buffer circuit are MOS transistors. A transistor is preferable. Between the first node and the first reference potential, between the second node and the second reference potential, between the third node and the first reference potential, and between the fourth node and the second reference potential, respectively. May be provided with a switch formed of a transistor different from the above-described switch. The sub-output buffer circuit is preferably similar to the main output buffer circuit, and the size of the corresponding transistor is K times (K is a constant value exceeding 1). Is preferred. Each of the main drive circuit and the sub drive circuit can include a logic circuit and the like.

  The transmission device of the present invention is a transmission device that outputs a current signal having a binary differential output level using a common differential transmission line, and can reduce power consumption.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. In the following, the configuration of the transmission device 1 of the present embodiment will be described while comparing with the configurations of the transmission device 1A of the first comparative example and the transmission device 1B of the second comparative example.

  (First comparative example)

  FIG. 1 is a schematic configuration diagram of a transmission device 1A of the first comparative example. The transmission device 1A of the first comparative example includes a data conversion circuit 10A, a drive circuit 20, and an output buffer circuit 30.

  The data conversion circuit 10A receives a parallel digital signal Dpara, converts it into a serial digital signal (DIN signal), and outputs the serial DIN signal to the drive circuit 20 in bit order. This DIN signal includes not only bits obtained by converting the input parallel digital signal Dpara into a serial digital signal, but also dummy bits between them. Further, the data conversion circuit 10A periodically outputs the EN signal as a significant value during a period in which the DIN signal corresponding to one parallel digital signal is output. In this example, the EN signal takes a significant value once or twice during a period in which a DIN signal corresponding to one parallel digital signal is output.

  The time for which the EN signal is output as a significant value is equal to the time for which each bit of the DIN signal is output. In the period in which the EN signal is output as a significant value, the same value as the DIN signal output in the immediately preceding period is output as the DIN signal. In the period immediately after the period in which the EN signal is output as a significant value, the DIN signal can output both the same value and the inverted value. This EN signal represents a clock signal.

  The drive circuit 20 receives the DIN signal and EN signal output from the data conversion circuit 10A, and outputs a signal for driving the output buffer circuit 30. The output buffer circuit 30 has a first output terminal OUTP and a second output terminal OUTN, receives a signal output from the drive circuit 20, and has a pair of resistors terminated from the first output terminal OUTP and the second output terminal OUTN. A current signal is output to the differential transmission line. Signals for driving the output buffer circuit 30 include a BIASp signal, a BIASn signal, a CTRLp signal, a CTRLn signal, an EN signal, and an ENb signal. The direction in which the current signal output from the output buffer circuit 30 flows corresponds to the logic level of each bit of the DIN signal.

FIG. 2 is a main part configuration diagram of the transmission device 1A of the first comparative example. In this figure, circuit diagrams of the drive circuit 20 and the output buffer circuit 30 are shown. The output buffer circuit 30 includes switches SW _{51 to} SW ₅₅ and switches SW _{61 to} SW ₆₅ . These switches are preferably composed of transistors, and particularly preferably composed of MOS transistors. When the switch is composed of a MOS transistor, the transistor is set to either an on state (open state) or an off state (closed state) according to the value of a signal input to the gate terminal of the MOS transistor. Is done.

The switch SW ₅₁ is provided between the first node N ₁ and the first output terminal OUTP. Switch _{SW 52} is provided between the first node _{N 1} and the second output terminal OUTN. The switch SW ₅₃ and the switch SW ₅₄ are connected in parallel to each other, and the two switches and the switch SW ₅₅ are connected in series to each other so that the first node N ₁ and the first reference potential (power supply potential) It is provided between.

Switch _{SW 61} is provided between the second node _{N 2} and the first output terminal OUTP. Switch _{SW 62} is provided between the second node _{N 2} and the second output terminal OUTN. The switch SW ₆₃ and the switch SW ₆₄ are connected in parallel to each other, and these two switches and the switch SW ₆₅ are connected in series to each other so that the second node N ₂ and the second reference potential (ground potential) are connected. It is provided between.

The switches SW ₅₁ and SW ₆₂ are set to either the on state or the off state according to the value of the CTRLp signal. The switches SW ₅₂ and SW ₆₁ are set to either the on state or the off state according to the value of the CTRLn signal. The switches SW ₅₃ and SW ₆₃ are always set to an on state during operation. The switches SW ₅₄ and SW ₆₄ are set to either the on state or the off state according to the value of the EN signal. The switch SW ₅₅ is always set to an on state by the BIASp signal during operation. Further, the switch SW ₆₅ is always set to the on state by the BIASn signal during operation. In the output buffer circuit 30, the amount of current flowing between the first output terminal OUTP and the second output terminal OUTN can be adjusted by adjusting the voltages of the BIASp signal and the BIASn signal.

The drive circuit 20 includes a buffer BUFp and a buffer BUFn. The buffer BUFp outputs a CTRLp signal having the same level as that of the input DIN signal. The buffer BUFn outputs a CTRLn signal whose level is logically inverted with respect to the level of the input DIN signal. When the DIN signal is at the H level, the drive circuit 20 sets the CTRLp signal to the H level to turn on the switches SW ₅₁ and SW ₆₂ , and sets the CTRLn signal to the L level to set the switches SW ₅₂ and SW ₆₁ to the off state. To do. When the DIN signal is at the L level, the drive circuit 20 sets the CTRLp signal to the L level to turn off the switches SW ₅₁ and SW ₆₂ , and sets the CTRLn signal to the H level to turn on the switches SW ₅₂ and SW _61. To do. The drive circuit 20 turns off the switches SW ₅₄ and SW ₆₄ when the EN signal is insignificant, and turns on the switches SW ₅₄ and SW ₆₄ when the EN signal is significant.

When the DIN signal is at the H level, the switches SW ₅₁ and SW ₆₂ are turned on, the switches SW ₅₂ and SW ₆₁ are turned off, and the first output terminal OUTP is connected to the first node via the switch SW _51. The second output terminal OUTN is connected to the second node N ₂ via the switch SW ₆₂ while being connected to N ₁ . On the other hand, when the DIN signal is at the L level, the switches SW ₅₁ and SW ₆₂ are turned off, the switches SW ₅₂ and SW ₆₁ are turned on, and the first output terminal OUTP is switched through the switch SW ₅₂ . The second output terminal OUTN is connected to the second node N ₂ via the switch SW ₆₁ while being connected to the one node N ₁ .

When the EN signal is an insignificant value, the first node N ₁ is connected to the first reference potential via the switch SW ₅₃ and the switch SW _55, and the second node N ₂ is connected to the switch SW _63. And the second reference potential via the switch SW ₆₅ . On the other hand, when the EN signal has a significant value, the first node N ₁ is connected to the first reference potential via the switches SW ₅₃ and SW ₅₄ and the switch SW ₅₅ connected in parallel, and the second node N 1 is connected. ₂ is connected to the second reference potential via switches SW ₆₃ and SW ₆₄ and a switch SW ₆₅ connected in parallel.

  FIG. 3 is a timing chart of each signal in the transmission device 1A of the first comparative example. As shown in this figure, the direction in which the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line flows is determined according to the level of the DIN signal. Further, the current signal output when the EN signal is a significant value is large.

In such a transmission apparatus 1A of the first comparative example, when the EN signal has a significant value, the switches SW ₅₄ and SW ₆₄ are turned on, and the current flowing through the switches SW ₅₁ , SW ₅₂ , SW ₆₁ , and SW ₆₂ flows. Since these are large, MOS transistors having a large gate width are used as these switches, and the buffers BUFp and BUFn included in the drive circuit 20 for driving these switches are also large. The buffers BUFp and BUFn consume a large current each time the value of the DIN signal changes.

  (Second comparative example)

  FIG. 4 is a schematic configuration diagram of a transmission device 1B of the second comparative example. The transmission device 1B of the second comparative example includes a data conversion circuit 10A, a drive circuit 20, a main output buffer circuit 31, and a sub output buffer circuit 32. The data conversion circuit 10A and the drive circuit 20 included in the transmission device 1B of the second comparative example have the same configuration as that included in the transmission device 1A of the first comparative example. Compared to the configuration of the transmission device 1A of the first comparative example, the transmission device 1B of the second comparative example is different in that it includes a main output buffer circuit 31 and a sub output buffer circuit 32 instead of the output buffer circuit 30.

  The main output buffer circuit 31 and the sub output buffer circuit 32 share the first output terminal OUTP and the second output terminal OUTN, receive a signal output from the drive circuit 20, and receive the first output terminal OUTP and the second output terminal. A current signal is output from OUTN to a pair of differential transmission lines that are resistance-terminated. The signals for driving the main output buffer circuit 31 include a BIASp signal, a BIASn signal, a CTRLp signal, and a CTRLn signal. The signals for driving the sub output buffer circuit 32 include a BIASp signal, a BIASn signal, a CTRLp signal, a CTRLn signal, an EN signal, and an ENb signal.

  FIG. 5 is a main part configuration diagram of a transmission apparatus 1B of the second comparative example. In this figure, circuit diagrams of the drive circuit 20, the main output buffer circuit 31, and the sub output buffer circuit 32 are shown. The configuration of the drive circuit 20 is the same as that of the first comparative example.

Main output buffer circuit 31 includes switches SW _{10 to} SW ₁₃ and switches SW _{20 to} SW ₂₃ . These switches are preferably composed of transistors, and particularly preferably composed of MOS transistors. When the switch is composed of a MOS transistor, the transistor is set to either an on state (open state) or an off state (closed state) according to the value of a signal input to the gate terminal of the MOS transistor. Is done.

Switch _{SW 11} is provided between the first node _{N 1} and the first output terminal OUTP. Switch _{SW 12} is provided between the first node _{N 1} and the second output terminal OUTN. The switch SW ₁₀ and the switch SW ₁₃ are connected in series with each other and provided between the first node N ₁ and the first reference potential (power supply potential).

Switch _{SW 21} is provided between the second node _{N 2} and the first output terminal OUTP. Switch _{SW 22} is provided between the second node _{N 2} and the second output terminal OUTN. The switch SW ₂₀ and the switch SW ₂₃ are connected in series with each other and provided between the second node N ₂ and the second reference potential (ground potential).

Switches _{SW 11} and _{SW 22} are set to an on state or an off state depending on the value of CTRLp signal. The switches SW ₁₂ and SW ₂₁ are set to either the on state or the off state according to the value of the CTRLn signal. The switches SW ₁₀ and SW ₂₀ are always set to an on state during operation. The switch SW ₁₃ is always set to an on state by a BIASp signal during operation. Further, the switch SW ₂₃ is always set to an on state by the BIASn signal during operation. As in the first comparative example, the main output buffer circuit 31 can adjust the amount of current flowing between the first output terminal OUTP and the second output terminal OUTN by adjusting the voltages of the BIASp signal and the BIASn signal. it can.

The sub output buffer circuit 32 includes switches SW _{30 to} SW ₃₃ and switches SW _{40 to} SW ₄₃ . These switches are preferably composed of transistors, and particularly preferably composed of MOS transistors. When the switch is composed of a MOS transistor, the transistor is set to either an on state (open state) or an off state (closed state) according to the value of a signal input to the gate terminal of the MOS transistor. Is done. The switches SW _{30 to} SW ₃₃ and the switches SW _{40 to} SW ₄₃ included in the sub output buffer circuit 32 have gate widths as compared with the switches SW _{10 to} SW ₁₃ and switches SW _{20 to} SW ₂₃ included in the main output buffer circuit 31. It is composed of a large MOS transistor.

Switch _{SW 31} is provided between the third node _{N 3} first output terminal OUTP. The switch SW ₃₂ is provided between the third node N ₃ and the second output terminal OUTN. The switch SW ₃₀ and the switch SW ₃₃ are connected in series with each other and provided between the third node N ₃ and the first reference potential (power supply potential).

The switch SW ₄₁ is provided between the fourth node N ₄ and the first output terminal OUTP. Switch _{SW 42} is provided between the fourth node _{N 4} second output terminal OUTN. The switch SW ₄₀ and the switch SW ₄₃ are connected in series with each other and provided between the fourth node N ₄ and the second reference potential (ground potential).

The switches SW ₃₁ and SW ₄₂ are set to either the on state or the off state according to the value of the CTRLp signal. The switches SW ₃₂ and SW ₄₁ are set to either the on state or the off state according to the value of the CTRLn signal. The switches SW ₃₀ and SW ₄₀ are set to either the on state or the off state according to the value of the EN signal. The switch SW ₃₃ is always set to the ON state by the BIASp signal during operation. Further, the switch SW ₄₃ is always set to an on state by the BIASn signal during operation. Similar to the main output buffer circuit 31, the sub output buffer circuit 32 adjusts the amount of current flowing between the first output terminal OUTP and the second output terminal OUTN by adjusting the voltages of the BIASp signal and the BIASn signal. Can do.

When the DIN signal is at the H level, the drive circuit 20 sets the CTRLp signal to the H level to turn on the switches SW ₁₁ , SW ₂₂ , SW ₃₁ and SW ₄₂ , and sets the CTRLn signal to the L level to set the switches SW ₁₂ , SW ₂₁ , SW ₃₂ and SW ₄₁ are turned off. When the DIN signal is at L level, the drive circuit 20 sets the CTRLp signal to L level to turn off the switches SW ₁₁ , SW ₂₂ , SW ₃₁ and SW ₄₂ , and sets the CTRLn signal to H level to switch SW ₁₂ , SW ₂₁ , SW ₃₂ and SW ₄₁ are turned on. The drive circuit 20 turns off the switches SW ₃₀ and SW ₄₀ when the EN signal is insignificant, and turns on the switches SW ₃₀ and SW ₄₀ when the EN signal is significant.

In the main output buffer circuit 31, when the DIN signal is at H level, the switch _{SW 11} and _{SW 22} are turned on, the switch _{SW 12} and _{SW 21} are turned off, the first output terminal OUTP switch SW ₁₁ is connected to the first node N _1, and the second output terminal OUTN is connected to the second node N ₂ via the switch SW ₂₂ . On the other hand, when the DIN signal is at the L level, the switches SW ₁₁ and SW ₂₂ are turned off, the switches SW ₁₂ and SW ₂₁ are turned on, and the first output terminal OUTP is switched through the switch SW ₁₂ . The second output terminal OUTN is connected to the second node N ₂ via the switch SW ₂₁ while being connected to the one node N ₁ . Therefore, the direction in which the current signal output from the main output buffer circuit 31 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN flows differs depending on the level of the DIN signal.

In sub-output buffer circuit 32, when the DIN signal is at H level, the switch _{SW 31} and _{SW 42} are turned on, the switch _{SW 32} and _{SW 41} are turned off, the first output terminal OUTP switch SW The second output terminal OUTN is connected to the fourth node N ₄ via the switch SW ₄₂ while being connected to the third node N ₃ via ₃₁ . On the other hand, when the DIN signal is at the L level, the switches SW ₃₁ and SW ₄₂ are turned off, the switches SW ₃₂ and SW ₄₁ are turned on, and the first output terminal OUTP is switched through the switch SW ₃₂ . The second output terminal OUTN is connected to the fourth node N ₄ via the switch SW ₄₁ while being connected to the third node N ₃ .

Further, the sub-output buffer circuit 32, when the EN signal is insignificant value, the third node N ₃ is not connected to the first reference potential, the fourth node N ₄ is not connected to the second reference potential. On the other hand, when the EN signal has a significant value, the third node N ₃ is connected to the first reference potential via the switch SW ₃₀ and the switch SW _33, and the fourth node N ₄ is connected to the switch SW ₄₀ . The second reference potential is connected to the switch SW ₄₃ .

  Therefore, when the EN signal is an insignificant value, no current signal is output from the secondary output buffer circuit 32. On the other hand, when the EN signal is a significant value, a current signal is output from the secondary output buffer circuit 32 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN, and the direction in which the current signal flows is the DIN signal. It depends on the level.

  The timing chart of each signal in the transmission device 1B of the second comparative example is the same as FIG. In the transmission device 1B of the second comparative example, when the EN signal is an insignificant value, the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is output from the main output buffer circuit 31. The direction in which the current signal flows is determined according to the level of the DIN signal. On the other hand, when the EN signal is a significant value, current signals output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line are output from the main output buffer circuit 31 and the sub output buffer circuit 32, respectively. The direction in which the current signal flows is determined according to the level of the DIN signal. Therefore, the current signal output when the EN signal is a significant value is large.

In the transmission apparatus 1B having such a second comparative example, since the current is small through the switch _SW 10 _{to SW 13} and the switch _SW 20 _{to SW 23} included in the main output buffer circuit 31, the gate width is small as these switches MOS transistors can be used. However, since the current flowing through the switches SW _{30 to} SW ₃₃ and the switches SW _{40 to} SW ₄₃ included in the sub output buffer circuit 32 is large, MOS transistors having a large gate width are used as these switches. The buffers BUFp and BUFn included in the driving circuit 20 for driving the are also large in size. The buffers BUFp and BUFn consume a large current each time the value of the DIN signal changes.

  (This embodiment)

  FIG. 6 is a schematic configuration diagram of the transmission device 1 of the present embodiment. The transmission device 1 of this embodiment includes a data conversion circuit 10, a main drive circuit 21, a sub drive circuit 22, a main output buffer circuit 31, and a sub output buffer circuit 32. The main output buffer circuit 31 and the sub output buffer circuit 32 included in the transmission device 1 of the present embodiment have the same configuration as that included in the transmission device 1B of the second comparative example. Compared with the configuration of the transmission device 1B of the second comparative example, the transmission device 1 of the present embodiment is different in that the data conversion circuit 10 is provided instead of the data conversion circuit 10A, and the main configuration is changed to the drive circuit 20. The difference is that a drive circuit 21 and a sub drive circuit 22 are provided.

  The data conversion circuit 10 receives a parallel digital signal Dpara, converts it into a serial digital signal (DIN signal), and outputs the serial DIN signal to the main drive circuit 21 in bit order. This DIN signal includes not only bits obtained by converting the input parallel digital signal Dpara into a serial digital signal, but also dummy bits between them. Further, the data conversion circuit 10 periodically outputs the EN signal as a significant value during a period in which the DIN signal corresponding to one parallel digital signal is output. In this example, the EN signal takes a significant value once or twice during a period in which a DIN signal corresponding to one parallel digital signal is output.

  The time for which the EN signal is output as a significant value is equal to the time for which each bit of the DIN signal is output. In the period in which the EN signal is output as a significant value, the same value as the DIN signal output in the immediately preceding period is output as the DIN signal. In the period immediately after the period in which the EN signal is output as a significant value, the DIN signal can output both the same value and the inverted value. This EN signal represents a clock signal.

  The data conversion circuit 10 receives the input parallel digital signal Dpara and outputs a POL signal to the sub drive circuit 22. The level of this POL signal is already determined by the period when the EN signal is a significant value. The level is equal to the level of the DIN signal output during a period in which the EN signal has a significant value.

  The main drive circuit 21 receives the DIN signal output from the data conversion circuit 10 and outputs a signal for driving the main output buffer circuit 31. Signals for driving the main output buffer circuit 31 include a BIASp signal, a BIASn signal, a CTRL1p signal, and a CTRL1n signal.

  The sub drive circuit 22 receives the EN signal and the POL signal output from the data conversion circuit 10 and outputs a signal for driving the sub output buffer circuit 32. The signals for driving the sub output buffer circuit 32 include a BIASp signal, a BIASn signal, a CTRL2p signal, a CTRL2n signal, an EN signal, and an ENb signal.

  FIG. 7 is a main part configuration diagram of the transmission apparatus 1 of the present embodiment. In this figure, circuit diagrams of the main drive circuit 21, the sub drive circuit 22, the main output buffer circuit 31, and the sub output buffer circuit 32 are shown. The configurations of the main output buffer circuit 31 and the sub output buffer circuit 32 are the same as those in the second comparative example.

The main drive circuit 21 includes a buffer BUF1p and a buffer BUF1n. The buffer BUF1p outputs a CTRL1p signal having the same level as that of the input DIN signal. The buffer BUF1n outputs a CTRL1n signal whose level is logically inverted with respect to the level of the input DIN signal. The main drive circuit 21, when DIN signal is H level, the CTRL1p signal with the switch _{SW 11} and _{SW 22} to the ON state as H level, turns off the switch _{SW 12} and _{SW 21} to CTRL1n signal as L level And The main drive circuit 21, when DIN signal is at the L level, while the switch _{SW 11} and _{SW 22} to an off state as L level CTRL1p signal, turning on the switch _{SW 12} and _{SW 21} to CTRL1n signal as H level And

The sub drive circuit 22 includes a buffer BUF2p and a buffer BUF2n. The buffer BUF2p outputs a CTRL2p signal having the same level as that of the input POL signal. The buffer BUF2n outputs a CTRL2n signal having a logically inverted level with respect to the level of the input POL signal. Auxiliary drive circuit 22, when the POL signal is H level, the CTRL2p signal with the switch _{SW 31} and _{SW 42} to the ON state as H level, turns off the switch _{SW 32} and _{SW 41} to CTRL2n signal as L level And Auxiliary drive circuit 22, when the POL signal is at the L level, while the switch _{SW 31} and _{SW 42} to an off state as L level CTRL2p signal, the on-state switch _{SW 32} and _{SW 41} to CTRL2n signal as H level And The sub-drive circuit 22 turns off the switches SW ₃₀ and SW ₄₀ when the EN signal is insignificant, and turns on the switches SW ₃₀ and SW ₄₀ when the EN signal is significant.

In the main output buffer circuit 31, when the DIN signal is at H level, the switch _{SW 11} and _{SW 22} are turned on, the switch _{SW 12} and _{SW 21} are turned off, the first output terminal OUTP switch SW ₁₁ is connected to the first node N _1, and the second output terminal OUTN is connected to the second node N ₂ via the switch SW ₂₂ . On the other hand, when the DIN signal is at the L level, the switches SW ₁₁ and SW ₂₂ are turned off, the switches SW ₁₂ and SW ₂₁ are turned on, and the first output terminal OUTP is switched through the switch SW ₁₂ . The second output terminal OUTN is connected to the second node N ₂ via the switch SW ₂₁ while being connected to the one node N ₁ . Therefore, the direction in which the current signal output from the main output buffer circuit 31 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN flows differs depending on the level of the DIN signal.

In sub-output buffer circuit 32, when the POL signal is at the H level, the switch _{SW 31} and _{SW 42} are turned on, the switch _{SW 32} and _{SW 41} are turned off, the first output terminal OUTP switch SW The second output terminal OUTN is connected to the fourth node N ₄ via the switch SW ₄₂ while being connected to the third node N ₃ via ₃₁ . On the other hand, when the POL signal is at the L level, the switches SW ₃₁ and SW ₄₂ are turned off, the switches SW ₃₂ and SW ₄₁ are turned on, and the first output terminal OUTP is switched through the switch SW ₃₂ . The second output terminal OUTN is connected to the fourth node N ₄ via the switch SW ₄₁ while being connected to the third node N ₃ .

Further, the sub-output buffer circuit 32, when the EN signal is insignificant value, the third node N ₃ is not connected to the first reference potential, the fourth node N ₄ is not connected to the second reference potential. On the other hand, when the EN signal has a significant value, the third node N ₃ is connected to the first reference potential via the switch SW ₃₀ and the switch SW _33, and the fourth node N ₄ is connected to the switch SW ₄₀ . The second reference potential is connected to the switch SW ₄₃ .

  Therefore, when the EN signal is an insignificant value, no current signal is output from the secondary output buffer circuit 32. On the other hand, when the EN signal is a significant value, a current signal is output from the secondary output buffer circuit 32 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN, and the direction in which the current signal flows is the POL signal. Varies depending on the level.

  FIG. 8 is a timing chart of each signal in the transmission device 1 of the present embodiment. In the transmission device 1 of the present embodiment, when the EN signal is an insignificant value, the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is output from the main output buffer circuit 31. The direction in which the current signal flows is determined according to the level of the DIN signal. On the other hand, when the EN signal has a significant value, the level of the POL signal is equal to the level of the DIN signal, and the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is the main output buffer. The current signal output from each of the circuit 31 and the sub output buffer circuit 32 is added, and the direction in which the current signal flows is determined according to the level of the DIN signal. Therefore, the current signal output when the EN signal is a significant value is large.

In the transmission apparatus 1 of the present embodiment, a sub drive circuit 22 that drives a sub output buffer circuit 32 is provided in addition to the main drive circuit 21 that drives the main output buffer circuit 31. Since the currents flowing through the switches SW _{10 to} SW ₁₃ and the switches SW _{20 to} SW ₂₃ included in the main output buffer circuit 31 are small, MOS transistors having a small gate width can be used as these switches. Therefore, the buffers BUF1p and BUF1n included in the main drive circuit 21 that drives the main output buffer circuit 31 are sufficient to be small in size, and thus power consumption is reduced.

On the other hand, since the currents flowing through the switches SW _{30 to} SW ₃₃ and the switches SW _{40 to} SW ₄₃ included in the sub output buffer circuit 32 are large, MOS transistors having a large gate width are used as these switches.

However, in the secondary output buffer circuit 32, the state of the switches SW ₃₁ , SW ₃₂ , SW ₄₁ and SW ₄₂ is determined by determining the level of the POL signal before the EN signal becomes a significant value. When the switches SW ₃₀ and SW ₄₀ are turned on with a significant value, a current signal is output.

  Therefore, the buffers BUF2p and BUF2n included in the sub-drive circuit 22 that drives the sub-output buffer circuit 32 do not need to shift the output levels of the CTRL2p signal and the CTRL2n signal at a high speed, so that a small size is sufficient. Further, the buffers BUF2p and BUF2n may have a small number of times of changing the output level. Therefore, the power consumption of the buffers BUF2p and BUF2n is reduced.

  As described above, the transmission device 1 of the present embodiment includes the sub-drive circuit 22 in addition to the main drive circuit 21, but compared with either the transmission device 1A of the first comparative example or the transmission device 1B of the second comparative example. In this case, not only the power consumption can be reduced, but also the layout area when integrated on a semiconductor substrate can be reduced.

It is a schematic block diagram of the transmitter 1A of the 1st comparative example. It is a principal part block diagram of the transmitter 1A of a 1st comparative example. It is a timing chart of each signal in transmitter 1A of the 1st comparative example. It is a schematic block diagram of the transmitter 1B of the 2nd comparative example. It is a principal part block diagram of the transmitter 1B of the 2nd comparative example. It is a schematic block diagram of the transmitter 1 of this embodiment. It is a principal part block diagram of the transmitter 1 of this embodiment. It is a timing chart of each signal in the transmitter 1 of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A, 1B ... Transmitting device 10, 10A ... Data conversion circuit, 20 ... Drive circuit, 21 ... Main drive circuit, 22 ... Sub drive circuit, 30 ... Output buffer circuit, 31 ... Main output buffer circuit, 32 ... Sub Output buffer circuit.

Claims (1)

A first output terminal and a second output terminal connected to a pair of resistance-terminated differential transmission lines, and a current signal flowing from the first output terminal and the second output terminal to the differential transmission line flows. A transmission device that transmits a digital signal by changing a direction and changes an output value of a current signal when an EN signal is a significant value,
A switch SW ₁₁ provided between a first node and the first output terminal, a switch SW ₁₂ provided between the first node and the second output terminal, a second node, and the first A switch SW ₂₁ provided between the output terminal and a switch SW ₂₂ provided between the second node and the second output terminal. These switches SW ₁₁ , SW ₁₂ , SW ₂₁ and A main output buffer circuit in which the SW ₂₂ is constituted by a transistor, the first node is connected to a first reference potential, and the second node is connected to a second reference potential;
A switch SW ₃₁ provided between a third node and the first output terminal, a switch SW ₃₂ provided between the third node and the second output terminal, a fourth node and the first The switch SW ₄₁ provided between the output terminal, the switch SW ₄₂ provided between the fourth node and the second output terminal, and between the third node and the first reference potential. A switch SW ₃₀ provided, and a switch SW ₄₀ provided between the fourth node and the second reference potential. These switches SW ₃₁ , SW ₃₂ , SW ₄₁ , SW ₄₂ , SW ₃₀ and A sub output buffer circuit in which the SW ₄₀ is constituted by a transistor;
The digital signal is the switch _{SW 12} and _{SW 21} to an off state with the ON state of the switch _{SW 11} and _{SW 22} when it is H level, the switch _{SW 11} and when the digital signal is at the L level A main drive circuit that turns SW ₂₂ off and switches SW ₁₂ and SW ₂₁ on;
When the EN signal is insignificant, the switches SW ₃₀ and SW ₄₀ are turned off. When the EN signal is significant, the switches SW ₃₀ and SW ₄₀ are turned on, and the EN signal is significant. When the POL signal whose level has already been determined by the period of value is at the H level, the switches SW ₃₁ and SW ₄₂ are turned on, the switches SW ₃₂ and SW ₄₁ are turned off, and the POL signal A sub-driving circuit that turns off the switches SW ₃₁ and SW ₄₂ and turns on the switches SW ₃₂ and SW ₄₁ when the switch is at the L level;
A transmission device comprising:

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