TW201019298A - Transmission device - Google Patents

Abstract

A transmission device (1) includes a data conversion circuit (10), a main drive circuit (21), a sub drive circuit (22), a main output buffer circuit (31), and a sub output buffer circuit (32). The sub drive circuit (22) turns OFF switches SW30 and SW40 when an EN signal has no significant value and turns ON the switches SW30 and SW40 when the EN signal has a significant value. When a POL signal having a level determined until the period when the EN signal has a significant value is at H level, the sub drive circuit (22) turns ON switches SW31 and SW42 and turns OFF switches SW32 and SW41. When the POL signal is at L level, the sub drive circuit (22) turns OFF the switches SW31 and SW42 and turns ON the switches SW32 and SW41.

Description

201019298 VI. Description of the Invention: [Technical Field] The present invention relates to a transmitting device that transmits a digital signal by changing a direction of a current in a pair of differential transmission lines to which a terminating resistor has been applied. [Prior Art] 0 By changing the current direction in the differential transmission line to which the terminating resistor has been applied to receive the digital signal, there is a small amplitude differential signal method (LVDS: Low-Voltage Differential Signaling). ) is well known. The LVDS system has been standardized to IEEE PI 596.3, which is generally capable of receiving digital signals at high speed, low power consumption, and low noise. The transmitting device used in the LVDS includes a first output terminal and a second output terminal connected to the differential transmission line. When the digital signal to be transmitted is a clamped position, the output is differentially transmitted from the first output terminal. The current signal flowing to the second output terminal of the transmission line outputs a current signal flowing from the second output terminal to the first output terminal via the differential transmission line when the digital signal to be transmitted is the L level. In LVDS, when a clock signal is to be transmitted in addition to the digital signal, it is necessary to use a differential transmission line for signal transmission other than the differential transmission line for digital signal transmission. On the other hand, a technique of transmitting both digital signals and time signals using a common differential transmission line is known (see Patent Document 1 and Non-Patent Document 1). The techniques described in Patent Document 1 and Non-Patent Document 1 are based on -5 - 201019298

The direction of the current in the differential transmission line that has been applied with the pair of termination resistors to receive the digital signal is the same as that of the LVD S, but whenever the digital signal receives a certain number of bits, The output of the current signal is increased and the clock signal is also received. That is, the transmitting device has a differential output level of 2 。. The receiving device detects the voltage between the pair of differential transmission lines to which the terminating resistor has been applied, and determines that it is a digital signal when the absolute value of the voltage is less than the predetermined value, when the absolute value of the voltage is greater than When it is determined, it is judged as a clock signal. If this technique is employed, the number of differential transmission lines can be reduced. [Prior Art Document] [Patent Document 1] [Patent Document 1] International Publication No. 200 7/01 371 No. 8 Booklet [Non-Patent Document] [Non-Patent Document 1] Μ · Park, et al, "An Advanced Intra-Panel Interface ( AiPi) with Clock Embedded Multi-

Level Point-to-Point Differential Signaling for Large-Sized TFT-LCD Applications, ” SIDDIGEST, 43.3, pp. 1 502- 1 505 (2006). [Problems to be Solved by the Invention] However, the use of common A differential transmission line for outputting a current signal having a differential output level of 2 ' is provided with a large-sized transistor -6 for outputting a current signal of a large differential output level - 201019298 The snubber circuit, and the power consumption of the drive circuit for driving the transistor included in the output buffer circuit is large. The present invention has been made in order to solve the above problem, and aims to provide a transmitting device. It is a transmission device that outputs a current signal having a differential output level of 2 turns using a common differential transmission line, and can reduce power consumption. ΰ % [Means for Solving the Problem] The transmission of the present invention The device is a first output terminal and a second output terminal having a differential transmission line connected to a pair of terminating resistors, by changing from the first output terminals And the second output terminal sends a digital signal to the flow direction of the current signal outputted by the differential transmission line, and the output device that changes the output of the current signal when the signal is correct, and has the following characteristics a main output buffer circuit, a sub-output buffer circuit, a main drive circuit, and a sub-drive circuit. The main output buffer circuit includes a switch SW11 provided between the first node and the first output terminal, and is provided at the first node. a switch sw12 between the second output terminal and a switch SW21 provided between the second node and the first output terminal; and a switch sw22 provided between the second node and the second output terminal; these switches SWu Sw12, sw21, and sw22 are formed by transistors, the first node is connected to the first reference potential, and the second node is connected to the second reference potential. The sub-output buffer circuit 'includes: is set to the third a switch SW31 between the node and the first output terminal; and a switch SW32 provided between the third node and the second output 201019298; and a switch SW41 provided between the fourth node and the first output terminal; and Set at node 4 and 2 a switch SW42 between the output terminals; a switch SW3 that is provided between the third node and the first reference potential; and a switch SW4 that is provided between the fourth node and the second reference potential; and the switches SW31, SW32, SW41, SW42, SW30, and SW40 are composed of transistors.

The main drive circuit sets the switch SWn&SW22 to the ON state and sets the switch SW12&SW21 to the OFF state when the digital signal is clamped. When the digital signal is the L level, the switches SWM and SW22 are set to the OFF state. And the switches SW12 and SW21 are set to the ON state.

The sub-driver circuit sets the switches SW3Q and SW4 to the OFF state when the EN signal is non-independent. When the EN signal is correct, the switches SW3C and SW4C are set to the ON state. Moreover, the sub-driver circuit sets the switches SW31 and SW42 to the ON state and sets the switches SW32 and SW41 to OFF when the POL signal whose level has been determined is the clamp time during the period when the EN signal is positive. In the state, when the POL signal is the L level, the switches 3\^31 and SW42 are set to the OFF state and the switches SW32 and SW41 are set to the ON state. Here, the first reference potential and the second reference potential are different from each other, and for example, one is a power supply potential and the other is a ground potential. The switches SWh, SW12, SW21, and SW22 included in the main output buffer circuit, and the switches SW31, SW32, SW41, SW42, SW30, and SW4 included in the sub output buffer circuit are composed of MOS transistors. Ideal. The first node and the first reference potential, the second node and the second reference -8 - ΰ 201019298 potential, the third node and the first reference potential, and the second reference potential may be respectively It is provided with a switch made of the above-mentioned crystal. Compared with the main output buffer circuit, the circuit system is ideal for its similar circuit configuration, and the corresponding system is K times (the K system is more than 値1). The logic circuit and the sub-drive circuit can each contain a logic circuit. [Effect of the Invention] The transmitting device of the present invention is capable of reducing the power consumption by using a common differential signal having a differential output level of 2 turns. [Embodiment] Hereinafter, a preferred embodiment will be described with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the φ. Further, the configuration of the transmitting device 1 of the present embodiment will be described below with reference to the transmitting device 1 of the second comparative example and the transmitting device 1 of the second comparative example. (First comparative example) Fig. 1 is a schematic diagram of a transmitting device 1 of a first comparative example. The transmitting device 1 of the comparative example includes a data conversion age circuit 20 and an output buffer circuit 30. The data conversion circuit 10A is a parallel input digital card and a size of a different electrical output buffer circuit of the fourth node. The main drive is powered. The transmission line communication device is described, and the configuration of each of the first comparative examples is shown in the drawings. No. 10, drive number Dpara, 201019298

This is converted into a serial digital signal (DIN signal), and the DIN signal of the sequence is output to the drive circuit 20 in bit order. The DIN signal is a bit that contains not only the input digital signal Dpara that is input into the serial digital signal, but also a dummy bit between them. Further, the data conversion circuit 10A periodically outputs the EN signal as a positive period while the DIN signal corresponding to one parallel digital signal is being output. In this example, the EN signal will become a valid one or two times during the period in which the DIN signal corresponding to one parallel digital signal is being output.

The time when the EN signal is output as a sense of time is equivalent to the time at which the elements of the DIN signal are output. The period in which the EN signal is outputted as a valid , is the same as the DIN signal outputted in the previous period 値' is output as a DIN signal. In the latter period of the period in which the EN signal is output as a sense, the DIN signal may be the same as the output 値 and the output reversal 値. This EN signal indicates the clock signal. The drive circuit 20 receives the DIN signal and the EN signal outputted from the data conversion circuit 10A, and then outputs a signal for driving the output buffer circuit 30. The output buffer circuit 30 has a first output terminal OUTP and a second output terminal OUTN, and receives a signal output from the drive circuit 20 from the first output terminal OUTP and the second output terminal OUTN to a terminal resistor that has been applied. For the differential transmission line, the output current signal. In the signal used to drive the output buffer circuit 30, the package contains the BIASp signal 'Blasson signal, CTRLp signal, CTRLn signal-10-201019298, ΕΝ signal and ENb signal. Further, the flow direction of the current signal output from the output buffer circuit 3 corresponds to the logic level of each of the DIN signals. Fig. 2 is a diagram showing the configuration of a main part of the transmitting device 1A of the first comparative example. The figure shows the electric circuit {output buffer circuit 30 of the drive circuit 20 and the output buffer circuit 3, and includes switches SW51 to SW55 and switches SW65. These switches' are preferably formed of a transistor, and are preferably formed of a MOS transistor. When the switch is composed of MOS electric power, the transistor is set to an ON state (an open state OFF state (closed state) corresponding to the 闸 gate signal input to the MOS transistor. SW51 is provided between the first node 与1 and the first output OUTP. The switch SW52 is provided between the first node N and the first terminal OUTN. The switch SW53 and the switch SW54 are connected to each other. The switch SW55 is connected in series between the node node and the first reference potential (power source potential). The switch SW61 is provided between the second node N2 and the first output OUTP. It is provided between the second node N2 and the output terminal OUTN. The switch SW63 and the switch SW64 are connected to each other, and the two switches and the switch SW65 are connected in series to each other and are provided at the node N2 and the second reference potential (ground potential). The switches SW51 and SW62 are set to either the ON state and the OFF state corresponding to the CTRLp signal. The switches SW52 and are set to the ON state corresponding to the CTRLn signal and

The bit transferred. This Γο-ί figure. Sw61 is the crystal sub) and terminal 2 is connected in parallel. The first terminal 2 is connected in parallel to the second and is in the SW6, OFF -11 - 201019298 state. The switches sw53 and sw63 are always set to the ON state during operation. The switches SW54 and SW64 are set to either the ON state or the OFF state in response to the EN signal. The switch SW55 is always set to the ON state by the BIASp signal during operation. Further, the switch SW65 is always set to the ON state by the BIASn signal during operation. Further, in the output buffer circuit 30, by adjusting the voltages of the BIASp signal and the BIASn signal, the amount of current flowing between the first output terminal OUTP and the second output terminal OUTN can be adjusted, and the drive circuit 20 is included. Buffer BUFp and buffer BUFn. The buffer BUFp outputs a CTRLp signal having the same level as the input DIN signal. The buffer BUFn outputs a CTRLn signal which is a level of logical inversion with respect to the level of the input DIN signal. The driving circuit 20 sets the CTRLp signal to the Η level and sets the switches SW51 and SW62 to the ON state, and sets the CTRLn signal to the L level and the switches SW52 and SW61 to the OFF state when the DIN signal is clamped. status. The driving circuit 20, when the DIN signal is the L level, sets the CTRLp signal to the L level and sets the switches 3\^51 and SW62 to the OFF state, and sets the CTRLn signal to the Η level and switches the switches SW52 and SW61. Set to the ON state. Further, the drive circuit 20 sets the switches SW54 and SW64 to the OFF state when the 讯 signal is non-intelligible, and sets the switches SW54 and SW64 to the ON state when the EN signal is ambiguous. When the DIN signal is clamped, the switches SW51 and SW62 become -12- 201019298 Ο

In the ΟΝ state, the switches SW52 and SW61 are turned off, the ith output terminal OUTP is connected to the first node 透过 through the switch SW51, and the second output terminal OUTN is connected to the second node N2 via the switch SW62. On the other hand, when the DIN signal is the L level, the switches SW51 and SW62 are in the OFF state, and the switches SW52 and SW61 are in the ON state, and the first output terminal OUTP is connected to the first node N! through the switch SW52, and The second output terminal OUTN is connected to the second node N2 via the switch SW61. Further, when the EN signal is non-sense, the first node Ν1 is connected to the first reference potential through the switch SW53 and the switch SW55, and the second node N2 is connected to the second reference potential through the switch SW63 and the switch SW65. On the other hand, when the EN signal is positive, the first node N1 is connected to the first reference potential through the switches SW53 and SW54 and the switch SW55 connected in parallel, and the second node N2 is transmitted through the switch SW63 connected in parallel. SW64 and switch SW65 are connected to the second reference potential. Fig. 3 is a timing chart of signals in the transmitting device 1A of the first comparative example. As shown in the figure, the flow direction of the current signal outputted from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is determined in accordance with the level of the DIN signal. Moreover, the current signal that is output when the εν signal is sensed is large. In the transmitting device 1A of the first comparative example, when the signal is positive, the switches SW54 and SW64 are turned ON and the currents flowing in the switches sw51, SW52, SW01, and SW62 are large, so that the current is used. A MOS transistor having a large gate width is used as these switches, and the buffers BUFp and BUFn included in the driving circuit 20 required for driving these switches from -13 to 201019298 are also used in larger sizes. Then, the buffers BUFp and BUFn consume large currents whenever the DIN of the DIN signal changes. (Second Comparative Example) Fig. 4 is a schematic configuration diagram of a transmitting device 1B of a second comparative example. The transmitting device 1B of the second comparative example includes a data conversion circuit iA, a drive circuit 20, a main output buffer circuit 31, and a sub output buffer circuit 32. The data conversion circuit 10A and the drive circuit 20 included in the transmission device 1B of the second comparative example have the same configuration as that of the transmission device 1A of the first comparative example. When compared with the transmitting device 1A of the first comparative example, the transmitting device 1B of the second comparative example is replaced with the main output buffer circuit 31 and the sub output buffer circuit 32 instead of the output buffer circuit 30. different.

The main output buffer circuit 31 and the sub output buffer circuit 32 share the first output terminal OUTP and the second output terminal OUTN, and receive signals output from the drive circuit 20, from the first output terminal OUTP and the second output terminal OUTN. A pair of differential transmission lines that have been applied with a terminating resistor to output a current signal. The signal for driving the main output buffer circuit 31 includes a BIASp signal, a BIASn signal, a CTRLp signal, and a CTRLri signal. Moreover, the signal for driving the sub-output buffer circuit 32 includes a BIASp signal, a BIASn signal, a CTRLp signal, a CTRLn signal, an EN signal, and an ENb signal. -14- 201019298 Fig. 5 is a configuration diagram of a main part of a transmitting device 1 of the second comparative example. This figure shows a circuit diagram of each of the drive circuit 20, the main output buffer circuit 31, and the sub output buffer circuit 32. The configuration of the drive circuit 20 is the same as that in the first comparative example. ΰ % The main output buffer circuit 31 includes switches SW1C to SW13 and switches SW2G to SW23. These switches' are preferably formed of a transistor, and are particularly preferably composed of a MOS transistor. When the switch is composed of a MOS transistor, corresponding to the signal input to the gate terminal of the MOS transistor, the transistor is set to an ON state (ON state) and an OFF state (OFF state). Either. The switch SWh is provided between the first node Νι and the first output terminal OUTP. The switch SW12 is provided between the first node N1 and the second output terminal OUTN. The switch SW1G and the switch SW13 are connected in series to each other and are provided between the first node K and the first reference potential (power supply potential). The switch SW21 is provided between the second node N2 and the first output terminal OUTP. The switch SW22 is provided between the second node N2 and the second output terminal OUTN. The switch SW2D and the switch SW23 are connected in series to each other and are provided between the second node N2 and the second reference potential (ground potential), and the switches SWh and SW22 are set to the ON state and the OFF state in response to the CTRLp signal. Either. The switches SW12 and SW21 are set to either the ON state or the OFF state in response to the CTRLn signal. The switches SW1() and SW2〇 are always set to ON when -15-201019298 is set during operation. The switch SW13 is always set to the ON state by the BIASp signal during operation. Further, the switch SW23' is always set to the ON state by the BIASn signal during the operation. Similarly to the first comparative example, in the main output buffer circuit 31, the amount of current flowing between the first output terminal OUTP and the second output terminal OUTN can be adjusted by adjusting the voltages of the BIASp signal and the BIASn signal. . The sub output buffer circuit 32 includes switches SW3Q to SW33 and switches SW4Q to SW43. These switches are preferably formed of a transistor, and are particularly preferably composed of a MOS transistor. When the switch is composed of a MOS transistor, the transistor is set to an ON state (ON state) and an OFF state (OFF state) corresponding to a signal input to a gate terminal of the MOS transistor. Either. The switches SW3〇 to SW33 and the switches SW4〇 to SW43 included in the sub output buffer circuit 32 are compared with the switches SW1C to SW13 and the switches SW2D to SW23 included in the main output buffer circuit 31, and are gate widths. A large MOS transistor is formed. The switch SW31 is provided between the third node N3 and the first output terminal OUTP. The switch SW32 is provided between the third node N3 and the second output terminal OUTN. The switch SW3Q and the switch SW33 are connected in series between the third node N3 and the first reference potential (power supply potential). The switch SW41 is provided between the fourth node N4 and the first output terminal OUTP. The switch SW42 is provided between the fourth node n4 and the second output terminal OUTN. The switch SW4Q and the switch SW43 are connected in series to each other and are provided between the fourth node N4 and the second reference potential (ground potential) -16 - 201019298. The switches SW31 and SW42 are set to the ON state corresponding to the CTRLp signal. And any of the OFF states. The switches SW32 and SW41 are set to either the ON state or the OFF state in response to the CTRLn signal. The switches SW3C and SW4C are set to either the ON state or the OFF state in response to the ΕΝ signal. The switch SW33 is always set to the ON state by the BIASp signal during operation. Further, the switch SW43 is always set to the ON state by the BIASn signal during operation. Similarly to the main output buffer circuit 31, in the sub output buffer circuit 32, the current flowing between the first output terminal OUTP and the second output terminal OUTN can be adjusted by adjusting the voltages of the BIASp signal and the BIASn signal. the amount.

The driving circuit 20, when the DIN signal is clamped, sets the CTRLp signal to the Η level and sets the switches SWh, SW22, SW31&SW42 to the ON state, and sets the CTRLn signal to the L level to turn the switch SW12, SW21, SW32, and SW41 are set to the OFF state. The driving circuit 20 is configured to set the CTRLp signal to the L level and the switches SWh, SW22, SW31, and SW42 to the OFF state when the DIN signal is the L level, and set the CTRLn signal to the Η level to turn the switch SW12, SW21, SW32, and SW41 are set to the ON state. Moreover, the driving circuit 20 sets the switches SW3 〇 and SW 4 C to the OFF state when the ΕΝ signal is non-intelligible ' 'When the EN signal is 有, the switches SW3Q and SW4C are set to the ON state in the main output snubber circuit. In 31, when the DIN signal is clamped on time -17- 201019298, the switch SWn & sw22 is turned ON, and the switches 3\¥12 and SW21 are turned OFF, and the first output terminal OUTP is transmitted through the switch SWM and the first The node N! is connected, and the second output terminal OUTN is connected to the second node N2 via the switch SW22. On the other hand, when the DIN signal is the L level, the switches SWM and SW22 are in the OFF state, and the switches SW12 and SW21 are in the ON state, and the first output terminal OUTP is connected to the first node 透过 through the switch SW12, and 2 The output terminal OUTN is connected to the second node N2 via the switch SW21. Therefore, the flow direction of the current signal output from the main output buffer circuit 31 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN differs depending on the level of the DIN signal. In the sub output buffer circuit 32, when the DIN signal is clamped, the switches SW31 and SW42 are turned ON, and the switches SW32 and SW41 are turned OFF, and the first output terminal OUTP is transmitted through the switch SW31 to the third node N3. The second output terminal OUTN is connected to the fourth node N4 via the switch SW42. On the other hand, when the DIN signal is the L level, the switches SW31 and SW42 are turned OFF, and the switches SW32 and SW41 are turned ON, and the first output terminal OUTP is connected to the third node N3 through the switch SW32. 2 The output terminal OUTN is connected to the fourth node N4 via the switch SW41. Further, in the sub-output buffer circuit 32, when the EN signal is non-sense, the third node N3 is not connected to the first reference potential, and the fourth node N4 is not connected to the second reference potential. On the other hand, when the EN signal is positive, the third node N3 is connected to the first reference potential of 201019298 through the switch SW3 〇 and the switch SW33, and the fourth node N4 is transmitted through the switch SW4 〇 and the switch SW43. 2 reference potential connection. Therefore, when the EN signal is non-sense, the secondary output buffer circuit 32 does not output a current signal. On the other hand, when the EN signal is positive, the secondary output buffer circuit 32 outputs a current signal to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN, and the flow direction of the current signal follows. The level of the DIN signal is different.

The timing chart of each signal in the transmitting device 1B of the second comparative example is the same as that of Fig. 3. In the transmitting device 1B of the second comparative example, when the EN signal is non-sense, the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is only from the main output. The current signal outputted by the buffer circuit 31, the flow direction of the current signal is determined according to the level of the DIN signal. On the other hand, when the EN signal is positive, the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line becomes the main output buffer circuit 31 and the sub output buffer circuit. The current signals output by the respective 32 signals are added, and the flow direction of the current signal is determined according to the level of the DIN signal. Therefore, the current signal that is output when the signal is correct is large. In the transmitting device 1 of the second comparative example, since the current flowing through the switches SW1() to SW13 and the switches SW2 to SW23 included in the main output buffer circuit 31 is small, the gate width can be used. Smaller MOS transistors are used as these switches. However, since the currents flowing through the switches SW30 to SW33 and the switches SW4 to SW43 included in the sub-output buffer circuit 32 are large, the MOS transistors having a large gate width are used as the switches, and The buffers BUFp and BUFn included in the drive circuit 20 required to drive these switches are also larger in size. Then, the buffers BUFp and BUFn consume large currents whenever the DIN of the DIN signal changes. (This embodiment)

Fig. 6 is a schematic block diagram of the transmitting device 1 of the embodiment. The transmitting device 1 of the present embodiment includes a data conversion circuit i, a main drive circuit 21, a sub drive circuit 22, a main output buffer circuit 31, and a sub output buffer circuit 32. The main output buffer circuit 31 and the sub output buffer circuit 32 included in the transmitting device 1 of the present embodiment have the same configuration as that of the transmitting device 1B of the second comparative example. When compared with the transmitting device 1B of the second comparative example, the transmitting device 1 of the present embodiment is replaced with the data conversion circuit 10 instead of the data conversion circuit 10A. The circuit 20 is different from the main drive circuit 21 and the sub drive circuit 22. The data conversion circuit 10 inputs a parallel digital signal Dpara, converts it into a serial digital signal (DIN signal), and outputs the DIN signal of the sequence to the main driving circuit 21 in bit order. The DIN signal contains not only the bits of the parallel digital signal Dpara that are input into the serial digital signal, but also dummy bits between them. Further, the data conversion circuit 10 periodically outputs the -20-201019298 ΕΝ signal to the sense while the DIN signal corresponding to one parallel digital signal is being output. In this example, the signal is one or two times during the period in which the DIN signal corresponding to one parallel digital signal is being output. The time when the EN signal is output as a sense of time is equivalent to the time at which the elements of the DIN signal are output. When the EN signal is output as a valid 値, it is the same as the DIN signal outputted in the previous period, and is output as a DIN signal. In the latter period of the period in which the EN signal is output as a sense, the DIN signal may be the same as the output 値 and the output reversal 値. This EN signal indicates the clock signal. Further, the data conversion circuit 10 receives the input digital signal Dpara and outputs the POL signal to the sub-drive circuit 22. The POL signal is determined until the period when the EN signal is correct. The level is equal to the level of the DIN signal that is output during the period when the EN signal is correct.

The main drive circuit 21 receives the DIN signal output from the data conversion circuit 10, and then outputs a signal for driving the main output buffer circuit 31. The signal used to drive the main output buffer circuit 31 includes a BIASp signal, a BIASn signal, a CTRLlp signal, and a CTRLln signal. The sub-driver circuit 22 receives the EN signal and the POL signal outputted from the data conversion circuit 10, and then outputs a signal for driving the sub-output buffer circuit 32. The signal for driving the sub-output buffer circuit 32 includes a BIASp signal, a BIASn signal, a CTRL2p signal, a -21 - 201019298 CTRL2n signal, a chirp signal, and an ENb signal. Fig. 7 shows a configuration in which the transmission device 1 of the present embodiment has the same configuration of each of the main drive circuit 21, the sub drive circuit 31, and the sub output buffer circuit 32, and the sub output buffer circuit 32. The main drive circuit 21 contains a buffer BUFln. The buffer BUFlp outputs a CTRLlp signal with the same level as the level. A CTRLln signal is generated relative to the input DIN signal. When the main drive circuit 21 is on time, the CTRLlp signal is set to the clamp SW22 to the ON state, and the CTRLln switches SW12 and SW21 are set to the OFF state. The DIN signal is the L-bit punctuality. The CTRLlp switches SWn and SW22 are set to the OFF state, and the switches SW12 & SW21 are set to the sub-drive circuit 22, which includes the buffer BUF2n. The buffer BUF2p outputs a CTRL2p signal having the same level as the level. A CTRL2n signal is generated relative to the POL signal being input. When the sub-driver circuit 22 is on time, the CTRL2p signal is set to the clamp SW42 to the ON state, and the main part of the CTRL2n is constructed. Figure 22. Main output buffer circuit diagram. The main output buffer circuit is the DIN signal buffer BUFln which is input to the second comparison example time unit BUFlp and the buffer. The output level is the logic inversion position. When the DIN signal is accurate, the switch SWu and The signal is set to the L level and the main drive circuit 21 is set to the L level and is turned on and the CTRLln signal is set to the ON state. The BUF2p and the POL signal buffer BUF2n input to the buffer are the logic inversion bits. When the POL signal is accurate, the switch SW31 and the signal are set to the L level. -22- 201019298 The switches SW32 and sw41 are set to the OFF state. The sub-driver circuit 22 sets the switches SW32 and SW41 to the CTRL2n signal to the OFF state when the POL signal is the L level, and sets the CTRL2p signal to the L level and the switches SW31 and SW42 to the OFF state. ON status. Further, the sub-driver circuit 22 sets the switches SW3Q and SW4Q to the OFF state when the EN signal is non-sense. When the EN signal is positive, the switches SW3 and SW4 are set to the ON state. & In the main output buffer circuit 31, when the DIN signal is clamped, the switches SWu and SW22 are turned ON, and the switches SW12 and SW21 are turned OFF, and the first output terminal OUTP is transmitted through the switch SWh and the first The node ratio is connected, and the second output terminal OUTN is connected to the second node N2 via the switch SW22. On the other hand, when the DIN signal is at the L level, the switches SWu and SW22 are turned OFF, and the switches SW12 & SW21 are turned ON, and the first output terminal OUTP is connected to the first node via the switch SW12, and 2 φ, the output terminal OUTN is connected to the second node N2 via the switch SW21. Therefore, the flow direction of the current signal outputted from the main output buffer circuit 31 to the differential transmission line via the first output terminal OUTP and the second output terminal OUTN differs depending on the level of the DIN signal.

In the sub output buffer circuit 32, when the POL signal is in the Η level, the switches SWs1 and SW42 are in the ON state, and the switches SW32 and SW^ are in the OFF state, and the first output terminal OUTP is transmitted through the switch SW^ and the third. The node N3 is connected, and the second output terminal OUTN is connected to the fourth node N4 via the switch SW42. On the other hand, when the POL -23-201019298 signal is the L level, the switches SW31 and SW42 are turned OFF, and the switches SW32 and SW41 are turned ON, and the first output terminal OUTP is transmitted through the switch SW32 and the third node N3. The second output terminal OUTN is connected to the fourth node N4 via the switch SW41. Further, in the sub-output buffer circuit 32, when the EN signal is non-sense, the third node N3 is not connected to the first reference potential, and the fourth node N4 is not connected to the second reference potential. On the other hand, when the EN signal is positive, the third node N3 is connected to the first reference potential through the switch SW3Q and the switch SW33, and the fourth node N4 is transmitted through the switch SW40 and the switch SW43 to the second reference potential. connection. Therefore, when the EN signal is non-sense, the secondary output buffer circuit 32 does not output a current signal. On the other hand, when the EN signal is positive, the secondary output buffer circuit 32 outputs a current signal to the differential transmission line via the first output terminal 〇υΤΡ and the second output terminal OUTN, and the flow direction of the current signal is It varies with the level of the POL signal. Fig. 8 is a timing chart of signals in the transmitting device 1 of the embodiment. In the transmitting device 1 of the present embodiment, when the EN signal is non-sense, the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line is buffered only from the main output. The current signal outputted by the circuit 3 1 'the flow direction of the current signal is determined corresponding to the level of the din signal. On the other hand, when the EN signal is correct, 'the POL signal level is equal to the DIN signal level, and the current signal output from the first output terminal OUTP and the second output terminal OUTN to the differential transmission line' The system becomes the sum of the current signals outputted by the main output buffer circuit 31 and the sub-input-24-201019298 out buffer circuit 32, and the flow direction of the current signal is determined according to the level of the DIN signal. Therefore, when the EN signal is correct, the current signal output is larger.

In the transmitting device 1 of the present embodiment, the main drive circuit 21 for driving the main output buffer circuit 31 is provided, and the sub drive circuit 22 for driving the sub output buffer circuit 32 is provided. Since the currents flowing in the switches SW1Q to SW13 and the switches SW2 to SW23 included in the main output buffer circuit 31 are small, MOS transistors having a small gate width can be used as these switches. Therefore, the buffers BUFlp and BUFln included in the main drive circuit 21 for driving the main output buffer circuit 31 are sufficient, and the power consumption can be reduced. On the other hand, since the sub output buffer circuit 32 The switch SW3 is included. Since the current flowing through the ~SW33 and the switches SW40 to SW43 is large, a MOS transistor having a large gate width is used as these switches. However, in the sub-output buffer circuit 32, before the EN signal is sensed, the level of the POL signal is determined, so that the states of the switches SW31, SW32, SW41, and SW42 are also determined, and the εν signal becomes meaningful. The switches SW3Q and SW4Q are turned ON, so a current signal is output. Therefore, the buffers BUF2p and BUF2n included in the sub-drive circuit 22 for driving the sub-output buffer circuit 32 do not need to shift the output levels of the CTRL2p signal and the CTRL2n signal at a high speed, so that a smaller size is sufficient. In addition, the buffers BUF2p and BUF2n are outputted at the level of -25-201019298. Therefore, the power consumption of the buffers BUF2p and BUF2n is lowered. As described above, in the transmitting device 1 of the present embodiment, the sub-driving circuit 22 is provided in addition to the main driving circuit 2, but compared with the transmitting device 1A and the second comparative example of the first comparative example. In either case of the transmitting device 1B, not only the power consumption can be reduced, but also the layout area can be reduced when it is shrunk to the semiconductor substrate. [Possibility of industrial use] It is applicable to a transmission device that outputs a current signal having a differential output level of 2 使用 using a common differential transmission line, and can reduce the use of a power transmitting device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram of a transmitting device 1A of a first comparative example. Fig. 2 is a configuration diagram of a main part of a transmitting device 1A of a first comparative example. Fig. 3 is a timing chart of signals in the transmitting device 1A of the first comparative example. Fig. 4 is a schematic block diagram of the transmitting device 1B of the second comparative example. Fig. 5 is a configuration diagram of a main part of a transmitting device 1B of a second comparative example. -26-201019298 [FIG. 6] FIG. 6 is a schematic configuration diagram of the transmitting device 1 of the present embodiment. FIG. 7 is a diagram showing the configuration of a main part of the transmitting device 1 of the present embodiment [FIG. 8] Fig. 8 is a timing chart of signals in the transmitting device 1 of the embodiment.

[Description of main component symbols] 1. ΙΑ, 1B: Transmitting device 10, 10A: data conversion circuit 2 0: drive circuit 2 1 : main drive circuit 2 2 : sub-drive circuit 30: output buffer circuit 3 1 : main output buffer Circuit 32: secondary output buffer circuit -27,

Claims (1)

201019298 VII. Application for patents: 1. A type of transmitting device belonging to a first output terminal and a second output terminal having a pair of differential transmission lines connected to a terminal resistor have been modified by The first output terminal and the second output terminal forwardly record the flow direction of the current signal outputted by the differential transmission line to transmit a digital signal. When the EN signal is positive, the output device of the current signal is changed. Characteristic is have: The main output buffer circuit includes: a switch SWM provided between the first node and the first output terminal; and a switch SW12 provided between the first node and the second output terminal; and a switch SW2 between the second node and the first output terminal, and a switch SW22 provided between the second node of the front and the second output terminal of the front; the switches SWU, SW12, SW21, and SW22 are formed by transistors. The first node is connected to the first reference potential, the second node is connected to the second reference potential, and the sub-output buffer circuit is provided between the third node and the first output terminal. a switch SW31; and a switch SW32 provided between the third node and the second output terminal of the preamble; and a switch SW41 provided between the fourth node and the first output terminal; and the fourth node of the preamble a switch SW42 between the second output terminal and the switch SW3Q provided between the third node of the preamble and the first reference potential, and a switch between the fourth node of the preamble and the second reference potential of the preamble SW40: These switches SW3, SW32, SW41, SW42, S W3. And the SW40 series -28-201019298 is composed of a transistor; and the main driving circuit is that the current digitizing signal is the punctuality, the pre-recording switches SWn and SW22 are set to the ON state, and the pre-recording switches SW12 and SW21 are set to the OFF state, When the current bit signal is L-bit, the pre-recording switches SW! t and SW22 are set to the OFF state and the pre-recording switches sw12 and SW21 are set to the ON state; the sub-driving circuit is the pre-recording when the current EN signal is non-independent. The switches SW3〇 and SW4 are set to the OFF state. When the current recording signal is correct, the pre-recording switches SW3Q and SW4Q are set to the ON state. The reading level has been determined during the period in which the EN signal is correct. When the P〇L signal is punctual, the pre-recording switches SW31 and SW42 are set to the ON state and the pre-recording switches SW32 and SW41 are set to the OFF state. When the current POL signal is the L-level, the pre-recording switch SW31&SW42 is set to OFF. The state and the pre-recording switches SW32 and SW41 are set to the ON state. -29-