JP2000200124A - Semiconductor integrated circuit and semiconductor integrated circuit system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit system capable of reducing current consumption in a data transmission system of a current drive type for high-speed data transmission. SOLUTION: This system is provided with a data line pair (Data-A and Data-XA) and a strobe line pair (Strobe-B and Strobe-XB) for transmitting data between first and second chips 1 and 2. A control circuit 6 provided in the first chip 1 controls an output circuit 5. The output circuit 5 supplies a DC current from a power source to a data line Data-A for instance and the input circuit 7 of the second chip 2 returns the DC current to the output circuit 5 through terminating resistors RA1 and RA2 and the data line Data-XA. The output circuit 5 successively supplies the returned DC current to a strobe line Strobe-B, the input circuit 7 further returns it through the terminating resistors RB1 and RB2 and the strobe line Strobe-XB to the output circuit 5 and the returned current is made to flow into the ground. Thus, the current consumption is reduced half/as compared with the case of respectively current driving the data line pair and the strobe line pair.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system which transmit data at high speed and consume low power.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit typified by an IEEE1394 physical layer LSI has a technology for transmitting data between devices at a high speed in order to realize a system for performing a large amount of data processing at a high speed such as a multimedia. Currently, a data transmission rate of 200 Mbps has been realized, and a 400 Mbps semiconductor integrated circuit has been sampled. At the research level, high-speed data transmission technologies exceeding 1 Gbps have also been developed.

In the IEEE1394 physical layer LSI, when data transmission is performed, the transmitting side outputs data in the form of a DC current to a differential twisted pair cable. A resistance element is connected between the twisted pair cables, and a potential difference between the twisted pair cables that appears due to a current flowing through the resistance element becomes an input on the receiving side. Also, this IEEE1394 physical layer LSI
A data transmission method called a link method is adopted. For data transmission, two pairs of transmission lines, a data line pair and a strobe line pair, are used for one port. The IEEE1394 specifications are shown in draft standard ver8.4.

[0004]

However, the aforementioned IE
In the technology using the EE1394 physical layer LSI, as described above, there is a problem in that a current always flows to output a DC current to the twisted pair cable, and the current consumption of the output unit is large.
In particular, when the number of ports increases, an increase in current consumption becomes a serious problem. Further, in the DS link system, data transition occurs only in one of the data line pair or the strobe line pair, but the data transition occurs in the other without the data transition.
The DC current continues to flow, and the constant flow of the DC current also causes an increase in current consumption.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an IEEE
An object of the present invention is to provide a semiconductor integrated circuit and a semiconductor integrated circuit system having an optimal configuration for reducing current consumption in a current-driven data transmission system for high-speed data transmission such as 1394.

[0006]

In order to achieve the above object, according to the present invention, when transmitting data using a plurality of data bus pairs such as a data line pair and a strobe line pair, any one of the data bus pairs is used. Current driving is performed, and the current flowing through this data bus pair is used for current driving of another data bus pair.

That is, a semiconductor integrated circuit system according to the first aspect of the present invention includes a first chip and a second chip, and a plurality of complementary data buses terminated by a resistance element. A semiconductor integrated circuit system for performing data transmission between said first and second chips using a data bus, comprising: a current driving type driving circuit for current driving said plurality of complementary data buses; And a path changing means for changing the current path between the power supply and the ground.

According to a second aspect of the present invention, in the semiconductor integrated circuit system according to the first aspect, each of the plurality of complementary data buses has one of a data line pair from the first chip to the second chip. And a current flowing from the second chip to the first chip.

Further, according to a third aspect of the present invention, in the semiconductor integrated circuit system according to the first aspect, there is provided an input circuit for inputting a potential difference appearing at a terminating resistor of each complementary data bus, and the input circuit comprises: It is characterized by a wide-range input circuit including the entire range of the central potential of the potential difference appearing at the terminating resistor of each of the complementary data buses.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit system according to the first aspect, the center potential of the potential difference appearing at the terminating resistors of the plurality of complementary data buses is entirely on the power supply potential side. Or, it is characterized by being biased toward the ground side.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit to which a plurality of data bus pairs terminated by a resistance element are connected, wherein the plurality of data bus pairs are connected between a power supply and a ground. And a path changing means for changing the current path, wherein the path changing means is connected to a first current source connected to a first power source and a second power source. A second current source;
First and second switch elements connected to a current source for controlling supply of current to any of the plurality of data bus pairs; and the plurality of data bus pairs connected to the second current source. And a fifth switch element for connecting between the plurality of data bus pairs and a third and fourth switch element for performing control for extracting a current from any of the other data bus pairs.

Further, according to a sixth aspect of the present invention, in the semiconductor integrated circuit of the fifth aspect, the path changing means further includes a control circuit for controlling the first to fifth switch elements, The control circuit is arranged on the same chip together with the first to fifth switch elements of the path changing means.

In addition, a semiconductor integrated circuit according to a seventh aspect of the present invention is a semiconductor integrated circuit to which a plurality of data bus pairs terminated by a resistance element are connected, wherein the plurality of data bus pairs are connected to a power supply and a ground. A single current path between
And a path changing means for changing the current path, wherein the path changing means is connected to a first power supply and supplies a current to any one of the plurality of data bus pairs; And a second current source that is connected to a power supply and extracts current from any of the plurality of data bus pairs, and a first through a data line that connects data lines between adjacent data bus pairs of the plurality of data bus pairs. A fourth switch element.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the seventh aspect, the path changing means further includes a control circuit for controlling the first and second switch elements, The control circuit is arranged on the same chip together with the first and second switch elements of the path changing unit.

Further, according to a ninth aspect of the present invention, in the semiconductor integrated circuit according to the fifth, sixth, seventh or eighth aspect, the semiconductor integrated circuit is separately provided corresponding to each data bus pair, and the data is stored in the corresponding data bus pair. In the inactive state where no data is transmitted,
A pseudo circuit is provided that sets the inactive data bus pair to the same state as the active state when viewed from a data bus pair other than the inactive data bus pair.

According to the above-described configuration, according to the present invention, when any one of the data bus pairs is driven by a current in a current-driven data transmission system such as IEEE1394 for high-speed data transmission. Since this current is used for driving the current of another data bus pair, the current consumption required for data transmission can be effectively reduced.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit system according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the principle of a semiconductor integrated circuit system according to the present invention.

In FIG. 1, 1 is a first chip, 2 is a second chip, DBA and DBB are data bus pairs (complementary data buses), RA and RB are arranged at the ends of data bus pairs DBA and DBB. Terminating resistor, VDD is a power supply, and VSS is a ground. The two data bus pairs DBA and DBB are provided between the first chip 1 and the second chip 2. First chip 1
Is provided with a data bus driving circuit 4.
Drives the data bus pair DBA, DBB with a DC current. At the time of this current drive, the voltage at the input section of the second chip 2 is determined by the DC current flowing through the terminating resistors RA and RB.

In the present invention, in order to reduce the current consumption caused by the DC current flowing through the two data bus pairs DBA and DBB, the DC current flowing through one data bus pair DBA is not directly flown to the ground VSS. It is used to drive the other data bus pair DBB. That is, the driving circuit 4 of the first chip 1
Drives a current from the power supply VDD to the data bus pair DBA.
One data line of the data bus pair DBA sends a current from the first chip 1 to the second chip 2, and the other data line sends a current flowing through the terminating resistor RA from the second chip 2 to the first chip. To chip 1. In the first chip 1, the drive circuit 4 further sends the returned current to one data line of the data bus pair DBB, and similarly, the current returned via the other data line is supplied by the drive circuit 4. Flowed into the ground VSS. By employing this configuration, the DC current flowing through the two data bus pairs DBA and DBB is reduced by half.

FIG. 2 is a timing chart schematically showing the above operation. The potentials of the two data bus pairs DBA and DBB are at different levels due to the termination resistors RA and RB and the voltage drop in the drive circuit 4, as shown in FIG.

Here, in the present principle, the current flowing through the two data bus pairs DBA and DBB is configured to flow through one current path, but three or more data bus pairs are connected to the power supply voltage. The same configuration is possible in a range where the voltage drop due to the current is smaller than the value. In this case, the DC current is reduced to 1 / the number of data bus pairs.

FIG. 3 shows an embodiment in which the above principle is applied to IEEE1394 data transmission.

In FIG. 3, an output circuit 5 and a control circuit 6 are arranged in the data bus drive circuit 4 of the first chip 1. These two circuits 5 and 6 constitute the path changing means 10. Data-A and Data-XA are data line pairs (complementary data bus), and Strobe-B and Strobe-XB are strobe line pairs (complementary data bus). The output circuit 5 includes the data line pair Data-A, Data-XA and the strobe line pair Strobe-
Current drive similar to the principle of FIG. 1 is performed on B and Strobe-XB. In the present embodiment, for example, a DC current is supplied from the power supply VDD to one data line Data-A of the data line pair,
The DC current is returned to the output circuit 5 through the other data line Data-XA via the terminating resistors RA1 and RA2. Next, the output circuit 5
Supplies the returned DC current to one strobe line Strobe-B of the strobe line pair. Finally, the termination resistors RB1, R
The current returning through the other strobe line Strobe-XB via B2 is passed by the output circuit 5 to the ground VSS.

The control circuit 6 is configured such that the output circuit 5 includes a data line pair Data-A, Data-XA and a strobe line pair Strobe-A.
B, Strobe-XB and termination resistors RA1, RA2, RB1, RB2 are controlled to flow from power supply VDD to ground VSS through a single current path, and output circuit 5 is controlled to change this current path in various ways. I do.

On the other hand, an input circuit 7 is provided on the second chip 2. This input circuit 7 operates with a potential difference appearing at both ends of the terminating resistors RA2 and RB2 as an input. Terminating resistor RA
2.The potential difference appearing at both ends of RB2 is the same because DC current flows, but the potential level itself differs greatly due to the voltage drop, and the input from the data line pair Data-A, Data-XA and the strobe line The input timing differs between the input from the pair Strobe-B and Strobe-XB. However, in the LSI of the IEEE 1394 standard adopting the DS link system, the above-mentioned timing shift does not cause a serious problem due to the characteristics of the DS link system. That is, in the DS link system, when data transmitted by the data line pair Data-A, Data-XA changes, data is fetched using the edge of the changed data, and when the data does not change, This is because the strobe signal transmitted by the strobe line pair Strobe-B and Strobe-XB changes to take in data. In other words, data is fetched by itself only at the strict data fetch timing when the data changes, and if the same value continues without changing the data, even if the strobe signal is slightly shifted, the data of the same value is fetched reliably. It is. Therefore, adopt the DS link method
In an LSI such as the IEEE1394 standard, as described in the principle of the present method, the effect of reducing current consumption can be fully utilized.

The input circuit 7 of the second chip 2
It can be configured with an internal configuration as shown in FIG. The input circuit of FIG. 4 includes the data line pair Data-A, Data-XA and the strobe line pair Strobe-B, Strobe-XB.
2. A wide-range rail-to-rail circuit that includes the entire range of the central potentials (common mode levels) V0A and V0B (see FIG. 2) of the potential difference appearing in RB2. Therefore, even if the two common mode levels V0A and V0B are different from each other, the Rail-to-Rail circuit can operate the data line pairs Data-A and Data-X
The data of A and the strobe line pairs Strobe-B and Strobe-XB can be captured at the same timing.

It is not always necessary to configure the input circuit 7 with the wide-range type rail-to-rail circuit. For example, a resistor is arranged between the power supply VDD and the ground VSS, and the data line pair Da is arranged in accordance with the position of the resistor.
ta-A, Data-XA and strobe line pair Strobe-B, Strobe-
If both the common mode levels V0A and V0B of XB are biased toward the power supply voltage side or the ground side, a rail-to-rail circuit is unnecessary.

FIG. 5 shows the internal configuration of the output circuit (semiconductor integrated circuit) 5 of this embodiment shown in FIG. In the figure, VDD is a power supply (first power supply), VSS is ground (second power supply).
, IS1 and IS2 are first current sources connected to the power supply VDD, and IS3 and IS4 are second current sources connected to the ground VSS.
Current source. SW1 and SW2 are first and second switch elements connected to the current sources IS1 and IS2, respectively, and SW8 and SW9 are third and fourth switch elements connected to the current sources IS3 and IS4, respectively. SW3 to SW7 are five switch elements as fifth switch elements disposed between the first to fourth switch elements. Data line pair Data-A, Da
Data-A of ta-XA is between two switch elements SW1 and SW3,
The other Data-XA of the data line pair has two switch elements SW2, S
One of strobe wire pairs Strobe-B and Strobe-XB between W4
Strobe-B is between two switch elements SW7 and SW9, and the other strobe line pair Strobe-XB is two switch elements SW6 and SW
Each is connected between eight.

The current sources IS1 to IS4 have the same current driving capability and drive the same current. Two current sources IS1 and IS2 form a pair, and the other two current sources IS3 and IS4 form a pair. Source IS
One of IS1 and IS2 drives a current to the data line pair Data-A and Data-XA, and one of the current sources IS3 and IS4 draws current from the strobe line pair Strobe-B and Strobe-XB.
For example, when the current source IS1 drives current, the other current source IS2 does not drive, and when the current source IS3 draws current, the other current source IS4 does not draw current. The two current sources IS1 and IS2 are shared, and the other two current sources IS3 and IS4
May be shared, and each may be used as one current source.

As shown in FIG. 6, each switch element SW1 to SW9 supplies the data line pair Data-A, Data-XA and the strobe line pair Strobe-B, Strobe-XB to what data (H or L level). Is turned on and off by the control circuit 6 shown in FIG. When the switch elements SW1 to SW9 are driven in any combination, the current flowing from the power supply VDD to the ground VSS is equal to the data line pair Data-A, Data-XA and the strobe line pair Strobe-.
B and Strobe-XB are controlled by the control circuit 6 so as to flow as a single current path, and the data line pairs Data-A and Data-A
-Strobe line pair Strobe- using DC current to drive XA
It has a configuration that can drive B and Strobe-XB.

(Modification of Output Circuit) FIG. 7 shows a modification of the output circuit 5 used in the semiconductor integrated circuit system of the present embodiment.

In the output circuit 5 'shown in FIG.
VSS is ground, IS11 and IS12 are connected to the power supply VDD.
Current sources, IS13 and IS14, are connected to ground VSS
Current sources, SW11, SW12, SW17 and SW18 are switch elements, SW13
To SW16 are first to fourth switch elements, Data-A,
Data-XA is a data line pair, and Strobe-B and Strobe-XB are strobe line pairs.

The output circuit 5 'shown in FIG.
The same operation as the output circuit 5 shown in FIG. 5 is performed. Since the current-driven output circuit 5 that continues to supply the DC current also benefits from the voltage drop in the switch element, it is important to reduce the number of switch elements in the current path. In the output circuit 5 'of this modification, four switch elements SW13 to SW16 are arranged between the data line pair Data-A, Data-XA and the strobe line pair Strobe-B, Strobe-XB. Switch element SW13
Connects the other data line pair Data-XA and one strobe line pair Strobe-B, and the switch element SW14 connects one data line pair Data-A and one strobe line pair Strobe-B
And the switching element SW15 is connected to the other of the data line pair.
Data-XA is connected to the other strobe line pair Strobe-XB, and switch element SW16 connects one data line pair Data-A and the other strobe line pair Strobe-XB.

In the output circuit 5 of FIG. 5, a maximum of five switch elements are used to drive two data bus pairs with the same current path. On the other hand, in the present modification, only a maximum of three switch elements are used. Not through. Therefore, since the voltage drop in the output circuit 5 'is reduced, it is possible to drive more data bus pairs in the same current path than in the output circuit 5 of FIG.

Also in this modification, as shown in FIG.
Each of the switch elements SW11 to SW18 is turned on / off by the control circuit 6 in accordance with what data is transmitted to the data bus pair. When both the output circuits 5 and 5 'of FIGS. 5 and 7 are incorporated in a semiconductor integrated circuit, a control circuit 6 for performing switching control shown in FIGS. 6 and 8 is provided at a stage preceding the output circuits 5 and 5'. It is provided in the chip 1.

(Other Modifications of Output Circuit) FIG. 9 shows another modification of the output circuit used in the semiconductor integrated circuit system of the present embodiment.

In the output circuit 5 ″ shown in FIG.
Is a current source, SW21 to SW40 are switch elements, Data-A, Data-X
A, Data-B, Data-XB, Data-C, and Data-XC are each a data bus pair of each port, RD35 to RD40 are pseudo termination resistors, VDD is a power supply, and VSS is a ground. Output circuit 5 ″ shown in FIG.
Are connected to three data bus pairs, but basically perform the same operation as the output circuit 5 'of FIG.

In this modified example, the feature of the output circuit 5 ″ is that, when each port is made inactive, a pseudo circuit that behaves as if the port is operating is provided. For example, when the ports of the data bus pair Data-A and Data-XA are deactivated, simply disconnecting the output will not allow the other data bus pair Data-A to be driven in the same current path.
The impedance of the system of the B, Data-XB, Data-C, and Data-XC ports changes, and the voltage levels of these two ports greatly change. As a result, the receiving ability of the receiving side connected to these two ports is greatly changed,
Timing adjustment when operating at high speed is not appropriate.
In the present modification, a pseudo circuit composed of a resistor and a switch element is provided in order to make all the ports operate even when there is a port inactivated to solve this problem.

That is, the pseudo circuit 11 composed of the resistor RD35 and the switch element SW35, the resistor RD36 and the switch element SW
The pseudo circuit 12 constituted by 36 is a data bus pair Data-A,
For the Data-XA, the pseudo circuit 13 composed of the resistor RD37 and the switch element SW37 and the pseudo circuit 14 composed of the resistor RD38 and the switch element SW38 are data bus pairs Data-B and Data-X.
The pseudo circuit 15 composed of the resistor RD39 and the switch element SW39 and the pseudo circuit 16 composed of the resistor RD40 and the switch element SW40 are for data bus pairs Data-C and Data-XC.

For example, a data bus pair Data-A, Data-XA
Switch ports SW35 and SW36
Is turned on, a current flows through the pseudo termination elements RD35 and RD36,
A voltage level is applied to the other two ports as if a current had flowed through the data bus pair Data-A and Data-XA. With the above configuration, even when there is an inactive port, the circuit on the receiving side can operate under the same conditions as when all ports are operating.

Also in this modification, as shown in FIG. 10, each switch element SW21 to SW40 is turned on by the control circuit 6 in accordance with what data is transmitted to each data bus pair.
-Switch off. When the output circuit 5 ″ of FIG. 9 is also incorporated in a semiconductor integrated circuit, it is necessary to provide a control circuit 6 for performing the control of FIG. 10 at a stage preceding the output circuit 5 ″.

In this modification, when the voltage of the power supply VDD is set to 3 V, three data bus pairs (Data-A, Data-XA),
200mv for (Data-B, Data-XB) and (Data-C, Data-XC) respectively
It was confirmed by the simulation that the amplitude of the above was obtained.

[0044]

As described above, according to the first to ninth aspects of the present invention, in a current-driven data transmission system for high-speed data transmission such as IEEE1394,
Since the current at the time of driving one of the data bus pairs is used for driving the current of another data bus pair, the current consumption required for data transmission can be effectively reduced.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a semiconductor integrated circuit system of the present invention.

FIG. 2 is a diagram showing a schematic timing chart according to the principle of the semiconductor integrated circuit system of the present invention.

FIG. 3 is a diagram showing an embodiment of a semiconductor integrated circuit system in which the principle of the present invention is adapted to IEEE1394.

FIG. 4 is a diagram showing a specific configuration of an input circuit provided in the semiconductor integrated circuit system of the embodiment.

FIG. 5 is a diagram showing a specific configuration of an output circuit provided in the semiconductor integrated circuit system of the embodiment.

FIG. 6 is an operation explanatory diagram of a control circuit that controls the output circuit.

FIG. 7 is a diagram showing a modified example of the output circuit provided in the semiconductor integrated circuit system according to the embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of a control circuit that controls the output circuit.

FIG. 9 is a diagram showing another modified example of the output circuit provided in the semiconductor integrated circuit system according to the embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of a control circuit that controls the output circuit.

[Explanation of symbols]

1 First chip 2 Second chip DBA, DBB Data bus pair (complementary data bus) RA, RB, RA1, RA2, RB1, RB2 Termination resistor VDD power supply (first power supply) VSS ground (second power supply) 4) Drive circuit 5, 5 ', 5''output circuit 6 Control circuit Data-A, Data-XA Data line pair (complementary data bus), (Data bus pair) Strobe-B, Strobe-XB Strobe line pair ( (Complementary data bus), (data bus pair) 7 input circuit IS1, IS2, IS11, IS12 first current source IS3, IS4, IS13, IS14 second current source SW1, SW13 first switch element SW2 second Switch elements SW3 to SW7 Fifth switch element SW8 Third switch element SW9 Fourth switch element SW13 First switch element SW14 Second switch element SW15 Third switch element SW16 Fourth switch element 10 Path changing means 11-16 pseudo circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Hirata 1006 Kazuma Kadoma, Osaka Pref.Matsushita Electric Industrial Co., Ltd. (72) Inventor Yukio Arima 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Tadahiro Yoshida 1006 Odoma, Kadoma, Osaka Pref. No. 1006, Kazuma, Kadoma, Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroyuki Yamauchi 1006, Kazuma, Kadoma, Kazuma, Osaka Prefecture F-term (reference) 5K029 AA11 AA13 CC01 DD04 DD13 DD23 EE02

Claims (9)

[Claims] A first chip and a second chip; and a plurality of complementary data buses terminated by a resistance element, wherein the first and second chips are provided using the plurality of complementary data buses.
A semiconductor integrated circuit system for performing data transmission between chips, comprising: a current driving type driving circuit for current driving the plurality of complementary data buses; and a circuit for connecting the plurality of complementary data buses between a power supply and a ground. A semiconductor integrated circuit system comprising: a current path; and a path changing means for changing the current path. 2. The plurality of complementary data buses, wherein one of a data line pair passes a current from the first chip to the second chip, and the other of the data line pairs flows from the second chip to the first chip. 2. The semiconductor integrated circuit system according to claim 1, wherein a current flows. 3. An input circuit for inputting a potential difference appearing at a terminating resistor of each complementary data bus, wherein the input circuit includes the entire range of the central potential of the potential difference appearing at the terminating resistor of each complementary data bus. 2. A wide-range input circuit.
13. The semiconductor integrated circuit system according to claim 1. 4. The semiconductor integrated circuit system according to claim 1, wherein a central potential of a potential difference appearing at terminating resistors of said plurality of complementary data buses is biased toward a power supply potential side or a ground side as a whole. 5. A semiconductor integrated circuit to which a plurality of data bus pairs terminated by a resistance element are connected, wherein said plurality of data bus pairs are a single current path between a power supply and a ground, and said current path is A path changing means for changing a current, a first current source connected to a first power supply, a second current source connected to a second power supply, and the first current A first and a second switch element connected to a current source and controlling supply of a current to any one of the plurality of data bus pairs; and a second switch element connected to the second current source and connected to the second data bus pair. 3. A semiconductor integrated circuit comprising: third and fourth switch elements for performing control for extracting a current from any one of the above, and a fifth switch element for connecting the plurality of data bus pairs. 6. The path changing unit further includes a control circuit for controlling the first to fifth switch elements, and the control circuit is provided together with the first to fifth switch elements of the path change unit. 6. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is arranged on the same chip. 7. A semiconductor integrated circuit to which a plurality of data bus pairs terminated by a resistance element are connected, wherein said plurality of data bus pairs are a single current path between a power supply and a ground, and said current path is And a path changing unit connected to a first power supply for supplying a current to any one of the plurality of data bus pairs, and a path changing unit connected to a second power supply. A second current source for drawing current from any of the plurality of data bus pairs; and a first to fourth switch for connecting data lines between adjacent data bus pairs among the plurality of data bus pairs. A semiconductor integrated circuit comprising: an element; 8. The path changing unit further includes a control circuit for controlling the first and second switch elements, wherein the control circuit is provided together with the first and second switch elements of the path changing unit. 8. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is arranged on the same chip. 9. An inactive state provided separately for each data bus pair and in which data is not transmitted to the corresponding data bus pair, when viewed from a data bus pair other than the inactive data bus pair. 9. The semiconductor integrated circuit according to claim 5, further comprising a pseudo circuit for setting said inactive data bus pair to the same state as said active state.