JP2000353035A - Signal communication interface formed by integrating single-end type and differential type - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface circuit to realize both of single-end output having compatibility with many existent external device and differential output by which noise reduction and lowering of power interface in an interface with the external devices are expected by using only the minimum number of pins. SOLUTION: The interface circuit 100 is provided with single-end electric circuits 106, 107 and a differential electric circuit 108, single-end and differential signals are switched by complementary ENSE and ENDF signals. Data transfer width is set as word width, data is transferred once by every clock in a single- end mode, however, the data is transferred twice by every clock in each edge of the clock in a differential mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to an interface circuit. More specifically, the present invention
The present invention relates to an interface circuit for providing a signal output from an OS image sensor to an external digital signal processor in a single-ended or differential manner. In addition, this application
A continuation-in-part of U.S. application Ser. No. 09 / 062,343, filed Apr. 17, 1998.

[0002]

2. Description of the Related Art One of the advantages of a CMOS image sensor (CMOS imager) over a CCD imager is that a CMOS imager chip can include electrical circuits for digital signal processing. In practice, signal processing is more often performed on companion chips to increase application flexibility. However, CMOS imagers often incorporate analog-to-digital converters for the purpose of converting analog signals into digital bit streams that can be processed by companion chips. Then, the digitized information is transferred to a companion chip or another external device (for storing, processing, or transmitting an image). Single-ended interfaces are the most common and simplest implementation for data transfer. Figure 1 shows an example of a single-ended interface. CMO
The driver 2 in the S imager 1 outputs a signal to the companion processing chip 3. Receiver 4 receives the signal and amplifies it for use in subsequent processing. FIG.
FIG. 2 is a circuit diagram showing one possible implementation of the single-ended interface in a CMOS.

[0003] Differential interfaces can minimize power and noise generation as compared to single-ended interfaces, but typically require two signal lines.
Double. FIG. 3 shows an example of a conventional low voltage differential signal (LVDS) circuit 11. The circuit of the LVDS 11 includes a current source I1 (nominal value: 3.5 mA) for driving one of the differential pair lines 13 and 15. Because the receiver 17 has a high DC impedance (does neither source nor sink DC current), the majority of the drive current flows through the 100Ω termination resistor R1, producing a voltage of approximately 350 mV at the inputs 19, 21 of the receiver. . When the driver 23 switches, it changes the direction of the current flowing through the resistor R1, thereby
A valid "1" or "0" logic state is generated.

There are several important ways to save power with LVDS technology. Load (100Ω termination resistor R
The power dissipated for 1) is only 1.2 mW. By comparison, RS422 drivers usually have 10
When sending 3 volts to a 0Ω termination resistor, the power consumption is 90
mW, which is 75 times the LVDS. Similarly, LVD
The power supply current required by the S device 11 is PECL / ECL
About one tenth of the device.

[0005] Apart from the power dissipated in the load and the static Icc current, LVDS further reduces the power required by the system through a CMOS current mode driver design. This design greatly reduces the frequency component of Icc. Icc vs. Frequenc on LVDS
The plot of y is substantially 10M for the quad device.
Hz and 100 MHx (<50 m
A, total of driver + receiver at 100 MHz). In contrast, for the single-ended case, TTL / CMOS transceivers see dynamic power consumption that increases exponentially with frequency.

[0006] To help ensure reliability, LV
The DS receiver 17 has a fail-safe function of setting an output under a certain fault condition to a known logical state (HIGH). These conditions include open, short, and interruption of the receiver input. Even if the driver 23 loses power, becomes unusable, or goes out of line, and the input is interrupted while the receiver 17 is turned on, the fail-safe function is used to output the receiver. Remains in a known state.

If one of the fault conditions occurs when the LVDS receiver 17 does not have a fail-safe feature,
External noise above the receiver threshold can trigger any output and cause errors. Receivers without failsafe may furthermore even vibrate under certain fault conditions. The fail-safe function ensures that the receiver output under a fault condition is HIGH, so that it does not become an unknown state.

FIG. 4 shows a pending US application Ser. No. 09 / 062,34.
3 illustrates a CMOS video image detection circuit according to the preferred embodiment described in FIG. This electrical circuit
CMOS image sensor chip 50 and image processing chip 5
2 is included. CMOS image sensor chip 50 typically includes a number of CMOS pixel sensors that respond to light and emit analog signals representing an image. Then, these analog signals are converted into A by the ADC circuit.
D converted to digital signals Din0, Din1. . . Produce Dinn. The image processing chip 52 includes a data processor 5 that performs various image data processing such as compression and color processing.
3 inclusive.

[0009] The processor 53 may be operated by software or realized by hardware. As can be seen, the circuit of FIG. 4 uses a plurality of LDVS circuits 11. Each circuit 11 has its own driver 54 and its own receiver 56. Each driver 54 has an input signal Din0, Din1. . . Receive Dinn. They are,
For example, a digital logic level of 3.3 volts for a logical value "1" and 0 volts for a logical value "0". The change in state of these signals is sent to the respective receiver 56 on the difference line. Each receiver 56 has its own output signal Douto, Dout1. . . Doutn, which are on the order of hundreds of millivolts.

On the imager, it is possible to use the differential interface shown in FIG. 4 instead of the single-ended interface. However, the existing image processor only supports the normal single-ended interface shown in FIG. The diff interface will not be supported. It is possible to place both interfaces on the imager to support both types of companion chips, but that would increase the pin count and cost.

The longest solution is to selectively support either a single-ended interface or a differential interface with the same number of pins (without requiring twice as many pins as the differential interface). It will be possible to realize an interface that can. According to this, it is possible to provide the flexibility of supporting both a generally used single-ended image processing apparatus and a new image processing apparatus having a low-noise differential interface.

The use of fewer digital data interface pins should minimize power, IC costs, package costs, and PC board size.

[0013]

However, the data rate per pin is inversely proportional to the number of pins. Higher data rates cause higher noise, such as electromagnetic interference and chip output ground bounce. Also, if the number of digital data interface pins is less than the word size of the data, some form of synchronization is often required, which adds to the complexity and cost of the system.

As one of the verified imager devices,
Some have a 4-bit single-ended pixel data interface. Since the data word size is 12 bits, the data of each pixel is transferred four bits at a time, divided into three clocks. Since multiple clock cycles are required to transfer individual pixel data, whether a 4-bit transfer is the first 4 bits, the middle 4 bits, or the last 4 bits of pixel data, A synchronization code is needed so that it can be determined.
Such a synchronization process makes the system more complex and increases the cost of the system.

[0015] As imagers have higher resolutions, the number of pixels per frame will be significantly higher. In order to keep the data rate per pin at a reasonable speed, the interface has been extended to the width of 10-bit pixel data. However, the data rate is still high, so signal conversion times will be short and ground bounce will occur. All of these can introduce noise into the silicon substrate of the imager and increase noise in the image.

Although a differential interface may be used, this usually results in doubling the number of pins. This is because two pins are used for each bit transfer. One for the "true" value (normal value) and the other for the "complementary" value. The present invention has been made in view of the above problems, and has as its object to provide an improved interface circuit that enables both single-ended output and differential output and uses only a minimum number of pins.

[0017]

In order to achieve the above object, the present invention provides a first single-ended interface connected to a first signal output line and a second single-ended interface connected to a second signal output line. A data interface circuit comprising: a second single-ended interface; and a differential interface having a normal signal output connected to the first output line and a complementary signal output connected to the second signal output line,
The output of the data interface circuit is selectable between a single-ended interface output and a differential interface output.

As a result, it is possible to realize an interface circuit improved by enabling both single-ended output and differential output, and using only a minimum number of pins.

[0019]

DETAILED DESCRIPTION OF THE INVENTION The following description is provided to enable any person skilled in the art to make and use the present invention. What is considered to be disclosed. However, it will be readily apparent to those skilled in the art that various modifications can be made. It discloses the basic principle of the present invention, and in particular, provides an interface circuit that realizes signal output from a CMOS image sensor to an external digital signal processing device in a single-ended or differential selectable manner. This is because.

The present invention is a data interface that can be either a single-ended interface or a differential interface. Here, a preferred embodiment of the present invention will be described with reference to FIG. Circuit 10 of FIG.
“0” is selectable between single-ended output and differential output. E if single-ended output is desired
If the NSE signal is enabled and differential output is desired,
The DF signal is allowed. Since only one mode can be selected at a time, it can be said that the ENSE and ENDF signals are complementary. Therefore, a single register bit may be used to represent the selected output type. The interface is easiest when the single-ended data interface width is equal to the pixel word width.
In the preferred embodiment, the data width is 10 bits, so 10 pins are used. FIG.
Although the operation for one pin is illustrated, it will be obvious to one skilled in the art how to duplicate the required circuitry to produce the desired number of output pins. All data bits are transferred on one edge of the clock (eg, the rising edge of the clock).

In the case of single-ended operation, the internal digitized signals ID0 and ID1 are supplied to the flip-flop 10
Timed by 4, 105, single-ended output drivers 106, 107 drive the output signal lines. Thus, the single-ended outputs D0 and D1 are provided to a companion chip or other off-chip electrical circuit.
Since the difference electric circuit 108 is not permitted, it does not interfere with the single-ended operation.

However, when a difference output is requested, the difference electric circuit 108 is permitted and the single-ended electric circuits 106 and 107 are not permitted. In difference mode,
Half of the bits are transferred on one edge of the clock and the other half of the bits are transferred on the other edge of the clock. The clocking scheme uses the same number of pins as a single-ended interface. Thus, if the relationship between the clock edge and the data transfer is always constant, no explicit synchronization is necessary. The internal digitized signals IDO and ID1 are
Timed by flip-flops 101, 102 and multiplexer 103, so that one signal is selected on the rising edge of the clock and another on the falling edge. The output from the multiplexer 103 is provided to a differential interface circuit, and generates a signal of a normal output and a complementary output. Thus, half of the clock cycles produce half of the bits in differential form, and the other half of the clock cycle produces the remaining bits. As described above, the generation of the differential output does not require twice as many pins and does not require a complicated bit synchronization method that causes a delay in data transfer.

All prior art CMOS imagers used a single-ended interface. If you allow the use of a single-ended interface, you can interface with many existing external devices. If the use of the differential interface is allowed, the noise can be reduced and the power interface can be reduced. A single-ended and differential signal interface would not increase the number of pins required compared to a single-ended-only interface. If the data transfer width is set to the word width, the timing relationship between the clock edge and the data transfer can be constant regardless of the single-end mode or the difference mode. If the timing relationship can be fixed, the need for explicit synchronization processing is eliminated, and the cost for that is eliminated.
The present invention may be used in place of the differential only interface shown in FIG. 4 in order to increase the flexibility of the interface.

As described above, the interface circuit in the present embodiment is a data interface for a CMOS imager that can be either a single-ended interface or a differential interface. As a single-ended interface, it is compatible with many existing external devices. Further, by realizing the differential interface, it is possible to reduce noise and power consumption in an interface with an external device that supports a differential signal. For single-ended and differential signal integrated interfaces, the number of pins is no more than the number of pins required for a single-ended-only interface.
The data transfer width is set to a word width, so that the time relationship between the clock edge and the data transfer can be fixed in both the single-ended mode and the differential mode. In single-ended mode, data is transferred once per clock, while in differential mode, data is transferred twice per clock at each edge of the clock. Since the time relationship is fixed, there is no need to explicitly synchronize the bits, and no cost is required.

It will be apparent to those skilled in the art that various modifications and variations can be made to the preferred embodiment described above without departing from the scope and spirit of the invention. Thus, it is apparent that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

[0026]

As is apparent from the above description, the present invention provides a first single-ended interface connected to a first signal output line and a second single-ended interface connected to a second signal output line. A data interface circuit comprising: an end interface; and a differential interface having a normal signal output connected to a first output line and a complementary signal output connected to a second signal output line. Output is selectable between a single-ended interface output and a differential interface output, so that both single-ended output and differential output are possible and only a minimum number of pins are used. An improved interface circuit can be realized.

In the above interface circuit according to the present invention, when the single-ended output is selected, one signal output line is used for each clock cycle.
If bits are transferred and the differential output is selected, half of all output bits are transferred on a first edge of the clock and the other half of the output bits are transferred on a second edge of the clock. In other words, since the total number of pins used for output is the same for single-ended and differential output, both single-ended and differential interfaces can be realized with the required number of pins for single-ended.

Then, the above interface circuit is connected to a CM
If incorporated into an OS image sensor chip, a CMOS image sensor chip that can perform both single-ended output and differential output and uses only a minimum number of pins can be obtained. Further, in the interface circuit of the present invention, if the data transfer width is set to the word width of the output of the CMOS image sensor, the time relationship between the clock edge and the data transfer is fixed in both single-ended and differential outputs. This eliminates the need for explicit bit synchronization and eliminates the cost associated therewith.

Further, the present invention provides a first single-ended interface connected to a first signal output line, a second single-ended interface connected to a second signal output line, and a first output line. A differential interface having a normal signal output connected to the second signal output line and a complementary signal output connected to the second signal output line, wherein the output is selectable between a single-ended interface output and a differential interface output A CMOS image sensor having a circuit, and an image processor connected to the CMOS image sensor and receiving an output signal from the data interface circuit, thereby providing a single-ended output and a differential signal. Output, and use only a minimal number of pins. The CMOS imaging device not be realized.

The present invention further comprises forming an analog image signal using a plurality of CMOS image sensing pixels; converting the analog image signal to form a plurality of digital output signals; Transferring the output signal to the digital image processing device, via either a single-ended or differential interface circuit, depending on the selection, thereby providing a single-ended output and An image processing method that enables both differential output and uses a minimum number of pins can be realized.

[Brief description of the drawings]

FIG. 1 illustrates a typical single-ended interface embedded in CMOS.

FIG. 2 is a circuit diagram of the single-ended interface of FIG.

FIG. 3 is a circuit diagram of a differential interface circuit.

FIG. 4 is a diagram illustrating an example in which an imager is applied to the differential interface circuit of FIG. 3;

FIG. 5 is a circuit diagram according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 circuit 101, 102, 104, 105 flip-flop 103 multiplexer 106, 107 single-ended electric circuit 108 differential electric circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Ferry Gunawan United States of America 92707 Santa Ana Southflower Street 3810 Apartment G (72) Inventor Dino di Trotta United States of America 92627 Costa Mesa Santa Isabel 308 Unit A2

Claims (16)

[Claims] A first single-ended interface connected to the first signal output line; a second single-ended interface connected to the second signal output line; and a first single-ended interface connected to the first output line. A differential interface having a normal signal output and a complementary signal output connected to a second signal output line, wherein the output of the data interface circuit is a single-ended interface output and a differential interface output. A data interface circuit that can be selected from among the following. 2. When the single-ended output is selected, each signal output line outputs one signal every clock cycle.
The data interface circuit according to claim 1, wherein bits are transferred. 3. When the differential output is selected, half of all output bits are transferred on a first edge of a clock and the other half of the output bits are transferred and used on a second edge of the clock. The data interface circuit according to claim 2, wherein the total number of pins is the same as that of the single-ended interface. 4. The data interface circuit according to claim 3, wherein the data interface circuit is incorporated in a CMOS image sensor chip. 5. The data interface circuit according to claim 3, further comprising a plurality of sets of single-ended and differential interface circuits. 6. The data interface circuit according to claim 5, comprising five sets of single-ended and differential interface circuits for driving ten output lines. 7. The data interface circuit according to claim 5, wherein the data transfer width is set to a word width of an output of the CMOS image sensor. 8. A first single-ended interface connected to a first signal output line, a second single-ended interface connected to a second signal output line, and a first single-ended interface connected to the first output line. A CMOS image sensor comprising a data interface circuit having a normal signal output and a differential interface having a complementary signal output connected to a second signal output line, wherein the output of the data interface circuit is a single-ended interface output And an image processor connected to the CMOS image sensor and receiving an output signal from the data interface circuit. 9. When the single-ended output is selected, each signal output line outputs one signal every clock cycle.
9. The CMOS imaging device according to claim 8, wherein bits are transferred. 10. When the difference output is selected, half of all output bits are transferred on a first edge of a clock and the other half of the output bits are transferred and used on a second edge of the clock. The CMOS imaging device according to claim 8, wherein the total number of pins is the same as that of the single-ended interface. 11. The CMOS imaging apparatus according to claim 10, further comprising a plurality of sets of single-ended and differential interface circuits. 12. The CMOS imaging apparatus according to claim 11, further comprising five sets of single-ended and differential interface circuits for driving ten output lines. 13. The CMOS imaging apparatus according to claim 11, wherein a data transfer width is set to a word width of an output of said CMOS image sensor. 14. An image processing method, comprising: forming an analog image signal using a plurality of CMOS image sensing pixels; converting the analog image signal to form a plurality of digital output signals. And transferring the digital output signal to the digital image processing device via either a single-ended or differential interface circuit, as selected. 15. When single-ended output is selected, each signal output line outputs one signal every clock cycle.
The image processing method according to claim 14, wherein bits are transferred. 16. When differential output is selected, half of all output bits are transferred on the first edge of the clock and the other half of the output bits are transferred on the second edge of the clock and used. The image processing method according to claim 15, wherein the total number is the same as that of the single-ended interface.