JP2009065399A - Digital data transmitter, digital data receiver, digital data transmitting-receiving system, method for transmitting digital data, method for receiving digital data, method for transmitting-receiving digital data, and electronic information device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transmitting and receiving system that transmits digital image data, which can transmit image data serial signals with synchronous control serial signals including a synchronous code that indicates a position of the image data, control data related to the image data and a control code that indicates a position of the control data, through one signal path. <P>SOLUTION: The data transmitting and receiving system that transmits digital image data has a parallel-serial conversion circuit 15 which converts image data parallel signals to image data serial signals, a data conversion circuit 101 which outputs synchronous control serial signals included with the synchronous code, the control data and the control code, and a differential amplitude signal transmitter (a transmitter 118 and a transistor 112) which converts the image data serial signals to differential amplitude signals to transmit them. The differential amplitude signal transmitter changes the amplitude of the differential amplitude signals of the image data serial signals corresponding to values of the synchronous control serial signals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a digital data transmission device, a digital data reception device, a digital data transmission / reception system, a digital data transmission method, a digital data reception method, a digital data transmission / reception method, and an electronic information device, in particular, mounted on a mobile communication terminal, Digital data transmitting apparatus and digital data transmitting method for transmitting data between camera module (image capturing section) and display apparatus (image display section), digital data receiving apparatus and digital receiving method The present invention relates to a data reception method, a digital data transmission / reception system and a digital data transmission / reception method using the same, and an electronic information device equipped with the digital data transmission / reception system.

  In digital cameras and digital video cameras, conversion of an optical image into an electrical signal is generally realized by an image sensor (charge coupled device CCD or complementary metal oxide semiconductor CMOS). This image sensor is a plate having a pixel array (also called a detector matrix) in which small image elements (pixels) sensitive to light and color are regularly arranged. The resolution of this matrix varies depending on the physical size of the pixels and the degree of integration thereof. In general, an image sensor has hundreds of thousands of pixels.

  In the manufacture of such an image sensor, it is possible to integrate a signal processing unit, which is a digital electronic device, and an image sensor, which is an analog electronic device, on the same semiconductor element by using highly developed CMOS technology. . In addition, the camera module can be mounted on a smaller electronic device such as a portable computer or a portable mobile terminal device that integrates an image capturing unit and an image display unit by reducing its size and weight. It becomes possible.

  When the camera module is mounted on a portable computer or a portable mobile terminal device, many output lines for transmitting the image signal are required for the image signal output from the camera module. Such a large number of output lines is necessary because of the wiring problem such as wiring arrangement and routing for digital image signals and the need for an input / output unit for data transfer corresponding to the number of wirings. This causes a problem of unnecessary radiation noise such as transfer problems and data interference between wirings, which is a major issue in reducing the cost, reducing power consumption, and downsizing of the terminal device and the system using the terminal device. .

  As a method for solving this problem, Patent Document 1 and Patent Document 2 disclose that a digital image signal is converted into an LVDS (Low Voltage Differential Signal) serial transmission / reception device with a small number of signal lines and a logic circuit. A data transfer control device that is simple and can reduce power consumption and an electronic device using the data transfer control device are disclosed.

  FIG. 7 is a block diagram for explaining a data transfer system using the conventional data transfer control device disclosed in Patent Document 1. In FIG.

  Here, a case where a 12-bit parallel signal is converted into a serial signal and the serial signal is transferred as a differential signal will be described.

  A data transfer system 400 shown in FIG. 7 is an LCD that outputs various signals including control signals to a liquid crystal display (not shown) as a display device based on an image signal obtained by a camera unit (not shown). It has a controller 407 and a transmission side data transfer device 400a for transmitting a signal from the controller 407. In addition, the data transfer system 400 includes a receiving-side data transfer device 400b that receives various signals from the transmitting-side data transfer device 400a, and the display device based on the various signals received by the receiving-side data transfer device 400b. And an LCD driver 401 for driving the liquid crystal display. The data transfer system 400 includes a bus 404 that connects the transmission-side data transfer device 400a and the reception-side data transfer device 400b. The bus 404 includes data signal lines DT1 that transfer differential signals. DT1X, DT2, and DT2X, control signal lines CTL and CTLX, and clock signal lines CK and CKX.

  The transmission-side data transfer device 400a includes a parallel-serial conversion circuit 406 that converts various signals from the LCD controller into parallel-serial signals, and an LVDS driver group 405 that transmits serial signals output from the parallel-serial conversion circuit 406. It is configured. The receiving-side data transfer device 400b includes an LVDS receiver group 403 that receives a serial signal from the LVDS driver group 405, and a serial / parallel conversion circuit 402 that serial-parallel converts the serial signal received by the LVDS receiver group 403 and outputs the serial signal. It consists of and.

  The LCD controller 407 sends a clock signal LO_CLK, 8-bit image data R [8: 1], G [8: 1], B [8: 1], and 3 bits to the transmission-side data transfer device 400a. Control signal CTL [3: 1], and the 3-bit control signal CTL [3: 1] includes a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, and a data control signal DataEnable. . The LCD controller 407 generates a high-speed clock signal HI_CLK obtained by multiplying the clock signal LO_CLK by 12 times by a PLL (Phase Locked Loop) circuit (not shown) built in the LCD controller 407, and transmits the data signal 400a on the transmission side. To send to. Further, the LCD controller 407 sets the transfer instruction signal START for instructing the start or stop of the transfer of image data, the reset signal RESET for initializing the internal data of the transmission side data transfer device 400a, and the LVDS driver group 405 to the standby state. The standby signal STBY to be transmitted is transmitted to the transmission side data transfer device 400a.

  On the other hand, the reception-side data transfer device 400b receives various signals from the transmission-side data transfer device 400a, and sends the clock signal RX_CLK and 8-bit image data RO [8: 1], GO [ 8: 1] and BO [8: 1] and a 3-bit control signal CTLO [3: 1] are transmitted. The 3-bit control signal CTLO [3: 1] is perpendicular to the horizontal synchronization signal HSYNC. A synchronization signal VSYNC and a data control signal DataEnable are included. The receiving-side data transfer device 400b transmits a transfer instruction signal STARTO to the LCD driver 401.

  The LCD driver 401 transmits a standby signal STBY for setting the LVDS receiver group 403 to a standby state to the receiving side data transfer apparatus 400b.

  Here, the LVDS receiver group 403 includes four LVDS receivers 403a to 403d, and the non-inverted signal lines RX_DT1, RX_DT2, RX_CTL, RX_CK and the inverted signal lines RX_DT1X, RX_DT2X, RX_CTLX, RX_CKX are connected between the input terminals. Are connected to termination resistors Ra to Rd of approximately 100Ω each.

  Next, the operation will be described.

  First, the operation of the transmission side data transfer apparatus will be described.

  The image data R [8: 1], G [8: 1], B [8: 1] and the control signal CTL [3: 1] are transmitted from the LCD controller 407 to the transmission side data transfer device 400a and the clock signal LO_CLK is transmitted. The image data R [8: 1], G [8: 1], and B [8: 1] are respectively latched by the corresponding latch circuit (not shown) in the data transfer device 400a at the rising timing of The control signal CTL [3: 1] is processed by a corresponding signal processing circuit (not shown) in the data transfer device 400a.

  At the next rising timing of the clock signal LO_CLK, each pixel data latched in each latch circuit and the control signal processed by the signal processing circuit are transferred to corresponding shift registers (see FIG. (Not shown).

  Thereafter, based on the high-speed clock signal HI_CLK, the input image data R [8: 1] and G [8: 5] are output from one shift register as the serial image data signal D1 in a predetermined period. The serial image data signal DT1 is transferred by the LVDS driver 405a as a differential signal composed of the non-inverted signal DT1 and the inverted signal DT1X to the receiving side data transfer device 400b via the data signal line of the bus 404.

  Further, during the predetermined period, the shift register 125 receives the input image data G [4: 1] and B [8: 1] from one shift register based on the high-speed clock signal HI_CLK. Output as signal D2. The serial image data signal D2 is transferred by the LVDS driver 405b as a differential signal composed of the non-inverted signal DT2 and the inverted signal DT2X to the receiving side data transfer device 400b via the data signal line of the bus 404.

  Further, during the predetermined period, based on the high-speed clock signal HI_CLK, the control signal C processed by the signal processing circuit is output from the corresponding shift register as the serial control signal CT. The serial control signal CT is transferred by the LVDS driver 405c as a differential signal composed of the non-inverted signal CTL and the inverted signal CTLX to the receiving side data transfer device 400b via the bus 404.

  In the transmission-side data transfer device 400a, such data input from the LCD controller 407 and serial output of the input data are repeatedly performed.

  In the parallel-serial conversion circuit 406 of the transmission-side data transfer device 400a, the input high-speed clock signal HI_CLK is inverted by an internal inverter to generate a serial clock signal CLKSR, and the LVDS driver 405d inverts the non-inverted signal CK. The differential signal including the signal CKX is transmitted to the receiving side data transfer device 400a via the bus 404.

  Next, the operation of the receiving side data transfer apparatus will be described.

  As described above, the LVDS receiver group 403 includes four LVDS receivers 403a to 403d. The LVDS receiver 403a controlled by the internal standby signal RSTB is not inverted from the data signal lines DT1 and DT1X of the bus 404. The signal and the inverted signal are received, and the serial image data signal RDT 1 is output to the serial / parallel conversion circuit 402.

  The LVDS receiver 403b controlled by the internal standby signal RSTB receives the non-inverted signal and the inverted signal from the data signal lines DT2 and DT2X of the bus 404 and outputs the serial image data signal RDT2 to the serial / parallel conversion circuit 402. .

  Further, the LVDS receiver 403 c controlled by the standby signal STBY receives the non-inverted signal and the inverted signal from the control signal lines CTL and CTLX of the bus 404 and outputs the serial control signal RCTL to the serial / parallel conversion circuit 402.

  The LVDS receiver 403 d controlled by the standby signal STBY receives the non-inverted signal and the inverted signal from the clock signal lines CK and CKX of the bus 404 and outputs the serial clock signal RCLK to the serial / parallel conversion circuit 402.

  Then, the serial / parallel conversion circuit 402 performs signal processing (reverse signal processing) opposite to the signal processing in the transmission side data transfer device on the serial clock signal RCLK by an internal signal processing circuit (not shown). The clock signal RX_CLK is output.

  In the serial-parallel conversion circuit 402, a control code CTLO [12: 1] is generated by a shift register (not shown) that receives signals from the LVDS receivers 403c and 403d, and the control code CTLO [12: 1] And a control code decoding circuit (not shown) that receives the clock signal CLK as input, outputs a 3-bit control signal CTLO [3: 1] and a transfer instruction signal STARTO.

  Further, an internal standby signal RSTB is output from an OR gate (not shown) that receives the standby signal STBY and an inverted signal of the transfer instruction signal STARTO.

  The serial-parallel conversion circuit 402 sequentially outputs the upper 8 bits as image data RO [8: 1] based on the serial clock signal RCLK by a shift register (not shown) that receives the 12-bit serial image data signal RDT1. The lower 4 bits are sequentially output as image data GO [8: 5].

  The serial-parallel conversion circuit 402 sequentially outputs the upper 4 bits as image data GO [4: 1] based on the serial clock signal RCLK by a shift register that receives the 12-bit serial image data signal RDT2, and outputs the lower order. 8 bits are sequentially output as image data BO [8: 1].

  The values of the image data RO [8: 1], GO [8: 1], and BO [8: 1] are respectively latched by the corresponding three latch circuits (not shown) when the clock signal CLK rises. .

  As described above, the control signal synchronized with the image data is encrypted into the control code by the control code generation circuit configured by a simple logic circuit, and the control code is converted into a serial signal together with the image data, and the data signal line of the same bus Therefore, the circuit configuration is easier than in the prior art, and image data can be transferred without preparing a separate signal line. Further, since the idle code and the start code can be included in the control code, the same control signal line can be used to return from the standby state to the operating state and to transition from the operating state to the standby state. Further, in the standby state, the LVDS driver and the LVDS receiver of the data signal line are set in the standby state, which is effective in suppressing power consumption.

  However, in addition to the serial image signal line, an LVDS driver and LVDS receiver for the serial control signal line and their two signal lines are required, the number of signal lines is small, the logic circuit is simple, and the power consumption is kept small and small. Realization on a circuit scale is not optimal because further ingenuity is required.

  Next, it is a block diagram which shows the data transmission / reception circuit disclosed by patent document 2. FIG.

  As shown in FIG. 8, the digital data transmission / reception circuit 500 disclosed in Patent Document 2 includes a data transmission device 501 for transmitting data and a data reception device 511 for receiving transmitted data. By transmitting and receiving such data, the image signal output from the data transmission device 501 does not require many output lines as described above.

  That is, the data transmission device 501 receives the image data PS conversion circuit 508 that performs parallel-serial conversion on the image data, the voltage supply unit 503 that supplies the voltage Vin to the differential circuit 502, and the transmitted bit element. The input unit 504 includes output units 505 and 506 that transmit a non-inverted current signal and an inverted current signal, and an external current setting resistor 507.

  The data receiving device 511 also includes an input unit 513 that supplies the voltage Vin to the differential circuit 512, input units 514 and 515 that receive the non-inverted current signal and the inverted current signal, and bit elements from the received current signal. An output unit 516 for outputting, a resistor 517 for setting an external gain, and an image data SP conversion circuit 518 for serial-parallel conversion of serial data output from the output unit 516 are provided.

  In this case, the transmission of data is data of a sub-LVDS type current signal that operates at the supply voltage of the mobile communication terminal device (for example, 1.5 to 1.8 V when a typical LVDS supply voltage is approximately 3.0 V). It is executed by the transmission device 501 and the data reception device 511, but is not necessarily limited to this.

  The signal is transferred from the data transmission device 501 to the data reception device 511 via transmission lines 518 and 519 using the self-bias signal transmission method according to FIG. In this self-bias signal transmission method, a resistor 520 (for example, a resistance value of 100 ohms) is disposed between transmission lines 518 and 519.

  Waveform diagrams in the transmission lines 518 and 519 from the data transmission device 501 to the data reception device 511 are shown in FIG. This operating principle is not different from that of a normal LVDS circuit.

  As shown in FIG. 9, the current signal in the transmission lines 518 and 519 is interpreted as one bit when the voltage waveform of the transmission line 518 which is a non-inversion line is positive, and in this case, the transmission line which is an inversion line. The voltage waveform at 519 is negative. Similarly, the case of 0 bits is indicated by the opposite situation. The sub-LVDS type current signal transmitter / receiver pair can be used at a high data transfer rate while keeping electromagnetic noise to a minimum.

  Next, for example, image data of VGA size will be described as an example of image data output from the camera module to the image display device by the data transmission device 501.

  The VGA size image data has 640 pixels of data in one line and 480 lines of data in one frame. The data size of one pixel often has 8 bits to 14 bits depending on the number of bits for quantizing the signal of the image sensor into a digital value. According to the prior art, image data output from the camera module to the image display device needs to handle one frame in units of several lines. FIG. 9 shows an example of a serial transmission / reception data string as a method for identifying which frame the image data belongs to that line.

  In FIG. 9, the frame is fixed using a special synchronization code so that the start of the frame is indicated by a synchronization code FS (frame start) 601 and the end of the frame is indicated by a synchronization code FE (frame end) 602. ing. Within this frame, the image data and statistical data for each line have a synchronization code LS (line start end) 603 indicating the beginning of the record and a synchronization code LE (line end) 604 indicating the end of the record. ing. Here, the statistical data includes, for example, an integrated luminance value, and this is used for exposure control so that the screen becomes dark when the screen is too bright, or the screen becomes bright when the screen is too dark. .

  In this case, the frame start synchronization code FS601 is transmitted, followed by the first line image data 605 and the line end synchronization code LE604. Further, the image data 605 for the second line and the line end synchronization code LE604 follow the line start end synchronization code LS603. As described above, the image data 605 for the lines 1 to 480 are transmitted between the line start synchronization code LS603 indicating the start of each line and the line end synchronization code LE604 indicating the end of each line. Further, after transmission of the line end synchronization code LE 604 from the final image data 605 for the line 480, the line start end synchronization code LS603 is transmitted, and further the statistical data SD606 is transmitted. Next, after the transmission of the statistical data SD606, a frame end synchronization code FE602 indicating the end of the transmitted frame is transmitted.

  Since the statistical data amount of the statistical data SD606 can be made smaller or larger than the data amount in one image data line, the last line may be shortened or lengthened accordingly. There is. However, this is unlikely to cause problems. This is because the frame is determined using a special synchronization code that does not appear in the image data, as indicated by the synchronization code FS601 at the start of the frame and the synchronization code FE602 at the end of the frame. As a result, by assuming that image data of 480 data units separated by the synchronization code is included in one frame and statistical data SD606 is included in the 481st data unit, lines 1 to 480 are received on the receiving side. Each image data 605 and statistical data SD606 can be easily separated from a series of data. When it is known in advance that the statistical data SD606 does not exist, 480 data units of image data 605 can be separated on the receiving side.

  However, in the conventional LVDS (low voltage differential signal) serial transmission / reception method disclosed in Patent Document 2, the image signal output from the camera module is realized with less wiring, reducing unnecessary radiation noise, and reducing the system cost. Although the solution to the problem of low power consumption and miniaturization is effective, the image data 605 for each frame and line can be easily and reliably separated, and the image data 605 and the image data 605 are followed. In order to easily and reliably separate the statistical data SD606, a frame start synchronization code FS601 using a special synchronization code that does not appear in the image data 605, a frame end synchronization code FE602, and the start of each line in the frame Line start end synchronization code LS603 and line end synchronization code indicating the end of each line It is necessary to use the E604. As described above, it is necessary to insert a synchronization code before and after the image data 605 and statistical data SD606 for each line input to the input unit 504 of the data transmission device 501, and from the output unit 516 of the data reception device 511. Since it is necessary to detect the synchronization code existing before and after the output line image data 605 and the statistical data SD606 and to separate this synchronization code from other image data 605 and statistical data SD606, the data transmission device A synchronization code insertion circuit is required at the front stage of 501 and a synchronization code separation circuit is required at the rear stage of the data reception device 511, so that transmission / reception time can be increased and the transmission / reception timing control circuit can be reduced in circuit scale. This is not optimal because it requires further ingenuity.

  Patent Document 2 discloses a data transmission / reception apparatus that solves such a problem, and will be briefly described below with reference to FIG.

  FIG. 10 is a block diagram illustrating the data transmitting / receiving apparatus.

  As shown in FIG. 10, the data transmitting / receiving apparatus 10a includes a data transmitting apparatus 110 that transmits digital data and a data receiving apparatus 150 that receives the transmitted digital data. For example, a camera module and an image display apparatus are included. Digital data is sent to and received from

  The data transmitting / receiving apparatus 10a further includes a current / voltage conversion resistor 151 as a resistance means for converting a signal current output from the data transmitting apparatus 110 to the data receiving apparatus 150 into a signal voltage. The current / voltage conversion resistor 151 is provided outside the data transmission device 110 and is provided on the data reception device 150 side.

  The data transmission device 110 includes a parallel-serial conversion circuit 116 that performs parallel-serial conversion on the image data parallel signal 115, an LVDS (Low Voltage Differential Signal) transmitter 118 that transmits the parallel-serial conversion output as a differential amplitude signal, and an amplitude. It has an Nch transistor 112 as a switching means, a first constant current power supply 114, and a second constant current power supply 113. The LVDS transmitter 118, the Nch transistor 112, and the constant current power supplies 113 and 114 constitute a differential amplitude signal transmission means. The differential amplitude signal transmission means is a value of a synchronous code serial signal 111 indicating the position of image data. The image data serial signal 117 from the parallel-serial conversion circuit 116 is changed to a differential amplitude signal (output to both transmission lines) so that the amplitude of the differential voltage (voltage between transmission lines) of the differential amplitude signal is changed according to The signal value S of the synchronous code serial signal 111 and the signal value Y of the image data serial signal 117 can be transmitted simultaneously via both transmission lines. The Nch transistor 112 and constant current power supplies 113 and 114 constitute constant current control means, and this constant current control means is supplied to the LVDS transmitter 118 according to the value S of the synchronization code serial signal 111. Control constant current.

  Here, the parallel-serial conversion circuit 116 uses N-bit (N is a natural number) parallel image data (image data parallel signal) per pixel as image input data, and this N-bit (N is a natural number) image per pixel. The data parallel signal 115 is converted into serial image data (image data serial signal).

  The LVDS transmitter 118 converts the transmission-side image data serial signal 117 output from the parallel-serial conversion circuit 116 into a differential amplitude signal.

  In the Nch transistor 112, the transmission side synchronization code serial signal 111 which is a serial synchronization signal is input to the gate, the output terminal of the constant current power supply 113 is connected to the source line, and a constant current is supplied, and the drain line Are connected to the power supply voltage input terminal of the LVDS transmitter 118 and the output terminal of the constant current power supply 114. As a result, the Nch transistor 112 performs on / off control of the output of the constant current power supply 113 to the LVDS transmitter 118 in accordance with the transmission side synchronization code serial signal 111, and the constant current supplied by the constant current power supplies 113 and 114 is constant. Switching to a constant current by only the current power source 114 is performed.

  The constant current power supply 113 is connected between the output terminal 100 of the power supply voltage Vdd and the source line of the Nch transistor 112 so that a predetermined constant current can be supplied to the LVDS transmitter 118 via the Nch transistor 112.

  The constant current power supply 114 is connected in parallel to the series circuit of the constant current power supply 113 and the Nch transistor 112, and the constant current from the constant current power supply 114 or the constant current from the constant current power supplies 113 and 114 is sent to the LVDS transmitter 118. To supply.

  In addition, the data transmission device 110 includes a control data conversion circuit 101b that performs parallel-serial conversion on arbitrary control data of M bits (M is a natural number) related to image data.

  On the other hand, the data receiving apparatus 150 includes an LVDS (Low Voltage Differential Signal) receiver 152, a synchronization code conversion circuit 155 as a synchronization signal conversion means, and a serial-parallel conversion circuit 156 as a serial-parallel conversion means. ing.

  Further, the data receiving device 150 receives a control data serial signal from the control data conversion circuit 101b and converts it into arbitrary control data of M bits (M is a natural number) related to the image data. have.

  The LVDS receiver 152 is provided between the output terminal 100 of the power supply voltage Vdd and the ground voltage connection terminal, receives the current output from the LVDS transmitter 118 as a voltage, and receives the reception-side synchronous serial signal 153 and the image data. The serial signal 154 is separated and output. The LVDS receiver 152 changes the amplitude width of the differential voltage from the LVDS transmitter 118, thereby changing the signal values of the synchronous code serial signal 111 and the image data serial signal 117 simultaneously from the LVDS transmitter 118. The output signal current is received as a signal voltage through a resistor 151 that converts the signal current into a signal voltage.

  That is, the LVDS receiver 152 constitutes a differential amplitude signal receiving means. The differential amplitude signal receiving means changes the amplitude of the output differential voltage of the image data serial signal 117 according to the value S of the synchronous code serial signal 111. The changed differential amplitude signal is received, and the signal value S of the synchronization code serial signal 111 and the signal value Y of the image data serial signal 117 are separated.

  The synchronization code conversion circuit 155 converts the reception-side synchronization code serial signal 153 output from the LVDS receiver 152 into a synchronization signal 157. That is, a unique code string (bit string) of the sync code serial signal 153 constitutes a sync code FS indicating the start end of one frame of image data, a sync code FE indicating the end of the one frame, and a part of the one frame. Each of the four types of synchronization code LS indicating the start end of one line and synchronization code LE indicating the end of the one line is converted into a synchronization signal 157 indicating the position of the image data.

  The serial-parallel conversion circuit 156 converts the image data serial signal 154 output from the LVDS receiver 152 into a parallel signal 158 of N bits (N is a natural number) per pixel.

  This principle of operation is not different from the case of normal LVDS transmission / reception. That is, in the LVDS receiver 152, the current signal is interpreted as “1” or “0” depending on the direction of flowing through the resistor 151. The LVDS transmitter 118 and LVDS receiver 152 pair can be used at high data rates while keeping electromagnetic noise to a minimum.

In such a data transmission / reception device, in particular, in LVDS data transmission / reception between the camera module and the electronic information device, the multiplexing processing of the image data and the synchronization code and the separation processing thereof do not increase the amount of serial transmission data, The position of the image data such as the start and end of one frame and the start and end of one line of image data, and the start and end of one pixel data can be recognized easily and accurately. The transmission / reception timing control circuit can be realized on a small circuit scale.
JP 2007-34885 A JP 2006-24972 A

  However, in the conventional data transmitting / receiving apparatus shown in FIG. 10, an arbitrary control code is transmitted by the conversion circuit 101b on the transmission side and the conversion circuit 160a on the reception side. A transmission path different from the transmission path for transmitting data and the synchronization code is required, and it is necessary to provide a conversion circuit in both the data transmission apparatus and the data reception apparatus.

  The present invention has been made to solve the above problems. On the image data serial signal transmission side, a synchronization code indicating the position of image data, a control signal (control data) related to the image data, and the like. Multiplexing processing can be performed, and on the receiving side of the image data serial signal, the multiplexed synchronization code and control signal can be separated and the transmission / reception timing control circuit can be realized with a small circuit scale Data transmitting apparatus, data transmitting method, data receiving apparatus, data receiving method, data transmitting / receiving system using the data transmitting apparatus and data receiving apparatus, data transmitting / receiving method, and electronic information device using the data transmitting / receiving apparatus The purpose is to obtain.

  A digital data transmission apparatus according to the present invention is a digital data transmission apparatus for transmitting digital image data, and converts an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal. A parallel-serial conversion circuit, a synchronization code indicating the position of the image data, M-bit (M is a natural number) control data related to the image data, and a control code indicating the position of the control data; A data conversion circuit that outputs a synchronization code, the control data, and a synchronization control serial signal including the control code, and a differential amplitude signal transmission unit that converts the image data serial signal into a differential amplitude signal and transmits the differential signal. The differential amplitude signal transmission unit converts the amplitude of the differential amplitude signal of the image data serial signal into the synchronous control serial signal. Is intended to vary in accordance with the value, the object is achieved.

  According to the present invention, in the digital data transmission device, the differential amplitude signal transmission unit includes a pair of signal output lines, and a resistor connected between the pair of signal output lines is connected to the image data serial signal. A differential transmitter for supplying a current signal to the pair of signal output lines and a power source and the differential transmitter are connected to each other so that a corresponding differential voltage is generated. A first constant current source that supplies one driving current; a second constant current source that is connected between a power source and the differential transmitter and supplies a second driving current to the differential transmitter; An Nch transistor connected between the second constant current source and the differential amplifier, and using the synchronization control serial signal as a gate input of the Nch transistor, the Nch transistor according to the value of the synchronization control serial signal The synchronous control serial signal is connected to the transistor. It is preferable to on-off control so that the transmitted data serial signal at the same time.

  According to the present invention, in the digital data transmitting apparatus, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, a second synchronization code indicating the end of the one frame, A third synchronization code indicating the start of one line in the one frame, and a fourth synchronization code indicating the end of one line in the one frame, and any control data in the one frame A first control code indicating a start end; arbitrary control data following the first control code; and a second control code indicating an end of the arbitrary control data; the first to third synchronization codes Is composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are preferably composed of a data string of M bits (M is a natural number).

  According to the present invention, in the digital data transmitting apparatus, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame and a second synchronization code indicating the end of the one frame. And a first control code indicating the start of any control data in the one frame, any control data following the first control code, and a second indicating the end of the any control data The first and second synchronization codes are composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are M bits (M Is preferably a natural number) data string.

  According to the present invention, in the digital data transmitting apparatus, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, and any control data in the one frame A first control code indicating a start end, arbitrary control data following the first control code, and a second control code indicating an end of the arbitrary control data, the first synchronization code being N It is preferable that the data string is composed of bits (N is a natural number), and the first and second control codes and the control data are composed of a data string of M bits (M is a natural number).

  According to the present invention, in the digital data transmitting apparatus, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data and a sixth synchronization code indicating the end of the one pixel data. And a first control code indicating the start of any control data in one frame, any control data following the first control code, and a first control code indicating the end of the control data The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number), and the first, second control codes, and control data are M bits ( It is preferable that M is a natural number) data string.

  According to the present invention, in the digital data transmitting apparatus, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data, and any control data in one frame A first control code indicating a start end; arbitrary control data following the first control code; and a second control code indicating an end of the arbitrary control data. The fifth synchronization code is N It is preferable that the data string is composed of bits (N is a natural number), and the first and second control codes and the control data are composed of a data string of M bits (M is a natural number).

  The digital data receiving apparatus according to the present invention changes the amplitude of a differential amplitude signal of an image data serial signal representing image data of N bits (N is a natural number) per pixel in accordance with the value of the synchronous control serial signal. A digital data receiving device for receiving the obtained differential amplitude signal as digital image data, the differential amplitude signal receiving the differential amplitude signal and outputting the image data serial signal and the synchronization control serial signal A receiving unit, a serial-parallel conversion circuit that converts the image data serial signal into an image data parallel signal representing the image data, and a data string that receives the synchronization control serial signal and constitutes the synchronization control serial signal; A synchronization code conversion circuit for converting the image data into a synchronization code indicating the position of the image data in comparison with various determined data sequences; A control serial signal is received, and a data sequence constituting the synchronous control serial signal is compared with various determined data sequences to indicate the position of control data of M bits (M is a natural number) related to the image data. And a control data code conversion circuit for converting the control data into the control data based on the control code, thereby achieving the above object.

  In the digital data receiving apparatus according to the present invention, the differential amplitude signal receiving unit includes a pair of signal input lines, and the amplitude information of the differential voltage is supplied to a resistor connected between the pair of signal input lines. It is preferable to provide a differential receiver that converts and outputs the synchronous control serial signal and converts the polarity information of the differential voltage into the image data serial signal.

  According to the present invention, in the digital data receiving apparatus, the data sequence constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, a second synchronization code indicating the end of the one frame, A third synchronization code indicating the start of one line in the one frame, and a fourth synchronization code indicating the end of one line in the one frame, and any control data in the one frame A first control code indicating a start end, arbitrary control data following the first control code, and a second control code indicating the end of the arbitrary control data, the first to third synchronizations The code is preferably composed of a data string of N bits (N is a natural number), and the first and second control codes and the control data are preferably composed of a data string of M bits (M is a natural number).

  According to the present invention, in the digital data receiving apparatus, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame and a second synchronization code indicating the end of the one frame. And a first control code indicating the start of any control data in the one frame, any control data following the first control code, and a second indicating the end of the any control data The first and second synchronization codes are composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are M bits (M Is preferably a natural number) data string.

  According to the present invention, in the digital data receiving apparatus, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, and any control data in the one frame It includes a control code indicating a start end, arbitrary control data following the control code, and a second control code indicating the end of the arbitrary control data, and the first synchronization code is N bits (N is a natural number) It is preferable that the first and second control codes and the control data are composed of a data string of M bits (M is a natural number).

  According to the present invention, in the digital data receiving apparatus, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data and a sixth synchronization code indicating the end of the one pixel data. And a first control code indicating the start of any control data in one frame, any control data following the first control code, and a first control code indicating the end of the control data The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number), and the first, second control codes, and control data are M bits ( It is preferable that M is a natural number) data string.

  According to the present invention, in the digital data receiving apparatus, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data, and includes any control data in one frame. A first control code indicating a start end; arbitrary control data following the first control code; and a second control code indicating an end of the arbitrary control data. The fifth synchronization code is N It is preferable that the data string is composed of bits (N is a natural number), and the first and second control codes and the control data are composed of a data string of M bits (M is a natural number).

  A data transmission / reception system according to the present invention is a digital data transmission / reception system including a digital data transmission device that transmits digital image data and a digital data reception device that receives the transmitted digital image data. The transmission apparatus includes a parallel-serial conversion circuit that converts an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal, a synchronization code indicating a position of the image data, and the M-bit (M is a natural number) control data related to image data and a control code indicating the position of the control data are input, and the synchronization code, the control data, and a synchronous control serial signal including the control code are output. And a data conversion circuit for converting the image data serial signal into a differential amplitude signal A differential amplitude signal transmission unit that converts and transmits the differential amplitude signal transmission unit, and changes the amplitude of the differential amplitude signal of the image data serial signal according to the value of the synchronization control serial signal The digital data receiving device receives the differential amplitude signal and outputs the image data serial signal and the synchronization control serial signal; and the image data serial signal A parallel-serial conversion circuit for converting the image data into an image data parallel signal representing the image data; and receiving the synchronization control serial signal, and comparing the data sequence constituting the synchronization control serial signal with various predetermined data sequences A synchronization code converting circuit for converting the image data into a synchronization code indicating the position of the image data, and receiving the synchronization control serial signal, and a data string constituting the synchronization control serial signal Control data code conversion circuit for converting to control data based on a control code indicating the position of control data of M bits (M is a natural number) related to the image data compared with various determined data strings Thus, the above-described object is achieved.

  In the data transmission / reception system according to the present invention, the differential amplitude signal transmission unit has a pair of signal output lines, and a resistor connected between the pair of signal output lines corresponds to the image data serial signal. A differential transmitter for supplying a current signal to the pair of signal output lines, and a power source and the differential transmitter so that a differential voltage is generated. A first constant current source for supplying a driving current of the second constant current source; a second constant current source connected between the power source and the differential transmitter for supplying a second driving current to the differential transmitter; An Nch transistor connected between the second constant current source and the differential amplifier, and using the synchronization control serial signal as a gate input of the Nch transistor, the Nch transistor according to the value of the synchronization control serial signal The synchronous control serial signal is the image data. The differential amplitude signal receiver has a pair of signal input lines, and a differential voltage is applied to a resistor connected between the pair of signal input lines. It is preferable to provide a differential receiver that converts the amplitude information of the differential voltage into the synchronous control serial signal and outputs the same, and converts the polarity information of the differential voltage into the image data serial signal and outputs the same.

  In the data transmission / reception system, the data sequence constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, a second synchronization code indicating the end of the one frame, A third synchronization code indicating the start of one line in one frame and a fourth synchronization code indicating the end of one line in the one frame, and the start of any control data in the one frame Including the first control code indicating the first control code, the arbitrary control data following the first control code, and the second control code indicating the end of the arbitrary control data, the first to third synchronization codes Is composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are preferably composed of a data string of M bits (M is a natural number).

  According to the present invention, in the data transmission / reception system, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame and a second synchronization code indicating the end of the one frame. And a first control code indicating the start of any control data in the one frame, any control data following the control code, and a second control code indicating the end of the control data The first and second synchronization codes are composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are M bits (M is a natural number). It is preferable that it is composed of data strings.

  According to the present invention, in the data transmission / reception system, the data string constituting the synchronization control serial signal includes a first synchronization code indicating the start of one frame, and the start of any control data in the one frame A first control code indicating the first control code, arbitrary control data following the first control code, and a second control code indicating the end of the arbitrary control data, and the first synchronization code includes N bits Preferably, (N is a natural number) data sequence, and the first and second control codes and control data are configured from an M-bit data sequence (M is a natural number).

  According to the present invention, in the data transmission / reception system, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data, and a sixth synchronization code indicating the end of the one pixel data. And a first control code indicating the start of any control data in one frame, any control data following the first control code, and a second indicating the end of the any control data The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number), and the first, second control codes, and control data are M bits (M Is preferably a natural number) data string.

  According to the present invention, in the data transmission / reception system, the data string constituting the synchronization control serial signal includes a fifth synchronization code indicating the start of one pixel data, and the start of any control data in one frame , A second control code indicating the end of the arbitrary control data, and the fifth synchronization code includes N bits. Preferably, (N is a natural number) data sequence, and the first and second control codes and control data are configured from an M-bit data sequence (M is a natural number).

  The data transmission method according to the present invention is a digital data transmission method for transmitting digital image data, and converts an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal. A parallel-serial conversion step, a synchronization code indicating the position of the image data, M-bit (M is a natural number) control data related to the image data, and a control code indicating the position of the control data are input. A data conversion step of outputting a code, the control data, and a synchronous control serial signal including the control code; and a differential amplitude signal transmission step of converting the image data serial signal into a differential amplitude signal and transmitting the differential amplitude signal. The differential amplitude signal transmission step converts the amplitude of the differential amplitude signal of the image data serial signal into the synchronization control sequence. Is intended to vary according to the value of the Al signal, the object is achieved.

  According to the digital data receiving method of the present invention, the amplitude of the differential amplitude signal of the image data serial signal representing the image data of N bits (N is a positive natural number) per pixel is determined according to the value of the synchronous control serial signal. A digital data receiving method for receiving a differential amplitude signal obtained by changing as a digital image data, wherein the differential amplitude signal is received and the image data serial signal and the synchronization control serial signal are output. A dynamic amplitude signal receiving step, a serial-parallel conversion step for converting the image data serial signal into an image data parallel signal representing the image data, and data constituting the synchronization control serial signal upon receiving the synchronization control serial signal Synchronous code conversion for converting a sequence into a synchronization code indicating the position of the image data by comparing with various predetermined data sequences And M bits related to the image data (M is a positive natural number) by comparing the data sequence constituting the synchronization control serial signal with various determined data sequences. And a control data code conversion step for converting the control data into the control data based on the control code indicating the position of the control data, thereby achieving the above object.

  A data transmission / reception method according to the present invention is a data transmission / reception method including a data transmission step of transmitting digital image data and a data reception step of receiving the transmitted digital image data. The data transmission step includes: A parallel-serial conversion step for converting an image data parallel signal representing image data of N bits (N is a positive natural number) per pixel into an image data serial signal, a synchronization code indicating the position of the image data, and related to the image data Data conversion step of inputting M-bit (M is a natural number) control data and a control code indicating the position of the control data as inputs, and outputting the synchronization code, the control data, and a synchronous control serial signal including the control code And a differential amplitude signal for converting the image data serial signal into a differential amplitude signal and transmitting it The differential amplitude signal transmission step changes the amplitude of the differential amplitude signal of the image data serial signal in accordance with the value of the synchronization control serial signal, and the data reception step A differential amplitude signal receiving step for receiving the differential amplitude signal and outputting the image data serial signal and the synchronization control serial signal; and an image data parallel signal representing the image data. A serial-to-parallel conversion step for converting to a synchronization code, and a synchronization code indicating the position of the image data by receiving the synchronization control serial signal and comparing the data sequence constituting the synchronization control serial signal with various determined data sequences Receiving the synchronization control serial signal and the data sequence constituting the synchronization control serial signal in various ways. A control data code conversion step for converting the control data into control data based on a control code indicating the position of control data of M bits (M is a positive natural number) related to the image data, In this way, the above object can be achieved.

  An electronic information device according to the present invention is equipped with the data transmission / reception system according to the present invention, thereby achieving the above object.

  The operation of the present invention will be described below.

  In the present invention, a differential amplitude signal transmission unit that converts an image data serial signal into a differential amplitude signal and transmits the differential amplitude signal is transmitted. Is changed according to the value of the synchronous control serial signal, so that the position of the image data can be recognized easily and accurately without increasing the amount of serial transmission data, and the transmission / reception timing control circuit can increase the speed of data transmission / reception. The small circuit scale can be realized.

  Furthermore, since the image data serial signal and the synchronization control serial signal are transmitted / received while changing the amplitude width of the LVDS transmission / reception differential voltage, the start and end of one frame and 1 can be easily transmitted without increasing the amount of serial transmission data. The start and end of line image data and the start and end of one pixel can be recognized, and the start and end of arbitrary control data can be recognized.

  Therefore, the multiplexing process and separation process of image data, synchronization code and synchronization signal, and the multiplexing process and separation process of image data and arbitrary control data and control synchronization signal can be realized with a small circuit scale.

  As described above, according to the present invention, the transmission side of the image data serial signal can perform the multiplexing process of the synchronization code indicating the position of the image data and the control signal (control data) related to the image data, On the receiving side of the image data serial signal, the multiplexed synchronization code and control signal can be separated.

Hereinafter, embodiments of the present invention will be described.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a data transmission / reception system according to Embodiment 1 of the present invention.

  A data transmission / reception system 10 shown in FIG. 1 is mounted on an electronic information device such as a camera-equipped mobile phone, and various signals including a control signal based on an image signal obtained by a camera unit (not shown). The transmission data signal processing unit 16 that outputs the signal and the transmission-side data transfer device 20a that transmits various signals from the transmission data signal processing unit 16 are provided. The data transfer system 10 includes a reception-side data transfer device 20b that receives various signals from the transmission-side data transfer device 20a, and a reception signal processing unit 11 that processes various signals received by the reception-side data transfer device 20b. have. The data transmission / reception system 10 has a transmission line 20c that connects the transmission-side data transfer apparatus 20a and the reception-side data transfer apparatus 20b, and the transmission line 20c is a data signal line that transfers a differential signal. DT and DTX, and clock signal lines CK and CKX for transferring differential signals.

  The transmission-side data transfer device 20a includes a parallel-serial conversion circuit 15 that performs parallel-serial conversion on various signals from the controller, and an LVDS driver group 14 that transmits serial signals output from the parallel-serial conversion circuit 15. ing. The reception-side data transfer device 20b includes an LVDS receiver group 13 that receives serial signals from the LVDS driver group 14, and a serial / parallel conversion circuit 12 that serial-parallel converts the serial signals received by the LVDS receiver group 13 and outputs the serial signals. It consists of and.

  The transmission data signal processing unit 16 sends the transmission clock TXCLK, 8-bit image line data (that is, luminance data Y [8: 1] and color difference data UV [8: 1]) to the transmission-side data transfer device 20a. ), Arbitrary control data CODE [7: 1], various synchronization codes (for example, codes FS, FE, LS, LE), and various control codes CS and CE indicating the position of the control data. is there.

  On the other hand, the reception-side data transfer device 20b receives various signals from the transmission-side data transfer device 20a and sends to the reception signal processing unit 11 a reception clock RXCLK and 8-bit image data (that is, luminance data Y [ 8: 1], color difference data UV [8: 1]), arbitrary control data CODE [7: 1], and various synchronization codes (for example, codes FS, FE, LS, LE).

  Here, the LVDS driver group 14 includes an LVDS driver 14 a that transmits an image data serial signal from the parallel-serial conversion circuit 15 and an LVDS driver 14 b that transmits a transmission clock from the parallel-serial conversion circuit 15. The LVDS receiver group 13 includes an LVDS receiver 13a that receives an image data serial signal from the LVDS driver 14a and an LVDS receiver 13b that receives a transmission clock from the LVDS driver 14b.

  The LVDS driver 14a and the LVDS receiver 13a are connected by a pair of signal lines for transmitting an image data serial signal as a current signal, that is, a non-inverted data signal line DT and an inverted data signal line DTX. The signal line is connected by a resistor R1 provided on the LVDS receiver 13a side. The LVDS driver 14b and the LVDS receiver 13b are connected by a pair of signal lines for transmitting a clock signal as a current signal, that is, a non-inverted data signal line CK and an inverted data signal line CKX. The signal lines are connected by a resistor R2 provided on the LVDS receiver 13b side.

  FIG. 2 is a diagram for explaining a data transmission / reception apparatus used in the data transmission / reception system shown in FIG. 1. The detailed configuration of the LVDS driver 14a and the circuit configuration on the input side, and the detailed configuration of the LVDS receiver 14b and the output thereof are shown. The circuit configuration of the side is shown.

  A data transmitting / receiving apparatus 1 shown in FIG. 2 converts a multi-bit parallel image data into serial data and transmits the serial data, and receives serial data transmitted from the data transmitting apparatus 100a and converts it into parallel data. And a data receiving device 150a for outputting.

  Here, the data transmission device 110a constitutes a part of the LVDS driver 14a and the preceding parallel-serial conversion circuit 15, and the data reception device 150a includes the LVDS receiver 14b and the subsequent-stage serial / parallel conversion circuit. 12 constitutes a part.

  Here, the image data parallel signal is N bits per pixel (N is a natural number), the synchronization code indicating the position of the image data is L bits (L is a natural number), and control data related to the image data and its data The control code indicating the position is M bits (M is a natural number).

  More specifically, the data transmitting apparatus 1 includes a parallel-serial conversion circuit (image data P) that converts a transmission side image data parallel signal 115 of N bits (N is a positive natural number) per pixel into an image data serial signal 117. -S conversion circuit) 116 and an LVDS transmitter 118 that converts the transmission-side image data serial signal 117 output from the parallel-serial conversion circuit 116 into a differential amplitude signal.

  The data transmitting apparatus 1 receives an L-bit synchronization code, an M-bit control code, and arbitrary control data, and converts these codes and data into a synchronization control serial signal 111 for output. A control code / arbitrary control data conversion circuit (hereinafter referred to as a control data conversion circuit) 101 and an Nch transistor 112 having a synchronous control serial signal 111 as a gate input are included.

  A first constant current power supply 113 is connected between the source of the Nch transistor 112 and the power supply Vdd, and a second constant current power supply 114 is connected in parallel to the Nch transistor 112 and the constant current power supply 113. The drain line of the Nch transistor 112 and the constant current power supply 114 are connected to the LVDS transmitter 118, and the LVDS transmitter 118 is supplied with a constant current from the two constant current power supplies. In FIG. 1, by the LVDS driver 14a, the LVDS transmitter 118, first and second constant current power supplies for supplying a constant current to the LVDS transmitter 118, and Nch connected to the LVDS transmitter 118. 1 schematically shows a circuit configuration including a transistor 112.

  The LVDS transmitter 118 has a pair of output lines for outputting a current signal, and a resistor 151 for changing the current signal to a voltage signal is connected between the pair of lines. The resistor 151 is provided outside the data transmission device 110a.

  Here, since the output signal 111 of the control data PS conversion circuit 101 is inputted to the gate of the Nch transistor 112, the current supplied to the LVDS transmitter 118 is as follows. Change.

  For example, when the value S of the output signal 111 is “1”, the Nch transistor 112 is turned on, and the LVDS transmitter 118 receives the constant current Id1 and the constant current Id1 from the first and second constant current power supplies 114 and 113, respectively. The power supply current supplied to Id2 and supplied to the LVDS transmitter 118 is Id1 + Id2. When the value S of the output signal 111 is “0”, the Nch transistor 112 is turned off, and the LVDS transmitter 118 is supplied with the constant current Id1 only from the first constant current power supply 114, and the LVDS The power supply current supplied to the transmitter 118 is Id1. At this time, the direction of the current output from the LVDS transmitter 118 is switched depending on whether the value Y of the image data serial signal input to the LVDS transmitter 118 is “0” or “1”.

  Here, the image data input to the image data PS conversion circuit 115 is 8-bit image line data (that is, luminance data Y [8: 1] and color difference data UV [8: 1] shown in FIG. )), And the synchronization codes input to the control data conversion circuit 101 are the synchronization codes FS, FE, LS, and LE shown in FIG. 1, and any control data input to the control data conversion circuit 101 is shown in FIG. 1 is arbitrary control data CODE [7: 1] shown in FIG. 1, and control codes input to the control data conversion circuit 101 are control codes CS and CE shown in FIG.

  On the other hand, the data receiving device 150a includes an LVDS receiver 152 that receives a current signal output from the LVDS transmitter 118 as a voltage signal generated across the resistor, and the LVDS receiver 152 includes a power supply voltage. Vdd is supplied from the power supply line 100b. The data receiving device 150a converts the image data serial signal 154, which is the value of the serial signal output from the LVDS receiver 152, into a parallel signal 158 of N bits (N is a natural number) per pixel. have. Further, the data receiving device 150 a includes a synchronization code conversion circuit 155 that converts the amplitude information (S) 153 of the serial output signal from the LVDS receiver 152 into the reception-side synchronization code serial signal 157, and the amplitude information of the serial output signal. (S) 153 includes a control data signal conversion circuit 160 that converts the control code 153 into an M-bit parallel data string 159 including the control code and arbitrary control data.

  The synchronization code conversion circuit unit 155 has a table including a bit string representing each synchronization code, compares the bit string included in the table with the input bit string, and compares the bit string included in the table with the L bit corresponding to the matched bit string. A bit synchronization code is output.

  The control data signal conversion circuit 160 has a table including a bit string representing each control code. The control data signal conversion circuit 160 compares the bit string included in the table with the input bit string and corresponds to the matched bit string. Each control code of M bits is detected, and arbitrary control data (M bit data) located between these control codes is output.

  FIG. 1 schematically shows a circuit configuration including the LVDS receiver 152 and the power source Vdd of the LVDS receiver 152 by the LVDS receiver 13a.

  Here, the operating principles of the LVDS transmitter and LVDS receiver are not different from those of normal LVDS transmission / reception. The current signal is interpreted as “1” or “0” depending on the direction of flow through the resistor 151. The pair of LVDS transmitter 118 and LVDS receiver 152 can be used at a high data transfer rate while keeping electromagnetic noise to a minimum.

  Next, the operation will be described.

  Here, description will be made using image data of VGA size as an example of image data output from the camera module.

  VGA size image data has 640 pixels of data in one line and 480 lines of data in one frame. The data size of one pixel often has 8 bits to 14 bits or the like depending on the number of bits for quantizing the signal of the image sensor into a digital value.

  3 is a diagram showing a waveform of an image data serial signal transmitted from the LVDS transmitter 118 to the LVDS receiver 152. FIG. 4 is a diagram of an image data serial signal transmitted from the LVDS transmitter 118 to the LVDS receiver 152. It is a figure which shows a structure.

  In FIG. 3, a bit (for example, Bit7) Lb in the image data serial signal has a large amplitude Vod2 (= (Id1 + Id2) × R), and a bit (for example, Bit1, Bit0) Sb in the image data serial signal has a small amplitude Vod1 ( = (Id1) × R), and the image data serial signal includes the information of the synchronization information serial signal corresponding to the change in the amplitude.

  The image data serial signal Dim shown in FIG. 4 includes bit strings 201 to 205,..., 206 corresponding to the image data of lines 1 to 5,. Although not shown in FIG. 4, the image data of each line includes a bit string corresponding to pixel data of 640 pixels.

  Further, FIG. 5 is a table showing an example of a bit string corresponding to each code included in the synchronization control serial signal.

  FIG. 6 is a diagram showing the structure of a synchronous control serial signal other than image data, which is transmitted as amplitude information of a differential voltage from an LVDS transmitter to an LVDS receiver.

  That is, the synchronization control serial signal Dsc includes a bit string 207 as a synchronization code FS indicating the start of a frame, a bit string 208 as a synchronization code CS indicating the start of arbitrary control data, and a bit string as an arbitrary control data following this 209, a bit string 210 as a synchronization code CE indicating the end of the control data, a bit string 211 as line data, and a synchronization code LE 212 indicating the end of the line. Here, each bit string representing a synchronization code, a control code, and arbitrary control data has an 8-bit structure, and each bit information of each bit string is the amplitude information of each bit of 1-pixel data having an 8-bit structure. One pixel data is included.

  The data transmission / reception in the data transmission / reception system 10 shown in FIG. 1 will be specifically described below.

  When image data is input to a transmission data signal processing unit (controller) 16 from an image data generation unit (not shown) such as a digital camera, the transmission data signal processing unit 16 outputs 8-bit luminance data as image line data. [8: 1] and 8-bit color difference data UV [8: 1] are output to the parallel-serial conversion circuit 15. At this time, the transmission data signal processing unit 16 also synchronizes codes FS, FE, LS, LE indicating the position of the image data, arbitrary control data CODE [7: 1] of 7 bits related to the image data, The control codes CS and CE indicating the position of the control data and the transmission clock TXCLK are output to the parallel / serial conversion circuit 15. Then, in the parallel / serial conversion circuit unit, the input transmission clock TXCLK is supplied to the LVDS driver 14b of the LVDS driver group 14 that transmits the transmission clock. The image line data is parallel-serial converted and supplied to the LVDS driver 14a of the LVDS driver group 14 that transmits the image line data. Further, in the parallel / serial conversion circuit unit, the synchronization codes FS, FE, LS, LE, arbitrary control data CODE [7: 1], and the control codes CS, CE are subjected to parallel-serial conversion to obtain a synchronization control serial signal. It is supplied to the LVDS driver 14a.

  The LVDS driver 14b transmits the input transmission clock TXCLK as a differential voltage signal via a pair of signal lines, that is, a non-inverted signal line CK and an inverted signal line CKX.

  Further, the LVDS driver 14a converts the input image data serial signal into a differential amplitude signal, and transmits it through a pair of signal lines, that is, a non-inverted signal line DT and an inverted signal line DTX. The amplitude of the differential amplitude signal of the image data serial signal is changed according to the value of the synchronization control serial signal.

  Thus, the differential amplitude signals output from the LVDS drivers 14a and 14b are respectively received by the corresponding LVDS receivers 13a and 13b on the receiving side. Then, the image data serial signal and the synchronization control serial signal are output from the LVDS receiver 13a to the serial / parallel conversion circuit 12, and the transmission clock is output from the LVDS receiver 13b to the serial / parallel conversion circuit 12.

  Then, the serial-parallel conversion circuit 12 obtains 8-bit luminance data [8: 1] and 8-bit color difference data UV [8: 1] by serial-parallel conversion of the image data parallel signal, which are received signal processing. The synchronization code FS, FE, LS, LE indicating the position of the image data, and 7-bit arbitrary control data CODE [7 associated with the image data are output to the unit 11 and serial-parallel conversion of the synchronization control serial signal. : 1], the control codes CS and CE indicating the position of the control data are obtained, and these are output to the reception signal processing unit 11. In the serial / parallel conversion circuit 12, a reception clock RXCLK obtained by signal processing of the transmission clock is output to the reception signal processing circuit 11.

  The reception signal processing unit 11 requires a circuit (not shown) in the subsequent stage of the reception signal processing unit based on the image data, the synchronization code, an arbitrary control code, and the reception clock obtained from the parallel-serial conversion circuit. Output the correct signal.

  Hereinafter, the operations of the data transmission device 110a and the data reception device 150a will be described in detail with reference to FIG.

  That is, the N-bit (N is a natural number) image data parallel signal input to the parallel-serial converter 15 is converted into an image data serial signal 117 by the image data PS conversion circuit 116 in the parallel-serial conversion circuit 15. The signal value Y of the image data serial signal 117 is input to the input terminal of the LVDS transmitter 118. When the M-bit (M is a natural number) control data, the control code indicating the position of the control data, and the L bit (L is a natural number) are input to the parallel-serial converter 15, the synchronization code, control data, The control code is supplied to the control data conversion circuit 101 in the parallel-serial converter 15.

  In the control data conversion circuit 101, these codes and data are subjected to parallel-serial conversion, and the signal value S of the synchronous control serial signal obtained by the conversion is applied to the gate of the Nch transistor 112. As a result, the signal value Y of the image data serial signal, which is the input signal, is converted into a differential amplitude signal whose amplitude changes in accordance with the value S of the synchronous control serial signal at the LVDS transmitter 118, The signal is output to a pair of current signal lines on the output side of the transmitter 118.

  Specifically, N-bit (N is a natural number) transmission-side image data parallel signal 115 per pixel is converted into image data serial signal 117 by parallel-serial conversion circuit 116, and the signal value of the image data serial signal 117 is converted. Depending on whether Y is “1” or “0”, the direction in which the resistor 151 connected to the pair of current signal lines flows is controlled by the LVDS transmitter 118.

Next, when the signal value S of the transmission side synchronization control serial signal 111 inputted to the gate of the Nch transistor 112 is “1”, the Nch transistor 112 is turned on and the signal value of the transmission side synchronization control serial signal 111 is “0”. In this case, the Nch transistor 112 is turned off. As a result, the current value IR flowing through the resistor 151 is
IR = Id1 (S = “0” and Y = “0”)
IR = −Id1 (S = “0” and Y = “1”)
IR = (Id1 + Id2) (S = “1” and Y = “0”)
IR = − (Id1 + Id2) (S = “1” and Y = “1”)
It becomes. Therefore, by setting the signal value S of the synchronization control serial signal 111 to “1”, the differential voltage amplitude width of the image data serial signal can be doubled, and the image data serial signal and the synchronization control serial signal can be transmitted simultaneously. it can.

  Next, the differential current signal transmitted from the LVDS transmitter 118 in this way is received by the LVDS receiver 152, and the LVDS receiver 152 corresponds to the transmission side synchronization control serial signal by the following comparison processing. The signal value S of the receiving side synchronization control serial signal 153 and the signal value Y of the receiving side image data serial signal 154 corresponding to the transmitting side image data serial signal are output.

When (R × IR)> 0 and (R × IR)> ((Id1 + Id2) × R) / 2, S = “1” and Y = “0” are obtained.

When (R × IR)> 0 and (R × IR) <((Id1 + Id2) × R) / 2, S = “0” and Y = “0” are obtained.

When (R × IR) <0 and (R × IR) <((Id1 + Id2) × R) / 2, S = “1” and Y = “1” are obtained.

When (R × IR) <0 and (R × IR)> ((Id1 + Id2) × R) / 2, S = “0” and Y = “1” are obtained.

In order to optimize the communication error tolerance when the current values Id2 and Id1 flowing through the first constant current source 113 and the second constant current source 114 are compared in the LVDS receiver 152,
Id2 = Id1 × 2
Is desirable.

  Thus, when the signal value Y of the reception-side image data serial signal 154 output from the LVDS receiver 152 is input to the serial-parallel conversion circuit 156, the serial-parallel conversion circuit 156 outputs the image data serial signal. With this serial-parallel conversion, an N-bit (N is a natural number) image data parallel signal is output per pixel. In addition, when the signal value S of the reception-side synchronization control serial signal 153 output from the LVDS receiver 152 is input to the synchronization conversion circuit 155 and the control data conversion circuit 160, the signal value S to be input is input to the synchronization conversion circuit 155. Are compared with a bit array corresponding to each synchronization code held in advance, and a synchronization code corresponding to a bit array that matches the bit array of the input signal value S is output. Similarly, in the control data conversion circuit 160, the bit arrangement of the input signal value S is compared with the bit arrangement corresponding to each control code held in advance, and matches the bit arrangement of the input signal value S. A control code corresponding to the selected bit arrangement is detected, and control data positioned between the control code indicating the start and end of the arbitrary control data is output.

  As shown in FIG. 5, the synchronization code FS indicating the start of one frame, the synchronization code FE indicating the end of one frame, the synchronization code LS indicating the start of one line, the synchronization code LE indicating the end of one line, and the control code By using the control code CS indicating the start end, the arbitrary control data following the control code CS, and the control code CE indicating the end of the arbitrary control data, each line can be easily or without increasing the amount of serial transmission data. It is possible to easily and accurately separate image data for each frame and easily and accurately separate arbitrary control data.

  The arbitrary control data shown here can include information indicating photographing conditions such as an electronic shutter speed and an analog gain setting value that are not included in the idle code and image data.

  An example in FIG. 5 is when the data size of the image data is 8 bits, but expansion to 10 bits or 14 bits can be handled by extending “0” to the LSB side of the synchronization code. . Furthermore, as long as it is a unique serial data string that can identify the codes FS, FE, LS, LE, CS, and CE, it is possible to use other than the example of the serial signal value (bit string) shown in FIG.

  As described above, the present embodiment includes a differential amplitude signal transmission unit that converts an image data serial signal into a differential amplitude signal and transmits the differential amplitude signal. Since the amplitude of the signal is changed according to the value of the synchronous control serial signal, the position of the image data can be recognized easily and accurately without increasing the amount of serial transmission data, speeding up data transmission / reception, and transmission / reception. A small circuit scale of the timing control circuit can be realized.

  Furthermore, since the image data serial signal and the synchronization control serial signal are transmitted / received while changing the amplitude width of the LVDS transmission / reception differential voltage, the start and end of one frame and 1 can be easily transmitted without increasing the amount of serial transmission data. The start and end of line image data and the start and end of one pixel can be recognized, and the start and end of arbitrary control data can be recognized.

  Therefore, the multiplexing process and separation process of image data, synchronization code and synchronization signal, and the multiplexing process and separation process of image data and arbitrary control data and control synchronization signal can be realized with a small circuit scale.

  In addition, the transmission / reception timing control circuit can be realized with a small circuit scale, and the transmission / reception time can be increased. Furthermore, transmission and reception of information indicating photographing conditions such as an electronic shutter speed and an analog gain setting value that are not included in the idle code and image data in the control data can be realized by a single LVDS serial driver and LVDS serial receiver. . Furthermore, since the amplitude width of the synchronization code is increased, the tolerance of communication errors on the receiver side can be improved, and low power consumption can be achieved.

  Note that the synchronization control serial signal Dsc shown in FIG. 6 indicates a first synchronization code indicating the start of one frame, a second synchronization code indicating the end of the one frame, and the start of one line in the one frame. A first control code including a third synchronization code and a fourth synchronization code indicating the end of one line in the one frame, and indicating a starting end of arbitrary control data in the one frame; Although it is assumed that it includes arbitrary control data following the control code CS and a second control code CE indicating the end of the arbitrary control data, the synchronous control serial signal Dsc is not limited to this.

  For example, the synchronization control serial signal Dsc shown in FIG. 6 includes a first synchronization code indicating the start of one frame and a second synchronization code indicating the end of the one frame, and is an arbitrary one in one frame. The first control code indicating the beginning of the control data, the arbitrary control data following the control code CS, and the second control code CE indicating the end of the arbitrary control data may be included.

  Further, the synchronization control serial signal Dsc shown in FIG. 6 includes a first synchronization code indicating the start of one frame, and a control code CS indicating the start of any control data in the one frame, and the control Arbitrary control data following the code and a second control code CE indicating the end of the arbitrary control data may be included.

  Further, the synchronization control serial signal Dsc shown in FIG. 6 includes a fifth synchronization code indicating the start of one pixel data and a sixth synchronization code indicating the end of the one pixel data, and is included in one frame. Including a first control code CS indicating the start of certain arbitrary control data, arbitrary control data following the first control code, and a second control code CE indicating the end of the arbitrary control data But you can.

  Further, the synchronization control serial signal Dsc shown in FIG. 6 includes a fifth synchronization code indicating the start of one pixel data, and a first control code CS indicating the start of any control data in one frame. , Arbitrary control data following the fourth control code, and second control code CE indicating the end of the arbitrary control data may be included.

  The first to sixth synchronization codes are composed of a data string of N bits (N is a natural number), and the first and second control codes and control data are from a data string of M bits (M is a natural number). For example, the first to sixth synchronization codes can be a 9-bit or 10-bit data string other than the 8 bits described above, and the first, second control codes, and The control data can be a 9-bit or 10-bit bit string other than the 8 bits described above.

  In the above embodiment, the data transmitting / receiving device is mounted on a mobile communication terminal (electronic information device) and transmits data between the camera module (image capturing unit) and the display device (image display unit). Although shown, the data transmitter / receiver of the present invention is not limited to the one that performs data transmission between the camera module and the display device in the mobile communication terminal.

  The data transmission / reception system 10 according to the first embodiment is a data transmission / reception unit of a digital camera such as a digital video camera or a digital still camera, or an electronic information device such as an image input camera, a scanner, a facsimile, or a camera-equipped mobile phone device. An electronic information device using the data transmission / reception system 10 according to the first embodiment will be briefly described below.

  An electronic information device according to the present invention uses the digital data transmission / reception system according to the first embodiment of the present invention as a data transmission unit. In the electronic information device, an image data serial signal can be transmitted without increasing the amount of serial transmission data. , A synchronization code indicating the position, arbitrary control data related to the image data, and a control code indicating the position can be transmitted simultaneously, thereby realizing high-speed transmission / reception time. Transmission / reception including information indicating shooting conditions such as shutter speed and analog gain setting value can be realized by one LVDS serial driver and LVDS serial receiver, and the amplitude width of the synchronization code is further increased. It is possible to improve resistance to communication errors and achieve low power consumption.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention is a data transmission device that is mounted on a mobile communication terminal and transmits data between its camera module (image capturing unit) and display device (image display unit), and receives data transmitted thereby. Recognizing the position of image data easily and accurately without increasing the amount of serial transmission data in the field of data receivers, data transmission / reception systems and data transmission / reception methods using the same, and electronic information equipment equipped with the data transmission / reception systems The speed of data transmission / reception and the small circuit scale of the transmission / reception timing control circuit can be realized. Further, when transmitting the image data serial signal to be transmitted / received as a differential amplitude signal, it depends on the value of the synchronization control serial signal By changing the amplitude width of the differential amplitude signal, without increasing the amount of serial transmission data, The data serial signal can be transmitted simultaneously with a synchronization code indicating its position, arbitrary control data related to the image data, and a control code indicating its position, thereby realizing a faster transmission / reception time and further control data. In addition, transmission and reception including information indicating shooting conditions such as electronic shutter speed and analog gain setting value can be realized by a single LVDS serial driver and LVDS serial receiver, and reception is performed by increasing the amplitude width of the synchronization code. It is possible to improve the tolerance of communication errors on the device side and achieve low power consumption.

FIG. 1 is a block diagram illustrating a data transmission / reception system according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining the configuration of the main part of the data transmission / reception system according to the first embodiment, and shows a specific configuration of the data transmission / reception apparatus that constitutes the data transmission / reception system. FIG. 3 is a diagram illustrating a waveform of an image data serial signal transmitted from the LVDS transmitter to the LVDS receiver in the data transmission / reception apparatus according to the first embodiment illustrated in FIG. 2. FIG. 4 is a diagram showing a data structure of an image data serial signal in the data transmission / reception system of the first embodiment. FIG. 5 is a diagram showing a bit string of a synchronization control serial signal superimposed on the differential amplitude signal that is the image data serial signal shown in FIG. 3, and corresponds to, for example, a synchronization code, a control code, arbitrary control data, and line data It is a figure which shows the bit sequence to do. FIG. 6 is a diagram showing a data structure of a synchronization control serial signal in the data transmission / reception system of the first embodiment. FIG. 7 is a block diagram for explaining a data transfer system using a conventional data transfer control device disclosed in Patent Document 1. In FIG. FIG. 8 is a block diagram illustrating a conventional data transmission / reception circuit disclosed in Patent Document 2. In FIG. FIG. 9 is a diagram illustrating a data structure of a serial transmission / reception data string in the conventional data transmission / reception circuit disclosed in Patent Document 2. FIG. 10 is a block diagram for explaining an improved data transmission / reception circuit disclosed in Patent Document 2. In FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Data transmission / reception system 11 Reception data signal processing part 12 Serial parallel conversion circuit 13 LDVS receiver group 13a, 13b LDVS receiver 14 LDVS driver group 14a, 14b LDVS driver 15 Parallel serial conversion circuit 16 Transmission data signal processing part 20a Transmission data signal processing Unit 20b received data signal processing unit 20c transmission line 100a, 100b power supply potential 101 synchronization code / control code / arbitrary control data conversion circuit (control data conversion circuit)
DESCRIPTION OF SYMBOLS 102 Control code and control data 103 Synchronization code 110a Data transmission apparatus 111 Synchronization control serial signal 112 Nch transistor 113 1st constant current power supply 114 2nd constant current power supply 115 Transmission side image data parallel signal 116 Image data PS conversion circuit (Parallel-serial conversion circuit)
117 Transmission Side Image Data Serial Signal 118 LVDS Transmitter 150a Data Receiving Device 151 Resistor 152 LVDS Receiver 153 Reception Side Synchronization Control Data Serial Signal 154 Reception Side Image Data Serial Signal 155 Synchronization Code Conversion Circuit 156 Image Data SP (Serial Parallel conversion circuit)
157 Reception side synchronization code parallel signal 158 Reception side image data parallel signal 159 Reception side synchronization control data parallel signal 160 Control code and arbitrary control data conversion circuit (control data conversion circuit)
201 to 205, 206 Line 1 to Line 5 and Line 480 image data 207 Synchronization code FS bit string 208 Arbitrary control data start point control code CS (bit string)
209 Arbitrary control data (bit string)
210 Control code CE (bit string) indicating the end of arbitrary control data
211 Bit string of line data 212 Synchronization code LE indicating the end of the last frame
R1, R2 resistance

Claims (25)

A digital data transmission device for transmitting digital image data,
A parallel-serial conversion circuit for converting an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal;
The synchronization code indicating the position of the image data, M-bit (M is a natural number) control data related to the image data, and the control code indicating the position of the control data are input, and the synchronization code, the control data, and A data conversion circuit for outputting a synchronous control serial signal including the control code;
A differential amplitude signal transmission unit that converts the image data serial signal into a differential amplitude signal and transmits the differential amplitude signal;
The differential amplitude signal transmission unit is a digital data transmission device that changes the amplitude of the differential amplitude signal of the image data serial signal according to the value of the synchronization control serial signal. The differential amplitude signal transmitter is
A pair of signal output lines, and a current signal is applied to the pair of signal output lines so that a differential voltage corresponding to the image data serial signal is generated in a resistor connected between the pair of signal output lines. A differential transmitter to supply,
A first constant current source connected between a power source and the differential transmitter and always supplying a first drive current to the differential transmitter;
A second constant current source connected between a power source and the differential transmitter and supplying a second drive current to the differential transmitter;
An Nch transistor connected between the second constant current source and the differential amplifier;
Using the synchronization control serial signal as a gate input of the Nch transistor, digital data transmission for controlling on / off of the Nch transistor according to the value of the synchronization control serial signal so that the synchronization control serial signal is transmitted simultaneously with the image data serial signal apparatus. The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame;
A third synchronization code indicating the beginning of one line in the one frame;
A fourth synchronization code indicating the end of one line in the one frame,
And the 1st control code which shows the beginning of arbitrary control data in this 1 frame,
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The first to third synchronization codes are composed of a data string of N bits (N is a natural number),
2. The digital data transmitting apparatus according to claim 1, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame,
And a first control code indicating the beginning of any control data in the one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data, and the first and second synchronization codes are composed of a data string of N bits (N is a natural number),
2. The digital data transmitting apparatus according to claim 1, wherein the first and second control codes and the control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a first synchronization code indicating the beginning of one frame;
And a first control code indicating the beginning of any control data in the one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The first synchronization code is composed of a data string of N bits (N is a natural number),
2. The digital data transmitting apparatus according to claim 1, wherein the first and second control codes and the control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A fifth synchronization code indicating the start of one pixel data;
A sixth synchronization code indicating the end of the one-pixel data,
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number),
2. The digital data transmitting apparatus according to claim 1, wherein the first and second control codes and the control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a fifth synchronization code indicating the start of one pixel data;
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth synchronization code is composed of a data string of N bits (N is a natural number),
2. The digital data transmitting apparatus according to claim 1, wherein the first and second control codes and the control data are composed of a data string of M bits (M is a natural number). The differential amplitude signal obtained by changing the amplitude of the differential amplitude signal of the image data serial signal representing N-bit (N is a natural number) image data per pixel according to the value of the synchronous control serial signal is used as digital data. A digital data receiving device for receiving,
A differential amplitude signal receiving unit that receives the differential amplitude signal and outputs the image data serial signal and the synchronization control serial signal;
A serial-parallel conversion circuit for converting the image data serial signal into an image data parallel signal representing the image data;
A synchronization code conversion circuit that receives the synchronization control serial signal and compares the data string constituting the synchronization control serial signal with a predetermined data string to convert the data string into a synchronization code indicating the position of the image data;
The position of the control data of M bits (M is a natural number) related to the image data is obtained by receiving the synchronization control serial signal and comparing the data sequence constituting the synchronization control serial signal with various determined data sequences. A digital data receiving apparatus comprising a control data / code conversion circuit for converting the control data into control data based on a control code indicating The differential amplitude signal receiver is
Having a pair of signal input lines, converting the amplitude information of the differential voltage into the synchronous control serial signal to a resistor connected between the pair of signal input lines, and outputting the polarity information of the differential voltage. The digital data receiving apparatus according to claim 8, further comprising a differential receiver that converts the image data into a serial signal and outputs the signal. The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame;
A third synchronization code indicating the beginning of one line in the one frame and a fourth synchronization code indicating the end of one line in the one frame;
And the 1st control code which shows the beginning of arbitrary control data in this 1 frame,
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The first to third synchronization codes are composed of a data string of N bits (N is a natural number),
9. The digital data receiving apparatus according to claim 8, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame,
And a first control code indicating the beginning of any control data in the one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The first and second synchronization codes are composed of a data string of N bits (N is a natural number),
9. The digital data receiving apparatus according to claim 8, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a first synchronization code indicating the beginning of one frame;
And a control code indicating the start of arbitrary control data in the one frame;
Any control data following the control code;
A second control code indicating the end of the arbitrary control data,
The first synchronization code is composed of a data string of N bits (N is a natural number),
9. The digital data receiving apparatus according to claim 8, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A fifth synchronization code indicating the start of one pixel data;
A sixth synchronization code indicating the end of the one-pixel data,
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number),
9. The digital data receiving apparatus according to claim 8, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a fifth synchronization code indicating the start of one pixel data;
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth synchronization code is composed of a data string of N bits (N is a natural number),
9. The digital data receiving apparatus according to claim 8, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). A digital data transmission / reception system comprising a digital data transmission device for transmitting digital image data and a digital data reception device for receiving the transmitted digital image data,
The digital data transmitting apparatus includes:
A parallel-serial conversion circuit for converting an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal;
The synchronization code indicating the position of the image data, M-bit (M is a natural number) control data related to the image data, and the control code indicating the position of the control data are input, and the synchronization code, the control data, and A data conversion circuit for outputting a synchronous control serial signal including the control code;
A differential amplitude signal transmission unit that converts the image data serial signal into a differential amplitude signal and transmits the differential amplitude signal;
The differential amplitude signal transmission unit changes the amplitude of the differential amplitude signal of the image data serial signal according to the value of the synchronization control serial signal,
The digital data receiving apparatus includes:
A differential amplitude signal receiving unit that receives the differential amplitude signal and outputs the image data serial signal and the synchronization control serial signal;
A parallel-serial conversion circuit for converting the image data serial signal into an image data parallel signal representing the image data;
A synchronization code conversion circuit that receives the synchronization control serial signal and compares the data string constituting the synchronization control serial signal with a predetermined data string to convert the data string into a synchronization code indicating the position of the image data;
The position of the control data of M bits (M is a natural number) related to the image data is obtained by receiving the synchronization control serial signal and comparing the data sequence constituting the synchronization control serial signal with various determined data sequences. A digital data transmission / reception system comprising a control data code conversion circuit for converting the control data into control data based on a control code indicating The differential amplitude signal transmitter is
A pair of signal output lines, and a current signal is applied to the pair of signal output lines so that a differential voltage corresponding to the image data serial signal is generated in a resistor connected between the pair of signal output lines. A differential transmitter to supply,
A first constant current source connected between a power source and the differential transmitter and always supplying a first drive current to the differential transmitter;
A second constant current source connected between a power source and the differential transmitter and supplying a second drive current to the differential transmitter;
An Nch transistor connected between the second constant current source and the differential amplifier;
The synchronization control serial signal is used as the gate input of the Nch transistor, and the Nch transistor is controlled to be turned on and off according to the value of the synchronization control serial signal so that the synchronization control serial signal is transmitted simultaneously with the image data serial signal. ,
The differential amplitude signal receiver is
It has a pair of signal input lines, converts the amplitude information of the differential voltage into the synchronous control serial signal to a resistor connected between the pair of signal input lines, and outputs the polarity information of the differential voltage. The digital data transmission / reception system according to claim 15, further comprising a differential receiver that converts the image data into a serial signal and outputs the signal. The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame;
A third synchronization code indicating the beginning of one line in the one frame and a fourth synchronization code indicating the end of one line in the one frame;
And the 1st control code which shows the beginning of arbitrary control data in this 1 frame,
Any control data following the first control code CS;
A second control code indicating the end of the arbitrary control data,
The first to third synchronization codes are composed of a data string of N bits (N is a natural number),
16. The digital data transmission / reception system according to claim 15, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A first synchronization code indicating the beginning of one frame;
A second synchronization code indicating the end of the one frame,
And a first control code indicating the start of any control data in the one frame;
Any control data following the control code;
A second control code indicating the end of the arbitrary control data,
The first and second synchronization codes are composed of a data string of N bits (N is a natural number),
16. The digital data transmission / reception system according to claim 15, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a first synchronization code indicating the beginning of one frame;
And a first control code indicating the beginning of any control data in the one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The first synchronization code is composed of a data string of N bits (N is a natural number),
16. The digital data transmission / reception system according to claim 15, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
A fifth synchronization code indicating the start of one pixel data;
A sixth synchronization code indicating the end of the one-pixel data,
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth and sixth synchronization codes are composed of a data string of N bits (N is a natural number),
16. The digital data transmission / reception system according to claim 15, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). The data string constituting the synchronization control serial signal is:
Including a fifth synchronization code indicating the start of one pixel data;
And a first control code indicating the start of any control data in one frame;
Optional control data following the first control code;
A second control code indicating the end of the arbitrary control data,
The fifth synchronization code is composed of a data string of N bits (N is a natural number),
16. The digital data transmission / reception system according to claim 15, wherein the first and second control codes and control data are composed of a data string of M bits (M is a natural number). A digital data transmission method for transmitting digital image data, comprising:
A parallel-serial conversion step of converting an image data parallel signal representing image data of N bits (N is a natural number) per pixel into an image data serial signal;
The synchronization code indicating the position of the image data, M-bit (M is a natural number) control data related to the image data, and the control code indicating the position of the control data are input, and the synchronization code, the control data, and A data conversion step of outputting a synchronous control serial signal including the control code;
A differential amplitude signal transmission step of converting the image data serial signal into a differential amplitude signal and transmitting the differential amplitude signal,
The differential amplitude signal transmission step is a digital data transmission method in which the amplitude of the differential amplitude signal of the image data serial signal is changed according to the value of the synchronization control serial signal. The differential amplitude signal obtained by changing the amplitude of the differential amplitude signal of the image data serial signal representing N-bit (N is a natural number) image data per pixel according to the value of the synchronous control serial signal is used as digital data. A digital data receiving method for receiving,
A differential amplitude signal receiving step for receiving the differential amplitude signal and outputting the image data serial signal and the synchronization control serial signal;
A serial-parallel conversion step of converting the image data serial signal into an image data parallel signal representing the image data;
A synchronization code conversion step for receiving the synchronization control serial signal and converting a data sequence constituting the synchronization control serial signal to a synchronization code indicating a position of the image data by comparing with a variety of determined data sequences;
The position of the control data of M bits (M is a natural number) related to the image data is obtained by receiving the synchronization control serial signal and comparing the data sequence constituting the synchronization control serial signal with various determined data sequences. And a control data code conversion step for converting the control data into control data based on a control code indicating a digital data. A data transmission / reception method including a data transmission step for transmitting digital image data and a data reception step for receiving the transmitted digital image data,
The data transmission step includes:
A parallel-serial conversion step of converting an image data parallel signal representing image data of N bits (N is a positive natural number) per pixel into an image data serial signal;
The synchronization code indicating the position of the image data and the control data of M bits (M is a positive natural number) related to the image data are input, and the control indicating the position of the synchronization code, the control data, and the control data A data conversion step for outputting a synchronous control serial signal including a code;
A differential amplitude signal transmission step of converting the image data serial signal into a differential amplitude signal and transmitting the differential amplitude signal,
The differential amplitude signal transmission step changes the amplitude of the differential amplitude signal of the image data serial signal according to the value of the synchronous control serial signal,
The data receiving step includes:
A differential amplitude signal receiving step for receiving the differential amplitude signal and outputting the image data serial signal and the synchronization control serial signal;
A serial-parallel conversion step of converting the image data serial signal into an image data parallel signal representing the image data;
A synchronization code conversion step for receiving the synchronization control serial signal and converting a data sequence constituting the synchronization control serial signal to a synchronization code indicating a position of the image data by comparing with a variety of determined data sequences;
M-bit (M is a positive natural number) control data related to the image data by receiving the synchronization control serial signal and comparing the data sequence constituting the synchronization control serial signal with various determined data sequences A digital data transmission / reception system including a control data code conversion step for converting the control data into control data based on a control code indicating the position of the data.   The electronic information device carrying the data transmission / reception system in any one of Claims 15-21.

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