CN117935729A - Data processing system and Micro-OLED display system - Google Patents

Data processing system and Micro-OLED display system Download PDF

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Publication number
CN117935729A
CN117935729A CN202311723101.7A CN202311723101A CN117935729A CN 117935729 A CN117935729 A CN 117935729A CN 202311723101 A CN202311723101 A CN 202311723101A CN 117935729 A CN117935729 A CN 117935729A
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China
Prior art keywords
signal
data
signal transmission
micro
transmission channel
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CN202311723101.7A
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Chinese (zh)
Inventor
谢俊杰
王本洋
周昊翔
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Zhejiang Hongxi Technology Co ltd
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Zhejiang Hongxi Technology Co ltd
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Priority to CN202311723101.7A priority Critical patent/CN117935729A/en
Publication of CN117935729A publication Critical patent/CN117935729A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application relates to a data processing system and a Micro-OLED display system, wherein the data processing system comprises a data transmitter, a signal transmission channel and a data receiver, and the data transmitter is connected with the data receiver through the signal transmission channel; the data transmitter is used for encoding an external video signal into an MIPI signal and a control signal, and transmitting the MIPI signal and the control signal to the data receiver through the signal transmission channel, and the data receiver is used for converting the MIPI signal and the control signal into a digital signal and a time sequence which can be identified by an analog driving module of the Micro-OLED display screen; wherein data is allowed to be transmitted through the signal transmission path on both clock rising and falling edges between the data transmitter and the data receiver signals. The application allows data to be transmitted on the rising edge and the falling edge of the clock pulse in the MIPI protocol data transmission process, can realize double transmission rate without increasing clock frequency, and improves the image signal transmission speed.

Description

Data processing system and Micro-OLED display system
Technical Field
The application relates to the technical field of image display, in particular to a data processing system and a Micro-OLED display system.
Background
The current MIPI protocol standard is one of main standards of image output in the Micro OLED display field, and aims to standardize internal interfaces such as a camera interface, a display screen interface, a radio frequency/baseband interface and the like, a physical Layer (Phy Layer) of DSI is formulated by a special work group (work group) work group, the current standard is D-PHY, and the D-PHY adopts 1 pair of source synchronous differential clocks and 1-4 pairs of differential data lines to carry out data transmission, and can realize signal transmission from image signals to a display pixel area through MIPI protocol ports.
With the development of Micro-OLED technology, higher requirements are put forward on display driving definition, resolution and transmission speed, and particularly, for Micro-led silicon-based display requirements, the current data transmission mode based on MIPI protocol cannot meet the use requirements.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a data processing system and a Micro-OLED display system, which solve the above-mentioned problems of the prior art.
To achieve the above and other related objects, the present application provides a data processing system comprising:
A data transmitter;
A signal transmission channel;
the data transmitter is connected with the data receiver through the signal transmission channel;
The data transmitter is used for encoding an external video signal into an MIPI signal and a control signal, and transmitting the MIPI signal and the control signal to the data receiver through the signal transmission channel, and the data receiver is used for converting the MIPI signal and the control signal into a digital signal and a time sequence which can be identified by an analog driving module of the Micro-OLED display screen;
wherein data is allowed to be transmitted through the signal transmission path on both clock rising and falling edges between the data transmitter and the data receiver signals.
In an alternative embodiment of the present application, the data transmitter includes a coding module and a first signal interface, where the coding module is connected to the signal transmission channel through the first signal interface, and the coding module is configured to code an external video signal into an MIPI signal and a control signal, and send the MIPI signal and the control signal to the signal transmission channel through the first signal interface.
In an alternative embodiment of the present application, the data receiver includes a second signal interface, a memory, and a decoding module, the memory is connected to the signal transmission channel through the second signal interface, and the decoder is connected to the memory;
The memory is used for storing MIPI signals and control signals received by the data receiver, and the decoding module is used for reading the stored MIPI signals and control signals from the memory and converting the MIPI signals and control signals into digital signals and time sequences which can be identified by an analog driving module of the Micro-OLED display screen.
In an alternative embodiment of the present application, the signal transmission channel includes:
a plurality of groups of data signal transmission channels for transmitting differential data signals;
a set of clock signal transmission channels for transmitting differential clock signal pairs;
a reference voltage transmission channel for transmitting a memory reference voltage;
a deskew signal transmission channel for transmitting a deskew signal.
In an alternative embodiment of the present application, the data transmitter can select a suitable number of the data signal transmission channels for data transmission according to the resolution and the sharpness required by the image.
In an alternative embodiment of the present application, the terminal of the data signal transmission channel is provided with an ODT resistance module.
In an alternative embodiment of the present application, the signal transmission channel further includes an ODT enable signal transmission channel for transmitting an ODT enable signal.
To achieve the above and other related objects, the present application also provides a Micro-OLED display system comprising:
a high-speed digital processing chip including a data transmitter;
A signal transmission channel;
The pixel driving chip comprises a data receiver, an analog driving module and a Micro-OLED display screen, wherein the data transmitter is connected with the data receiver through the signal transmission channel, the data receiver is connected with the input end of the analog driving module, and the output end of the analog driving module is connected with the Micro-OLED display screen;
The data transmitter is used for encoding an external video signal into an MIPI signal and a control signal according to an MIPI protocol and transmitting the MIPI signal and the control signal to the data receiver through the signal transmission channel, the data receiver is used for converting the MIPI signal and the control signal into a digital signal and a time sequence, and the analog driving module is used for outputting a pixel driving voltage to the Micro-OLED display screen based on the digital signal and the time sequence;
wherein data is allowed to be transmitted through the signal transmission path on both clock rising and falling edges between the data transmitter and the data receiver signals.
In an alternative embodiment of the present application, the data transmitter includes a coding module and a first signal interface, where the coding module is connected to the signal transmission channel through the first signal interface, and the coding module is configured to code an external video signal into an MIPI signal and a control signal, and send the MIPI signal and the control signal to the signal transmission channel through the first signal interface.
In an alternative embodiment of the present application, the data receiver includes a second signal interface, a memory, and a decoding module, the memory is connected to the signal transmission channel through the second signal interface, and the decoder is connected to the memory;
The memory is used for storing MIPI signals and control signals received by the data receiver, and the decoding module is used for reading the stored MIPI signals and control signals from the memory and converting the MIPI signals and control signals into digital signals and time sequences which can be identified by an analog driving module of the Micro-OLED display screen.
In an alternative embodiment of the present application, the signal transmission channel includes:
a plurality of groups of data signal transmission channels for transmitting differential data signals;
a set of clock signal transmission channels for transmitting differential clock signal pairs;
a reference voltage transmission channel for transmitting a memory reference voltage;
a deskew signal transmission channel for transmitting a deskew signal.
In an alternative embodiment of the present application, the data transmitter can select a suitable number of the data signal transmission channels for data transmission according to the resolution and the sharpness required by the image.
In an alternative embodiment of the present application, the terminal of the data signal transmission channel is provided with an ODT resistance module.
In an alternative embodiment of the present application, the signal transmission channel further includes an ODT enable signal transmission channel for transmitting an ODT enable signal.
In an optional embodiment of the application, the analog driving module includes a digital-to-analog conversion circuit, a voltage generation circuit and an operational amplifier circuit;
the digital-to-analog conversion circuit is connected with the data receiver and is used for converting digital signals output by the data receiver into analog signals;
The voltage generation circuit is connected with the digital-to-analog conversion circuit and is used for outputting stable reference voltage according to the analog signal output by the digital-to-analog conversion circuit;
The operational amplifier circuit is respectively connected with the digital-to-analog conversion circuit and the voltage generation circuit, and is used for outputting pixel driving voltage to the Micro-OLED display screen according to the reference voltage output by the voltage generation circuit and referring to the time sequence signal output by the data receiver.
In an optional embodiment of the present application, an FPC interface is further disposed on the pixel driving chip, and an external video signal is accessed through the FPC interface and is transmitted to the high-speed digital processing chip through an interconnection structure between the pixel driving chip and the high-speed digital processing chip.
In an alternative embodiment of the present application, the interconnection between the pixel driving chip and the high-speed digital processing chip is realized through I/Opad.
According to the data processing system and the Micro-OLED display system, data is allowed to be transmitted on the rising edge and the falling edge of clock pulses in the MIPI protocol data transmission process, double transmission rate can be achieved under the condition that clock frequency is not increased, and image signal transmission speed is increased.
According to the data processing system and the Micro-OLED display system, the ODT resistance module is arranged at the terminal of the data signal transmission channel, and the ODT enable signal transmission channel is arranged between the data transmitter and the data receiver and used for transmitting the ODT enable signal, so that the access of the ODT resistance module can be controlled in the high-speed data transmission process, the signal is ensured to be absorbed by the terminal of the circuit without being reflected on the circuit, the influence on the following signal is caused, the frame number and the pixel signal quality are improved, and the Micro OLED picture display quality is improved.
Drawings
FIG. 1 shows a schematic diagram of the Micro-OLED display system of the present application.
FIG. 2 shows a functional block diagram of a Micro-OLED display system of the present application.
Fig. 3 shows a functional block diagram of the analog driving module of the present application.
Fig. 4 is a schematic diagram showing the present application for setting an ODT resistance module at a terminal of a data signal transmission channel.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
The application introduces a Micro-OLED display system based on a data transmission mode of an improved MIPI protocol, wherein FIG. 1 shows a structural schematic diagram of the Micro-OLED display system, and FIG. 2 outputs a functional module schematic diagram of the Micro-OLED display system.
As shown in fig. 1, the Micro-OLED display system mainly comprises a high-speed digital processing chip 1, a pixel driving chip 2 and a signal transmission channel for connecting the two. The pixel driving chip 2 is provided with a Micro-OLED display screen 19 and two rows of input/output pins (I/O pads) 12 and 13, one row of input/output pins 12 of the pixel driving chip 2 is interconnected with the package of the high-speed digital processing chip 1 after being flipped, the other row of I/O input/output pins 13 of the pixel driving chip 2 is used as an FPC interface, the other row of input/output pins are connected with external terminals such as a computer and a mobile phone through an FPC flexible connection line 3, video signals of the external terminals such as the computer and the mobile phone can be transmitted to the high-speed digital processing chip 1 through the FPC flexible connection line 3, the FPC interface and the internal wiring of the pixel driving chip 2 and then are transmitted to the high-speed digital processing chip 1 through the interconnection structure between the pixel driving chip 2 and the high-speed digital processing chip 1, the processed signals are transmitted to the pixel driving chip 2 for display, and the pixel driving chip 2 transmits the external video signals to the high-speed digital processing chip 1 through different pins of the input/output pins 12.
As shown in fig. 1 and 2, the high-speed digital processing chip 1 includes a data transmitter 21; the pixel driving chip 2 comprises a data receiver 14, an analog driving module 18 and a Micro-OLED display screen 19; the data transmitter 21 is connected with the data receiver 14 through the signal transmission channel, the input end of the data receiver 14 is connected with the analog driving module 18, and the output end of the analog driving module 18 is connected with the Micro-OLED display screen 19; the data transmitter 21 is configured to encode external video signals into MIPI signals such as d0_p/N to d7_p/N, ck_p/N, vref, etc. and control signals such as odt_en, initial_deskew, etc. according to MIPI protocol, and transmit the signals to the data receiver 14 through the signal transmission channel, the data receiver 14 is configured to convert the MIPI signals and the control signals into digital signals and time sequences, and the analog driving module 18 is configured to output pixel driving voltages to the Micro-OLED display screen 19 based on the digital signals and time sequences. Wherein the data transmitter 21, the signal transmission channel and the data receiver 14 form a data processing system of the Micro-OLED display system.
In order to increase the transmission rate, the data transmitter 21 and the data receiver 14 may be set to an internal mode based on the MIPI protocol to allow data to be transmitted on the rising and falling edges of a clock, that is, the data transmitter 21 and the data receiver 14 may allow data to be transmitted through the signal transmission channel on the rising and falling edges of the clock, so that the data may be transmitted on the rising and falling edges of the clock at the time of transmitting the data at a high speed, or on the rising or falling edges of the clock at the time of transmitting the data at a low speed, and the double transmission rate may be achieved without increasing the clock frequency, thereby increasing the image signal transmission rate. It will be appreciated that in other embodiments, the data may be transferred only on the rising and falling edges of the clock pulses when transferring data at high speeds, and on the rising or falling edges of the clock pulses when transferring data at low speeds.
As shown in fig. 2, in a specific embodiment, the data transmitter 21 may be integrated in the high-speed digital processing chip 1, and includes a first signal interface 22 and a coding module 22 integrated in the data transmitter 21, where the coding module 22 is connected to the signal transmission channel through the first signal interface 22, and the coding module 22 is configured to code an external video signal into an MIPI signal and a control signal according to an MIPI protocol, and send the MIPI signal and the control signal to the signal transmission channel through the first signal interface 22. Of course, the encoding module 22 may also be integrated independently within the high-speed digital processing chip 1.
In one embodiment, as shown in fig. 2, the data receiver 14 is configured to convert the MIPI signal and control signal into digital signals and timing. The data receiver 14 may be integrated in the high-speed digital processing chip 1, and comprises a second signal interface 15, and a memory 16 and a decoding module 17 integrated in the data receiver 14, wherein the memory 16 is connected with the signal transmission channel through the second signal interface 15, the decoder is connected with the memory 16, the memory 16 is used for storing MIPI signals and control signals received by the data receiver 14, and the decoding module 17 is used for reading the stored MIPI signals and control signals from the memory 16 and converting the stored MIPI signals and control signals into digital signals and time sequences which can be identified by an analog driving module 18 of the Micro-OLED display 19. Of course, the memory 16 and the decoding module 17 may also be integrated independently within the high-speed digital processing chip 1.
As shown in fig. 2, the signal transmission channels include a data signal transmission channel d0_p/N to d7_p/N, a clock signal transmission channel ck_p/N, a deskew signal transmission channel initial_deskew, a reference voltage transmission channel Vref, and an ODT enable signal transmission channel odt_en, and the number of the data signal transmission channels d0_p/N to d7_p/N, the clock signal transmission channel ck_p/N, the deskew signal transmission channel initial_deskew, the reference voltage transmission channel Vref, and the ODT enable signal transmission channel odt_en may be set according to actual needs. Corresponding to the signal transmission channels d0_p/N to d7_p/N, the first signal interface 22 and the second signal interface 15 are respectively provided with interfaces corresponding to the data signal transmission channels d0_p/N to d7_p/N, the clock signal transmission channel ck_p/N, initial _deskew, the reference voltage transmission channel Vref and the ODT enable signal transmission channel odt_en one by one.
In one embodiment, as shown in FIG. 2, the signal transmission channels include several sets of data signal transmission channels D0_P/N-D7_P/N for transmitting differential data signals. Each set of the data signal transmission channels includes a P-channel and an N-channel for transmitting differential data signal pairs, the differential data signals are sent by the data transmitter 21 and transmitted to the data receiver 14 via at least one set of the data signal transmission channels, and noise of the data signals can be eliminated or reduced by adopting a data transmission mode of the differential data signal pairs. By arranging a plurality of groups of data signal transmission channels D0_P/N-D7_P/N, when data signal transmission is performed, the data signal transmission channels with proper groups can be selected according to the resolution and definition required by an image to perform data transmission. The number of the data signal transmission channels can be determined according to the highest transmission rate required by the resolution and the definition of the actual image transmission, and the larger the required highest transmission rate is, the more the number of the groups of the required data signal transmission channels is.
Taking the 8 groups of data signal transmission channels d0_p/N to d7_p/N in fig. 2 as an example, the number of groups of data signal transmission channels can be selectively used according to the resolution and the definition required by the pixels, when the pixels are required to be high in frame number and high in resolution, the required data transmission rate is necessarily high, the number of groups of data signal transmission channels can be selected to be 6-8 groups, when the pixels are required to be low in frame number and low in resolution, the required data transmission rate is necessarily low, and the number of groups of data signal transmission channels can be selected to be less than 4 groups.
In one embodiment, as shown in FIG. 2, the signal transmission channels include a set of clock signal transmission channels CK_P/N for transmitting differential clock signal pairs. The clock signal transmission channels ck_p/N include ck_p channels and ck_n channels for transmitting differential clock signal pairs, and the differential clock signals are sent by the data transmitter 21 and transmitted to the data receiver 14 via the clock channels, and noise of the clock signals can be eliminated or reduced by adopting the data transmission mode of the differential clock signal pairs.
In one embodiment, as shown in fig. 2, the signal transmission channel includes a deskew signal transmission channel, which is used as a transmission channel for transmitting an Initial deskew signal (initial_deskew burst) from the data transmitter 21 to the data receiver 14, so that the data receiver 14 performs deskewing calibration according to the Initial deskew signal sent by the data transmitter 21, thereby eliminating a phase difference that may exist between the clock transmission channel and the data transmission channel.
Specifically, when the transmission rate is equal to or greater than the preset transmission rate, or the transmission rate is increased to or above the preset transmission rate, the data transmitter 21 needs to transmit an initial deskew burst to the data receiver 14 before high-speed data transmission, so that the data receiver 14 performs deskew according to the data transmitted by the data transmitter 21; and when the transmission rate is smaller than the preset transmission rate, the deskewing calibration is an optional function, and whether to perform the deskewing calibration can be selected according to the actual choice. Of course, it is also possible to perform periodic deskewing, and configure the periodic deskewing function to be optional, so as to select whether to perform periodic deskewing according to actual conditions. The preset transmission rate can be reasonably selected according to practical situations, and in this embodiment, the preset transmission rate takes a value of 1.6Gbps.
In one embodiment, as shown in fig. 2, the signal transmission channel includes a reference voltage transmission channel Vref for transmitting the memory reference voltage. The memory reference voltage is sent by the data transmitter 21 and transmitted to the data receiver 14 through the reference voltage transmission channel Vref, and the data receiver 14 can perform read-write operation of the memory 16 according to the received memory reference voltage, so as to ensure read-write stability of the MIPI signal and the control signal, prevent the MIPI signal and the control signal from being lost in the read-write process, thereby improving signal stability and Micro OLED picture display quality.
As shown in fig. 2 and 4, the Micro-OLED display system further includes a DT-enable signal path odt_en as a signal transmission path, and an ODT resistance module provided on a terminal of a part or all of the data signal path, the ODT resistance module being connected to the data receiver 14.
The ODT enable signal channel odt_en is used for transmitting an ODT enable signal to the data receiver 14, the ODT enable signal is sent by the data transmitter 21 and is transmitted through the ODT enable signal channel odt_en, the ODT enable signal is received by the data receiver 14, after the data receiver 14 receives the ODT enable signal, whether the ODT resistor module needs to be accessed or not is judged according to the data transmission speed, when the data signal is transmitted at a low speed, the ODT resistor module is not accessed, and in the process of transmitting the data at a high speed, reflection is easily formed on a circuit, the ODT resistor module is accessed, the signal is ensured to be absorbed by a terminal of the circuit, and reflection is not formed on the circuit, so that the influence on a following signal can be avoided, the frame number of a picture and the quality of the pixel signal are improved, and the display quality of the Micro OLED picture is further improved.
As shown in fig. 3, in one embodiment, the analog driving module 18 includes a digital-to-analog conversion circuit 181 (DAC circuit), a GAMMA voltage generating circuit 182, and an operational amplifier circuit 183 (OP amplifier circuit); the digital-to-analog conversion circuit 181 is connected to the data receiver 14 and is configured to convert digital signals and time sequences output by the data receiver 14 into analog signals and time sequences; the GAMMA voltage generating circuit 182 is connected to the digital-to-analog conversion circuit 181, and is configured to output a reference voltage within a certain range according to an analog signal output by the digital-to-analog conversion circuit 181 and maintain the stability of the reference voltage; the operational amplifier circuit 183 is connected to the dac circuit 181 and the GAMMA voltage generating circuit 182, respectively, and the operational amplifier 183 is configured to output a pixel driving voltage to the Micro-OLED display 19 according to the reference voltage output by the GAMMA voltage generating circuit 182 and with reference to a timing sequence output by the dac circuit 181, so as to control a pixel switching state of each pixel subunit in the Micro-OLED display 19 and voltage values at different times, so as to implement a change in a pixel display color.
The whole workflow of the Micro-OLED display system is as follows:
The external video signal enters and is transmitted to the high-speed digital processing chip 1 through the FPC interface on the pixel driving chip 2, the high-speed digital processing chip 1 is connected with an internal coding module 22, the external video signal is coded into MIPI signals such as D0_P/N-D7_P/N, CK_P/N, vref and the like and control signals such as ODT_EN, initial_deskew and the like according to MIPI protocol, the MIPI signals and the control signals are transmitted to a data receiver 14 of the pixel driving chip 2 through a data transmitter 21, the pixel driving chip 2 firstly stores the MIPI signals and the control signals into a memory 16 after receiving the MIPI signals and the control signals, then the MIPI signals and the control signals are decoded through a decoding module 17 in the data receiver 14, the MIPI signals and the control signals are converted into digital signals and time sequences which can be identified by an analog driving module 18 in the pixel driving chip 2, the analog driving module 18 outputs pixel driving voltages to the Micro-OLED display screen 19 based on the pixel driving voltages, and the Micro-OLED display screen 19 controls pixel switching states and voltage values of each pixel sub-units in the Micro-OLED display screen 19 to realize color changes.
In summary, the data processing system and the Micro-OLED display system of the present application allow data to be transmitted on the rising edge and the falling edge of the clock pulse in the MIPI protocol data transmission process, so that the double transmission rate can be realized without increasing the clock frequency, and the image signal transmission rate can be increased.
According to the data processing system and the Micro-OLED display system, the ODT resistance module is arranged at the terminal of the data signal transmission channel, and the ODT enable signal transmission channel is arranged between the data transmitter and the data receiver and used for transmitting the ODT enable signal, so that the access of the ODT resistance module can be controlled in the high-speed data transmission process, the signal is ensured to be absorbed by the terminal of the circuit without being reflected on the circuit, the influence on the following signal is caused, the frame number and the pixel signal quality are improved, and the Micro OLED picture display quality is improved.
In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that an embodiment of the application can be practiced without one or more of the specific details, or with other apparatus, systems, components, methods, components, materials, parts, and so forth.
It will also be appreciated that one or more of the elements shown in the figures may also be implemented in a more separated or integrated manner, or even removed because of inoperability in certain circumstances or provided because it may be useful depending on the particular application.
In addition, any labeled arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise specifically indicated. Furthermore, the term "or" as used herein is generally intended to mean "and/or" unless specified otherwise. Combinations of parts or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
The above description of illustrated embodiments of the application, including what is described in the abstract, is not intended to be exhaustive or to limit the application to the precise forms disclosed herein. Although specific embodiments of, and examples for, the application are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present application, as those skilled in the relevant art will recognize and appreciate. As noted, these modifications can be made to the present application in light of the foregoing description of illustrated embodiments of the present application and are to be included within the spirit and scope of the present application.
The systems and methods have been described herein in general terms as being helpful in understanding the details of the present application. Furthermore, various specific details have been set forth in order to provide a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that an embodiment of the application can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the application.
Thus, although the application has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the application will be employed without a corresponding use of other features without departing from the scope and spirit of the application as set forth. Therefore, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present application. It is intended that the application not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this application, but that the application will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the application should be determined only by the following claims.

Claims (17)

1. A data processing system, comprising:
A data transmitter;
A signal transmission channel;
the data transmitter is connected with the data receiver through the signal transmission channel;
The data transmitter is used for encoding an external video signal into an MIPI signal and a control signal, and transmitting the MIPI signal and the control signal to the data receiver through the signal transmission channel, and the data receiver is used for converting the MIPI signal and the control signal into a digital signal and a time sequence which can be identified by an analog driving module of the Micro-OLED display screen;
wherein data is allowed to be transmitted through the signal transmission path on both clock rising and falling edges between the data transmitter and the data receiver signals.
2. The data processing system of claim 1, wherein the data transmitter comprises an encoding module and a first signal interface, the encoding module being coupled to the signal transmission path via the first signal interface, the encoding module being configured to encode an external video signal into a MIPI signal and a control signal and to transmit the MIPI signal to the signal transmission path via the first signal interface.
3. The data processing system of claim 2, wherein the data receiver comprises a second signal interface, a memory and a decoding module, the memory being coupled to the signal transmission channel through the second signal interface, the decoder being coupled to the memory;
The memory is used for storing MIPI signals and control signals received by the data receiver, and the decoding module is used for reading the stored MIPI signals and control signals from the memory and converting the MIPI signals and control signals into digital signals and time sequences which can be identified by an analog driving module of the Micro-OLED display screen.
4. A data processing system according to claim 3, wherein the signal transmission path comprises:
a plurality of groups of data signal transmission channels for transmitting differential data signals;
a set of clock signal transmission channels for transmitting differential clock signal pairs;
a reference voltage transmission channel for transmitting a memory reference voltage;
a deskew signal transmission channel for transmitting a deskew signal.
5. The data processing system of claim 4 wherein the data transmitter is capable of selecting an appropriate number of the data signal transmission channels for data transmission based on the resolution and sharpness of the image requirements.
6. The data processing system of claim 4, wherein the termination of the data signal transmission path is provided with an ODT resistance module.
7. The data processing system of claim 6, wherein the signal transmission channel further comprises an ODT enable signal transmission channel for transmitting an ODT enable signal.
8. A Micro-OLED display system, comprising:
a high-speed digital processing chip including a data transmitter;
A signal transmission channel;
The pixel driving chip comprises a data receiver, an analog driving module and a Micro-OLED display screen, wherein the data transmitter is connected with the data receiver through the signal transmission channel, the data receiver is connected with the input end of the analog driving module, and the output end of the analog driving module is connected with the Micro-OLED display screen;
The data transmitter is used for encoding an external video signal into an MIPI signal and a control signal according to an MIPI protocol and transmitting the MIPI signal and the control signal to the data receiver through the signal transmission channel, the data receiver is used for converting the MIPI signal and the control signal into a digital signal and a time sequence, and the analog driving module is used for outputting a pixel driving voltage to the Micro-OLED display screen based on the digital signal and the time sequence;
wherein data is allowed to be transmitted through the signal transmission path on both clock rising and falling edges between the data transmitter and the data receiver signals.
9. The Micro-OLED display system according to claim 8, wherein the data transmitter includes an encoding module and a first signal interface, the encoding module is connected to the signal transmission channel through the first signal interface, and the encoding module is configured to encode an external video signal into a MIPI signal and a control signal, and transmit the MIPI signal and the control signal to the signal transmission channel through the first signal interface.
10. The Micro-OLED display system according to claim 9, wherein the data receiver includes a second signal interface, a memory and a decoding module, the memory is connected to the signal transmission channel through the second signal interface, and the decoder is connected to the memory;
The memory is used for storing MIPI signals and control signals received by the data receiver, and the decoding module is used for reading the stored MIPI signals and control signals from the memory and converting the MIPI signals and control signals into digital signals and time sequences which can be identified by an analog driving module of the Micro-OLED display screen.
11. The Micro-OLED display system of claim 10, wherein the signal transmission channel comprises:
a plurality of groups of data signal transmission channels for transmitting differential data signals;
a set of clock signal transmission channels for transmitting differential clock signal pairs;
a reference voltage transmission channel for transmitting a memory reference voltage;
a deskew signal transmission channel for transmitting a deskew signal.
12. The Micro-OLED display system according to claim 11, wherein the data transmitter can select an appropriate number of the data signal transmission channels for data transmission according to the resolution and the sharpness required by the image.
13. The Micro-OLED display system according to claim 11, wherein the terminal of the data signal transmission channel is provided with an ODT resistance module.
14. The Micro-OLED display system of claim 13, wherein the signal transmission channel further comprises an ODT enable signal transmission channel for transmitting an ODT enable signal.
15. The Micro-OLED display system of claim 8, wherein the analog driving module includes a digital-to-analog conversion circuit, a voltage generation circuit, and an operational amplification circuit;
The digital-to-analog conversion circuit is connected with the data receiver and is used for converting digital signals and time sequences output by the data receiver into analog signals and time sequences;
The voltage generation circuit is connected with the digital-to-analog conversion circuit and is used for outputting stable reference voltage according to the analog signal output by the digital-to-analog conversion circuit;
The operational amplifier circuit is respectively connected with the digital-to-analog conversion circuit and the voltage generation circuit, and is used for outputting pixel driving voltage to the Micro-OLED display screen according to the reference voltage output by the voltage generation circuit and referring to the time sequence output by the digital-to-analog conversion circuit.
16. The Micro-OLED display system according to claim 8, wherein an FPC interface is further provided on the pixel driving chip, and an external video signal is accessed through the FPC interface and is transmitted to the high-speed digital processing chip through an interconnection structure between the pixel driving chip and the high-speed digital processing chip.
17. The Micro-OLED display system of claim 8, wherein the pixel driving chip and the high-speed digital processing chip are interconnected by an I/O pad.
CN202311723101.7A 2023-12-14 2023-12-14 Data processing system and Micro-OLED display system Pending CN117935729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311723101.7A CN117935729A (en) 2023-12-14 2023-12-14 Data processing system and Micro-OLED display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311723101.7A CN117935729A (en) 2023-12-14 2023-12-14 Data processing system and Micro-OLED display system

Publications (1)

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CN117935729A true CN117935729A (en) 2024-04-26

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