JPH07212690A - Picture size conversion circuit - Google Patents

Abstract

PURPOSE:To display a picture on a PDP (plasma display panel) by compressing picture element number so as to convert a picture size without decreasing a sampling frequency in the case of A/D conversion and without interleaving picture elements. CONSTITUTION:An input video signal is separated into a luminance signal and a chrominance signal by a Y/C separate section 2, an inverse MTX circuit 3 converts them into three color signals R, G, B, they are sampled at an A/D converter section 4 based on a clock signal whose frequency is 14.318MHz and converted into digital signals, required processing is implemented by a digital processing section 5 and in order to make a picture element number of one line corresponding to a picture element number of a PDP or the like for a display section 7, a 6-5 conversion section 6 divides the signal for each 6 picture elements to convert 6 picture elements of each division into 5 picture elements, the converted signal is inputted to the display section to be displayed on the PDP or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image size conversion circuit, and more particularly to an image size conversion circuit for compressing the number of pixels of one line of an input image so as to match the number of pixels of a display body without deteriorating the image quality.

[0002]

2. Description of the Related Art PDP (plasma display panel)
Alternatively, on a display body such as an LCD (liquid crystal display board), the aspect ratio of the screen is 3 to 4 vertically and the aspect ratio of the number of pixels is also 3 to 4.
Some are 480 vertical by 640 horizontal.
If the ratio of the number of vertical and horizontal pixels of the input image is the same as this,
The aspect ratio of the displayed image matches that of the original image. By the way, it is necessary to digitally convert a video signal for displaying on a PDP or LCD, and the frequency of this sampling clock is, for example, the color carrier frequency (3.
When the frequency is set to 14.318MHz, which is four times as high as 58MHz = megahertz (it is convenient because it is possible to use signal processing at this clock frequency for the subsequent circuit), the number of pixels corresponding to one horizontal scanning line period (1H) is About 910 pixels (1H = 63.5μ
S = microsecond divided by the sampling frequency 14.318 MHz). On the other hand, the number of pixels of 1H is the number of samples when sampling at a frequency of 13.5MHz according to CCIR (International Radiocommunication Advisory Committee) No. 601 recommended digital component sampling standard.
Since the number of effective samples for 1H is 720 (pixels) for the value obtained by dividing by the reciprocal of z, the number of effective samples for 1H (pixels) when sampling the input image at the above-mentioned clock frequency of 14.318MHz is , 910 × (720/858) ≒ 764 (pixels). On the other hand, since the number of effective pixels in the vertical direction is 483, the aspect ratio of the image is 483 in the vertical direction and 764 in the horizontal direction ≈ 3 in the horizontal direction and 4.
It becomes a horizontally stretched image of 74. If the display body is a cathode ray picture tube, the aspect ratio of the displayed image can be changed by appropriately setting the deflection circuit of the picture tube. PDP or LCD
If you can't do this. If you only want to solve the horizontal stretch of the image, for example, by setting the sampling frequency to 15.734KHz × (858/720) × 640 ≈ 12MHz (where 15.734KHz is the reciprocal of 1H = 63.5μS) It is possible, but in this case, the frequency of the aliasing elimination filter (low-pass filter for cutting the frequency component more than half of the sampling clock) inserted before the digital conversion circuit corresponds to this 12MHz.
In addition to the problem that the resolution must be reduced to 6 MHz, as described above, there is a problem that a general-purpose one with a clock frequency of 14.318 MHz cannot be used for the subsequent signal processing circuit.

[0003]

In view of the above, the present invention has a sampling clock frequency of 14.318 MHz (color subcarrier signal frequency of 3.58 MHz, 4) of the digital conversion circuit.
The number of pixels of 1H is compressed so as to match the number of pixels of a display body such as a PDP, and the image quality is not impaired, and the clock frequency of the subsequent signal processing circuit is 14.318.
It is to be able to use the thing of MHz.

[0004]

In order to solve the above-mentioned problems, the present invention separates a video signal into three signals of red, green and blue, and each color signal from the separation part is a color subcarrier signal. The A / D converter that samples at a frequency four times higher than that and converts into a digital signal, and each color signal from the A / D converter is divided into 6 pixels, and the 6th pixel of each division and the 1st of the previous division And a 6-5 conversion unit for averaging the pixels and outputting the second to fifth pixels in succession,
The present invention provides an image size conversion circuit adapted to display based on a signal from the 6-5 conversion unit.

[0005]

With the above construction, in the image size conversion circuit according to the present invention, the composite video signal is separated into the luminance signal and the chrominance signal by the Y / C separation section, and the inverse MTX (matrix) circuit produces the red ( R), green (G) and blue (B) color signals are processed and sampled by the A / D converter at a clock of 14.318MHz which is four times the frequency of the color subcarrier signal frequency and converted into digital signals. After the required signal processing, the signals are input to the 6-5 converter. And
The 6-5 converter divides each color signal into 6 pixels, averages the 6th pixel of each division and the 1st pixel of the previous division, and outputs the 2nd to 5th pixels in succession. The signal is input to a display such as a PDP or LCD and displayed on the screen.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image size conversion circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of an image size conversion circuit according to the present invention. In the figure, reference numeral 1 denotes a video signal input, which inputs a composite video signal. A Y / C separation unit 2 separates the composite video signal into a luminance signal and a color signal. 3 is an inverse MTX circuit, Y /
Based on the luminance signal and the color signal from the C separation unit 2, R,
The signals of three colors of G and B are processed. Reference numeral 4 is an A / D converter, which converts the signal of each color from the inverse MTX circuit 3 into the frequency 14.3
Sampling is done with 18MHz clock and each is converted into digital signal. A digital processing unit 5 processes each color signal from the A / D conversion unit 4. 6 is 6-5
The conversion unit divides each color signal from the digital processing unit 5 into 6 pixels, and averages the 6th pixel of each division and the 1st pixel of the previous division to generate one pixel. It is output following the second pixel to the fifth pixel. 7 is a display part, PD
The signal from the 6-5 conversion unit 6 is displayed by a display body composed of P or LCD.

Next, the operation of the image size conversion circuit according to the present invention will be described. The composite video signal from the video signal input unit 1 is separated into a luminance signal and a color signal by the Y / C separation unit 2, processed by the inverse MTX circuit 3 into signals of each color of R, G, and B, respectively A / A. Input to the D conversion unit 4. The A / D converter 4 samples at a frequency of 13.318 MHz, which is four times the color subcarrier signal frequency of 3.58 MHz, and converts it into a digital signal. The digitally converted signals of the respective colors are subjected to required processing by the digital processing section 5, and then input to the 6-5 conversion section 6. Then, the input signal is divided into 6 pixels, and the 6th pixel of each division and the 1st pixel of the previous division are averaged to generate one pixel, which is output following the 2nd to 5th pixels. The signal from the 6-5 conversion unit 6 is input to the display unit 7 and displayed on the PDP or LCD.

The 6-5 converter 6 is constructed, for example, as shown in the block diagram of FIG. FIG. 3 shows the 6-5 converter 6
3 is a time chart for explaining the operation of FIG. The signal of each color from the digital processing unit 5 is input to the D terminal of a D-type flip-flop circuit (hereinafter abbreviated as D-FF).
In the 6-5 conversion unit 6, since the signals of each color from the digital processing unit 5 are divided into 6 pixels each and processed, the 6 pixels in the first division are divided into D01, D02, ... D06 and 6 in the second division.
The pixels are represented as D11, D12, ... D16, and the six pixels in the third section are represented as D31, D32 ,.

The signal applied to the D terminal of the D-FF, for example, "D16", is read at the rising edge of clock 1 (hereinafter abbreviated as CLK1), and the next signal, "D21", is input at the next clock input. Is output from the Q terminal until "" is read. The output "D16" of this D-FF is DF
Applied to F. Since the same CLK1 as that of the D-FF is applied to the clock terminal of the D-FF,
A signal "D15" that is one pixel behind the output of the D-FF Q terminal is output to the D-FF Q terminal. Then, the outputs of these D-FF and D-FF are applied to the adder and added to become "D15 + D16", and are halved by the 1/2 multiplier to become "(D15 + D16) / 2". Input to D-FF. After that, the same processing as above is performed at the next clock, and "(D16 + D21) / 2" is input to the D-FF at the next clock.

The clock terminal of the D-FF is "(D16 + D21) / 2", and "(D26 +
CLK2 is applied at the timing of "D31) / 2". As a result, the Q terminal output of the D-FF is "(D16 + D21) / 2", "(D26 + D31) / 2", every 6 clocks.
“(D36 + D41) / 2”, ...

On the other hand, the outputs "D15", "D16", "D21", ... Of the D-FF are applied to the D-FF. The clock terminal of this D-FF has a CLK with no rising edge when "D16" and "D21" are input.
Since 3 is applied, "D15" is continuously output during the periods "D16" and "D21".

The output of the D-FF and the output of the D-FF are applied to the selector circuit, and the select signal (S) causes the output terminal Y to output "D1" from the D-FF.
4 ”and“ D15 ”are output (“ D15 ”is also output during the period corresponding to“ D16 ”), then switch to the D-FF side and output“ (D16 + D21) / 2 ”, then D -FF
It switches to the side and outputs "D22".

The line memory is, for example, a FIFO (fi
rst-in first-out) type memory,
The signal from the selector circuit, by the write clock (inverted WCLK) with no rising in the period of 6 ”, ...
Write as "D15", "(D16 + D21) / 2", "D22", ... And read clock (inverted RCLK)
Read out, applied to the D-FF, processed according to the read clock applied to the clock terminal, and output. As a result, the output of the D-FF, that is, the output of the 6-5 conversion unit 6, is ... "D12", "D13", "D14",
"D15" and "(D16 + D21) / 2", "D22",
As described above, for each section divided into 6 pixels, the second to fifth pixels are output as they are, and the subsequent 6th pixel and the 1st pixel of the next section are averaged to form one pixel. Output. That is, since one pixel is not thinned out at all, a good quality image can be displayed.

[0014]

As described above, according to the image size conversion circuit of the present invention, since the number of pixels is converted without lowering the clock frequency (14.318 MHz) at the time of A / D conversion, the resolution is lowered. In addition, a general-purpose signal processing circuit can be used for the circuits before and after, and when converting the number of pixels, the pixels that should be reduced are interpolated with the average value of adjacent pixels, so there is no complete loss of one pixel. From this point, it is possible to display a good quality image.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of an image size conversion circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a configuration of a 6-5 conversion unit.

FIG. 3 is a time chart for explaining a 6-5 conversion operation.

[Explanation of symbols]

 2 Y / C separation unit 3 Inverse MTX circuit 4 A / D conversion unit 5 Digital processing unit 6 6-5 conversion unit 7 Display unit D-type flip-flop circuit Adder selector circuit Line memory (FIFO type)

Claims (4)

[Claims] 1. A separation unit for separating a video signal into three signals of red, green and blue, and A / A for sampling each color signal from the separation unit at a frequency four times that of a color subcarrier signal and converting it into a digital signal. It is composed of a D conversion unit and a 6-5 conversion unit that divides each color signal from the A / D conversion unit into 6 pixels and converts each to 5 pixels, and displays based on the signal from the 6-5 conversion unit. Image size conversion circuit. 2. The 6-5 conversion unit divides each color signal from the A / D conversion unit into 6 pixels, and averages the 6th pixel of each division and the 1st pixel of the previous division. , Second
The pixel to the fifth pixel are output subsequently.
The described image size conversion circuit. 3. A first D-type flip-flop circuit for processing the signal from the A / D conversion unit with a first clock signal, and a signal from the first D-type flip-flop circuit in the 6-5 conversion unit. Second D processed with first clock signal
Type flip-flop circuit, an adder for adding a signal from the first D-type flip-flop circuit and a signal from the second D-type flip-flop circuit, and a third D-type for processing the signal from the adder with a second clock signal A flip-flop circuit, a fourth D-type flip-flop circuit that processes a signal from the second D-type flip-flop circuit with a third clock signal, a signal from the third D-type flip-flop circuit, and a fourth D-type flip-flop circuit A selector circuit for selecting the signal of # 1 by a required select signal, a line memory for writing the signal from the selector circuit with a required write clock signal and reading with a required read clock signal, and a signal from the line memory for the read clock signal. And a fifth D-type flip-flop circuit processed by Image size conversion circuit Motomeko 1 wherein. 4. The image size conversion circuit according to claim 3, wherein the line memory is a FIFO type memory.