JPH05153426A - Video signal processor - Google Patents

Abstract

PURPOSE:To apply a line interpolation processing without deteriorating the resolution to an intermittent video signal whose video information is missing in the unit of the horizontal scanning period. CONSTITUTION:A video signal DY0 subjected to digital conversion by an A/D converter circuit 11 is written alternately by line memories 12, 13 in response to write enable signals WE1, WE2. Moreover, the video signal DY0 is inputted respectively to three multiplier circuits 14-16 together with video signals DY1, DY2 read from the line memories 12, 13, in which a specific multiplier designated by multiplier designation signals RS1-RS3 is multiplied. Two outputs of the multiplier circuits 14-16 are fetched by a synthesis circuit 17 according to a selective signal CS and the two signals are synthesized to obtain the video signal DY3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for line-interpolating a video signal obtained from a solid-state image pickup device in units of horizontal scanning periods.

[0002]

2. Description of the Related Art The reproduction screen of a general television is 240 pixels vertically and 324 horizontally per field in the case of the NTSC system.
It is composed of pixels, and at least an image sensor corresponding to the number of pixels is required to obtain this screen. However, a solid-state image sensor with a large number of pixels requires high integration, so
There is a problem in that the manufacturing yield cannot be improved and the cost increases, resulting in an increase in the price of the television camera.

Therefore, the applicant of the present application has proposed an image pickup device for enabling the use of a low-resolution solid-state image pickup device having a small number of pixels in Japanese Patent Application No. 63-20458. Figure 8
FIG. 10 is a block diagram showing a configuration of the image pickup device, and FIG. 9 is a timing diagram showing an operation. The frame transfer type CCD solid-state imaging device 1 includes an imaging unit 1I and a storage unit 1S.
And the horizontal transfer unit 1H, the number of pixels in the vertical and horizontal directions of the image pickup unit 1I is omitted to be 1/2 of that of the normal element. For example, in the case of NTSC system,
One field has 120 vertical pixels and 162 horizontal pixels. The solid-state image pickup device 1 is pulse-driven by the transfer clock generation circuit 2, and the image pickup unit 1I and the storage unit 1S are driven.
The vertical transfer clock φ _I , the storage transfer clock φ _S, and the horizontal transfer clock φ _H are supplied to the horizontal transfer unit 1H, respectively. The transfer clock generation circuit 2 supplies the transfer pulses φ _I , φ _S, and φ _H to each part of the solid-state image sensor 1 according to the timing signal created by the timing control circuit 3 based on the vertical scanning signal VD and the horizontal scanning signal HD. To do.

Since the number of pixels in the vertical and horizontal directions of the above-described solid-state image pickup device 1 is 1/2 of the normal number, the information charges are read out from the storage section 1S by a transfer pulse having the same period as the horizontal scanning signal HD. Then, only 1/2 the number of horizontal scanning lines can be obtained, and the television screen cannot be constructed. Therefore, the frequency of the accumulation transfer pulse φ _S and the horizontal transfer pulse φ _H is set to 1/2 of the frequency of the horizontal scanning signal HD. That is, the transfer of the information charges from the storage section 1S to the horizontal transfer section 1H is performed every 2H cycle. Therefore, the video signal Y0 obtained from the solid-state image sensor 1 has a predetermined signal every 1H. The video signal Y0 is an intermittent signal in which only 1H signal exists every 2H, and is input to the interpolation circuit 4 to make it a continuous signal. Interpolation circuit 4
Is 1H by adding (4b) the video signal Y1 and the video signal Y0 which are delayed (4a) by 1H.
The continuous video signal Y2 is output every time.

The video signal Y2 as described above is subjected to processing such as sample hold and amplification in the signal processing circuit 5, becomes a video signal, and is supplied to the television monitor 6. According to the above configuration, every two horizontal scanning lines of the reproduction screen can be obtained with the same signal, and a CCD with a small number of pixels can be adopted in the television camera.

[0006]

In the image pickup apparatus as described above, it is possible to improve the horizontal resolution by interlacing the solid-state image pickup device 1. However, the interpolation circuit 4 as described above is used. The following inconveniences occur in the provided image pickup apparatus. That is, when the subject is imaged,
As shown in 0, in the even field EVEN, A to
The region D is imaged to display A, A to D, and D (solid line) on the reproduction screen, and in the next odd field ODD, the regions a to d are imaged to form a, a to d on the reproduction screen. , D (chain line) are displayed. Therefore, as is apparent from the figure, the positions of the respective areas may be reversed in the subject pair and the reproduction screen. For example, while B is located above b in the subject,
In the reproduction screen, an area where B is located below b is generated. Therefore, although the solid-state imaging device 1 is interlaced, it is not possible to improve the image quality of the reproduction screen.

Therefore, an object of the present invention is to provide an image pickup apparatus capable of obtaining a high quality reproduction screen by using a solid-state image pickup element having a small number of pixels.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that the number of horizontal scanning periods set in the vertical scanning period is greater than the vertical scanning period. For the video signal obtained by reading the video information of one horizontal line at every constant horizontal scanning period from the solid-state image sensor having a small number of pixels, the video component in the horizontal scanning period in which the reading of the video information is stopped is displayed before and after that. In a video signal processing device that interpolates using video components in a scanning period, an A / D conversion circuit that converts a video signal obtained from a solid-state image sensor into digital data, and a plurality of A / D conversion circuits that store the digital data in units of horizontal scanning periods. Line memory and above A / D
A plurality of multiplication circuits for multiplying the digital data from the conversion circuit and the digital data from the line memory by a specific multiplier, respectively, and an addition circuit for selectively extracting and combining two of the outputs of these multiplication circuits, Memory control means for respectively setting a data writing period to the line memory, and arithmetic control means for individually setting the multiplier of the multiplication circuit and designating two outputs to be combined by the addition circuit are provided. It is in.

[0009]

According to the present invention, new video information is created by multiplying the video information output before and after the horizontal scanning period having no video information by a specific coefficient and then adding the new video information. Since the horizontal scanning period in which the image information is not output from the image sensor is interpolated, the signal displaying each horizontal scanning line is faithfully associated with the display position on the reproduction screen. Therefore, it is possible to prevent the display of the reproduction screen from being reversed with respect to the subject.

[0010]

1 is a block diagram of a video signal processing apparatus according to the present invention. The A / D conversion circuit 11 converts the analog-valued video signal Y0 obtained from the solid-state imaging device into a digital-valued video signal DY0, and outputs the digital-valued video signal DY0. Two line memories 1
2 and 13 store the video signal DY0 at each timing for each horizontal scanning period. Also, the video signal Y0 and the video signals DY1, read from the line memories 12 and 13
DY2 is input to each of the multiplication circuits 14-16.
The multipliers 14 to 16 have multipliers of, for example, 1/2, 1 /
4 or 3/4 is selectively set, and each video signal DY0 to DY2 is multiplied by a predetermined multiplier and supplied to the synthesis circuit 17. The synthesizing circuit 17 includes three video signals DT0 to DY.
Two of the two video signals are selected and fetched, the two video signals are combined, and a video signal DY3 is output.

The memory control circuit 18 sets the write enable signals WE1 and WE2 so that the video information of the video signal DY0 is alternately fetched into the two line memories 12 and 13, and supplies the write enable signals WE1 and WE2 to the line memories 12 and 13. Similarly, the arithmetic control circuit 19 causes each of the multiplying circuits 14 to 1 to be arranged every horizontal scanning period.
Designation signals RS1 to RS3 designating a multiplier of 6 are generated, and at the same time, a selection signal CS that selects a signal to be synthesized by the synthesis circuit 17 is generated and supplied to the multiplication circuits 14 to 16 and the synthesis circuit 17, respectively. These memory control circuits 18
The operation control circuit 19 includes a vertical synchronization signal VD and a horizontal synchronization signal HD for setting the drive timing of the solid-state image sensor.
Is input and the write enable signals WE1 and WE2, the designation signals RS1 to RS3, and the selection signal CS are input to the video signal Y0.
Is configured to synchronize with.

2 and 3 are timing charts for explaining the operation of the video signal processing circuit. FIG. 2 shows the write enable signal and the multiplier designation signal, and FIG. 3 shows the video signal. Here, the write enable signals WE1 and WE2 indicate the case where the video signal Y0 includes video information every 1H.
Are synchronized with the horizontal synchronizing signal HD, set the write period in 1H in 4H cycles, and halve each other.
The phase relationship is shifted by the period (2H). Therefore, the video information A, B, C, D, ... Between 1H included in the video signal DY0 every 1H (2H synchronization) is written alternately in the line memories 12 and 13.

[0013] Multiplier specification signal RS1~RS3 have different specified values even field EVEN and odd field ODD, in the even field EVEN, multiplier designation signal RS1 _E specifies a half between 1H in 2H cycle, multiplier The designation signals RS2 _E and RS3 _E both have a phase difference of 2H with each other and designate 1 for 1H at a cycle of 4H and continue 1
Specify 1/2 during H. As a result, as shown in FIG. 3, the video information A, B, C, D, ...
B) / 2, (B + C) / 2, (C + D) / 2, ... Are created, and video information A, B, C, D, ... And video information (A +
A video signal DY3 in which B) / 2, (B + C) / 2, (C + D) / 2, ... Are alternately output is obtained. In the odd field ODD, the multiplier designation signal RS1 _O
Specifies 1/4 for 1H in 2H cycle, and the multiplier designation signal R
Both S2 _O and RS3 _O have a phase difference of 2H and specify 3/4 during 2H at a cycle of 4H and specify ¼ of 1H that follows. These multiplier designation signals RS2 _O and RS3 _O are 3/4
Period designated a is set phase for multiplier designation signal RS1 _O to overlap with the period designated 1/4 multiplier designation signal RS1 _O with overlap period to specify the quarter of one another. Therefore, as shown in FIG. 3, video information (3a +
A video signal DY3 in which b) / 4, (a + 3b) / 4, (3b + c) / 4, ... Is successively output is obtained.

FIG. 4 is a schematic diagram showing a state of scanning lines of a reproduction screen displayed according to the video signal DY3. This figure corresponds to the subject shown in FIG. In the even field EVEN, the original image information A, such as the image information (A + B) / 2 is drawn between the scanning line indicating the image information A and the scanning line indicating the image information B.
Twice as many scanning lines are displayed for B, C, D, .... In the odd field ODD, the video information a,
Video information (3a + b) / 4 created from b, c, d
(A + 3b) / 4, (3b + c) / 4, ... Display twice as many scanning lines as the video information a, b, c, d ,. These video information (3a + b) / 4, (a + 3b)
According to / 4, (3b + c) / 4, ..., the image information a, b, c, d, ... Is corrected by the amount of deviation from the position at which it should be originally displayed. There is no position reversal. That is, the scan lines corresponding to the subject image and the scan lines actually drawn are odd field ODs.
Since D shifts by ½ pitch, the image information of adjacent scanning lines is added by the amount of the shift to obtain new image information and is drawn on the actual scanning line. Therefore, in the even field EVEN and the odd field ODD, the video information corresponding to the actual display position of the scanning line is obtained by calculation, and the display position on the reproduction screen with respect to the subject is not inverted, so that the image quality can be improved. ..

By the way, in the above signal processing, flicker may occur because the process of signal processing is different between the even field and the odd field. For example, in the even field EVEN, video information A, B, C, D, ...
On the other hand, in the odd-numbered field ODD, the image components (3a + b) / 4, (a + 3b) / 4, (3b + c) / which have undergone the processes of multiplication and addition for each H are output.
.. are output, a difference easily occurs between the signal levels due to the influence of a calculation error or the like, and the difference appears as a flicker on the reproduction screen.

Therefore, with respect to flicker caused by the difference in the process of signal processing, it is possible to significantly calculate each image information by assuming the position where each scanning line is shifted by 1/4 pitch. Can be suppressed. For example, as shown in FIG. 5, the video information (A + B) / 2, B, (B + of FIG.
C) / 2, C ... (even field EVEN),
Video information (5
A + 3B) / 8, (A + 7B) / 8, (5B + 3C) /
Each scanning line is displayed by 8, ..., Video information (3a + b)
/ 4, (a + 3b) / 4, (3b + c) / 4, ... (Odd field ODD) image information (7a + b) / 8, (3a + 5b) /
Each scanning line is displayed by 8, (7b + c) / 8, ....

FIG. 6 shows write enable signals WE1 and WE2 and multiplier designating signals RS1 to RS3 when performing signal processing for obtaining such video information, and FIG. 7 shows corresponding video signals DY0 to DY3. Show. At this time, it is not necessary to change the configuration of the signal processing device itself, and the multipliers of the multiplication circuits 14 to 16 are set to 1/8, 3/8, 5/8, 7
You can change it to / 8.

The write enable signals WE1 and WE2 are
2, the line memories 12 and 13 perform the same operation, and the same video signals DY1 and DY2 as those in FIG. 3 are obtained. Here, what is changed with respect to the signal processing shown in FIGS. 2 and 3 is only the multipliers of the multiplication circuits 14 to 16 designated by the multiplier designation signals RS1 to RS3. In the even field EVEN, the multiplier designation signal RS1 _E is 1H in 2H cycles.
3/8 is designated between the two, and multiplier designation signals RS2 _E and RS3 _E
However, 7/8, 5/8, and 1/8 are continuously specified for each 1H in the 4H cycle. In the odd field, the multiplier designating signal RS1 _O designates 1/8 during 1 H in 2 H cycles, and the multiplier designating signals RS2 _O and RS3 _O are 5 / in 4 H periods.
Specify 8/7/8 and 3/8 in succession every 1H. As a result, in the even field EVEN, the video information (5A
+ 3B) / 8, (A + 7B) / 8, (5B + 3C) /
, (B + 7C) / 8, ... Are successively output, and a video signal DY3 is obtained, and in the odd field ODD, video information (7a + b) / 8, (3a + 5b) / 8, (7b +).
A video signal DY3 in which c) / 8, (5b + 3c) / 8, ... Is continuous is obtained.

In the signal processing as described above, since the signal processing steps of the even field EVEN and the odd field ODD are almost the same, the possibility that flicker appears on the reproduced screen is extremely low. In the present embodiment, the case where the video signal including the video information is line-captured every 1H period has been described as an example. However, for the video signal including the video information every 2H period or longer. Line interpolation processing can be performed.

[0020]

According to the present invention, interpolation processing can be performed on an intermittent video signal containing video information after a certain period without causing inversion of the image position during interlace driving. it can. Therefore, even when a solid-state image sensor having a small number of pixels is used, it is possible to shoot without significantly lowering the resolution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video signal processing device of the present invention.

FIG. 2 is a timing chart showing an example of each signal given to the video signal processing device.

FIG. 3 is a timing chart showing an example of a video signal obtained by the video signal processing device.

FIG. 4 is a schematic diagram showing scanning lines displayed on a reproduction screen.

FIG. 5 is a schematic diagram showing scanning lines on a reproduction screen that are assumed to be shifted by ¼ pitch.

FIG. 6 is a timing diagram showing another example of each signal given to the video signal processing device.

FIG. 7 is a timing diagram showing another example of a video signal obtained by the video signal processing device.

FIG. 8 is a block diagram showing a configuration of a conventional imaging device.

FIG. 9 is a timing chart showing the operation of the image pickup apparatus.

FIG. 10 is a schematic diagram showing a subject and scanning lines on the reproduction screen corresponding to the subject.

[Explanation of symbols]

 1 CCD solid-state image sensor 2 transfer clock generation circuit 3 timing control circuit 4 capture circuit 5 video signal processing device 6 TV monitor 11 A / D conversion circuit 12, 13 line memory 14, 15, 16 multiplication circuit 17 synthesis circuit 18 memory control Circuit 19 Arithmetic control circuit

Claims (2)

[Claims] 1. A video signal obtained by reading out video information of one horizontal line for every fixed horizontal scanning period from a solid-state image pickup device having a smaller number of vertical pixels than the number of horizontal scanning periods set in the vertical scanning period. In a video signal processing device that interpolates a video component in a horizontal scanning period in which the reading of video information is stopped using video components in the horizontal scanning periods before and after that, a video signal obtained from a solid-state image sensor is converted into digital data. An A / D conversion circuit, first and second line memories for storing the digital data in units of horizontal scanning periods, digital data from the A / D conversion circuit and the first and second line memories First to third multiplication circuits for multiplying digital data by specific multipliers, and addition for selectively extracting two from outputs of these multiplication circuits and synthesizing the two A circuit, a memory control unit for setting a data writing period to the line memory, and an operation control unit for individually setting a multiplier of the multiplication circuit and designating two outputs to be combined by the addition circuit, A video signal processing device comprising: 2. The first and second line memories alternately store digital data corresponding to video information from the A / D conversion circuit in units of horizontal scanning periods. Video signal processing device.