JPH01261086A - Image pickup device - Google Patents

Abstract

PURPOSE:To attain magnification and interpolation of a picture with only the small number of line memories by controlling a vertical transfer section of a solid-state image pickup element. CONSTITUTION:The image pickup device is provided with an image pickup element drive circuit 2 using a control signal C1 to control the transfer/stop of vertical transfer of a solid-state image pickup element 1, a switch using a control signal C2 so as to share an output signal of the solid-state image pickup element 1 to line memories M1-Mn, e.g., 5-7, and a selector using a control signal C3 to select an output signal of 2 lines in the line memories 5-7. Moreover, multipliers 9, 10 multiplying weighted signals W1, W2 to the output signal respectively, an adder 1 adding output signals of the multipliers 9, 10 and a control signal generating circuit 13 outputting the control signals C1-C3, W1, W2 are provided. Then if the signal stored in the remaining line memories after the selection of the selector 8 is the oldest signal, the vertical transfer of the solid-state image pickup element 1 is applied to output a new 1-line signal. Thus, the magnification processing of the picture is applied by using a less number of the memories 5-7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an imaging device such as a video camera, and more particularly to an electronic zoom function for enlarging a photographed image.

Conventional technology In order to electronically enlarge an image taken with a conventional image sensor, the output signal of the image sensor is once stored in a field memory, only the necessary portions are read out, processed through interpolation, etc., and then output. Was. The configuration of a conventional imaging device of this type is shown in FIG.

In FIG. 8, 101 is an image sensor, 102 is an image sensor 1
01 is a drive circuit, 103 is a process circuit that generates a luminance signal and a color signal from the output of the image sensor 101, 104 is a switch that selects either field memory 105 or 106 according to the field and writes the signal, and 107 is a A memory control circuit that outputs write addresses, read addresses, etc. of field memories 105 and 106, 1
08 is field memory 105.1 according to the field.
06 is a selector that selects one that is not being written and reads the signal; 109 is an interpolation circuit that performs interpolation;
A signal is output to the output terminal 110.

FIG. 9 shows a conceptual diagram of image enlargement processing. It is now assumed that the image sensor 101 outputs an image of 240 lines in one field. A case will be described in which a portion corresponding to 180 lines is enlarged and output as a one-screen image as shown in FIG. 9(a). The magnification in this case is 240÷180=4/3 times.

In order to increase the number of scanning lines from 180 to 240, the interpolation circuit 109 in FIG. 8 performs interpolation processing as shown in FIG. 9(h). That is, in order to generate line (2), lines (2) and (2) are read out from the field memory 105 or 106, multiplied by a weight according to the distance and added, and line (2) is interpolated and output. Other lines■〜■
Similarly, the upper and lower two lines are interpolated and output.

Problems to be Solved by the Invention However, as described above, the conventional imaging device that stores the entire screen of signals in a field memory and then reads out the necessary portions has the problem of requiring a huge amount of memory. had.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an imaging device that can perform image enlargement processing with a small amount of memory without using field memory.

Means for Solving the Problems In order to achieve the above object, an imaging device of the present invention includes a solid-state imaging device including a vertical transfer section having a shift register structure, and a vertical transfer/transfer function of the solid-state imaging device using a control signal C1.
an image sensor drive circuit that performs stop control; and a switch that distributes the output signal SO of the solid-state image sensor to a first line memory M1 to an n-th line memory Mn (n≧3, n is an integer) according to a control signal C2. and the line memories M1 to M
A selector that selects the output signal of m lines (2≦m<n, m is an integer) out of n using a control signal C3, and a weighting signal W1 for each of the output signals 81 to Sm of the selector.
m multipliers that multiply by ~Wm, an adder that adds the m output signals of the multipliers, and the control signals C1, C
2, C3, Wl to Wm, and the remaining line memories M! selected by the selector. If the signal stored in (]≦x≦n, x is an integer) is the oldest signal among the line memories M1 to Mn, vertical transfer of the solid-state image sensor is performed and a new line of signal S is stored. 0new, and the switch selects the line memory Mx and outputs the signal S0new.
It is configured to control writing.

Operation The present invention has the above configuration, and by controlling the vertical transfer section of the solid-state image sensor in the same manner as a conventional field memory,
Image enlargement and interpolation are possible with only a small amount of line memory.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an imaging device according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a solid-state image sensor, which has a vertical transfer section with a shift register structure, such as a CCD type. Reference numeral 2 denotes a drive circuit for the solid-state image sensor 1, which controls transfer and stop of vertical transfer of the solid-state image sensor 1 in accordance with a control signal CI. Further, the control signal C4 is used to sweep out charges from unnecessary scanning lines. 3 is a process circuit that generates a luminance signal, color signal, color difference signal, etc. from the output signal of the solid-state image sensor 1. 4 is the output signal of the process circuit 3, and the control signal C
A switch for distributing line memories 5 to 6 according to 2, 8
is a selector that selects and outputs two line memories according to the control signal C3. 9゜10 is a multiplier that multiplies the output signal of the selector 8 by weight signals Wl and W2, respectively;
The signal on the upper scanning line of the screen is applied to multiplier 9, and the signal on the lower scanning line is applied to multiplier 1O. 11 is a multiplier 9,
This is an adder that adds 100 output signals and outputs the result to an output terminal 12. Reference numeral 13 denotes a control signal generation circuit that supplies control signals and weight signals to each section, and address signals to the line memory.

FIG. 2 shows a block diagram of the control signal generation circuit 13.

Reference numeral 21 is a start address register indicating the position of the first scanning line of the portion of the screen to be enlarged. Here, the scanning line interval of each field is set to 1. The integer part is output as the number of unnecessary scanning line sweep lines 04, and the decimal part is output to the selector 23. A pitch register 22 indicates a value obtained by converting the scanning line interval of the screen after enlargement to the scanning line interval of the original image, and in the case of enlargement, this value becomes 1 or less. A selector 23 outputs an upper initial value during the vertical blanking period, and outputs a lower signal at other times so that the circuit forms a loop. 24 is a latch circuit that latches the input once per line. 25 is an adder that adds the output of the latch 24 and the output of the pitch register 22, outputs a carry signal as C1, and sends a lower signal to the selector 23.
Output to. 26 is a ternary counter which counts C1 as a clock input and outputs the count values as C2 and C3. The output of the latch 24 becomes the weight signal W2 (0≦W2<1), and the result of subtraction by (1-W2) by the subtracter 27 is output as the weight signal W1 (0<W1≦1).

The operation of the imaging apparatus in this embodiment configured as shown in FIG. 9 will be explained with reference to FIG.

Now, as shown in FIG. 9, 473 times enlargement in the vertical direction will be explained. In the pitch register 22 in FIG. 2, a pitch of 0.67 corresponding to the magnification is written. It is assumed that the line memories 5 to 7 respectively store scanning lines ① to ② output from the solid-state image sensor 1. First, the interpolation of the scanning line ■ will be explained. The latch 24 holds the decimal part of the vertical position of the scanning line (2). In order to interpolate a scanning line ■, two scanning lines above and below it, that is, ■
and ■ use the signals. Therefore, the selector 8 works to output the signal from the line memory 6 to the multiplier 9, and the signal from the line memory 7 to the multiplier IO. latch 24
If the value of the decimal part of the vertical address of scanning line ■ held by is 0.33, then
3 outputs 0.67 to Wl and 0.33 to W2, multipliers 9 and 10 multiply the scanning lines ■ and ■ by their respective weights, and adder 11 adds them together to produce the output for scanning line ■. The signal is interpolated and output. Also, at this time, the adder 25 performs addition of the next address, and the output of the latch 24 is 0.
．． The value 0.67 of the pitch register 22 is added to 33.

Here, the sum is 1.00, so the carry signal, that is, CI
is given to the drive circuit 2 as l, and the decimal part 0.00 is written to the latch 24 with the next horizontal pulse HD. When C1 becomes 1, the drive circuit 2 operates to perform vertical transfer of the solid-state image sensor l, and transfers a new scanning line from the solid-state image sensor 1 to
signal is output. On the other hand, the signal of the scanning line (2) stored in the line memory 5 is the oldest among the signals (1) to (2), and is no longer used for interpolation of the subsequent scanning lines (1) to (2). Therefore, the switch 4 selects this line memory 5 and operates to write the signal of the scanning line (2) output from the solid-state image sensor 1. Reading and writing to these line memories can be performed simultaneously. That is, the scanning line (■) is written while reading the scanning lines (■) and (2).

Next, interpolation of scanning line [F] will be explained. Since the content currently held in the latch 24 is 0.00, the signal of the scanning line ■ may be used as is for the scanning line ■. Here, the weight signal Wl given to the multiplier 9 is 12.
The weighting signal W2 given to is O, and the multiplier 9 operates so that the signal of the scanning line (2) is supplied, and the multiplier 1O is supplied with the signal of the scanning line (2). In other words, the selector 8 sends the signal from the line memory 7 to the multiplier 9, and sends the signal from the line memory 5 to the multiplier 10.
Output to. Therefore, the adder 11 outputs the signal of the scanning line (2), that is, the signal of the scanning line (2). Also, at this time, the adder 25 performs addition of the next address, and adds the value 0.67 of the pitch register 22 to the output 0.00 of the latch 24. Here, since the sum is 0°67, the carry signal, that is, C1 becomes O and is given to the drive circuit 2, and the decimal part is 0.
67 is written into the latch 24 with the next horizontal pulse HD.

Since the drive circuit 2 does not perform vertical transfer of the solid-state image sensor 1 when C1 becomes 0, nothing is output from the solid-state image sensor 1. Therefore, both line memories hold their current contents.

Among the above operations, selection of line memory read/write and control of transfer of the solid-state image sensor are summarized as shown in FIG.

Thereafter, by repeating similar operations, vertical expansion can be achieved using only the line memory.

An example of horizontal expansion will be explained. Using the output of the control signal generation circuit shown in FIG. 3 as the read address of the line memories 5 to 7, the output signal of the adder 11 is applied to the horizontal interpolation circuit shown in FIG. 4, and the control signal of FIG. Horizontal weighting signal W3. generated by the generation circuit. Interpolation between two horizontal pixels may be performed using W4.

As described above, in the imaging device of this embodiment, it is possible to realize an imaging device having an image enlargement function, that is, an electronic zoom function, by using only a few line memories without using a frame memory.

Next, an imaging device according to another embodiment of the present invention will be described.

FIG. 5 is a block diagram of the imaging device of this embodiment.

The only difference in FIG. 5 from FIG. 1 is the process processing section, and the other parts are exactly the same. 51・52
is an IH delay line (IHDL) that delays the horizontal scanning period signal; 53 and 54 are selectors that switch the inputs of the IHDLs 51 and 52 according to the control signal C1 output from the control signal generation circuit 13; and 55 is the output signal of the IHDLs 51 and 52. and a signal generation circuit that generates a luminance signal and a color signal using the output signal of the solid-state image sensor l. This 51-5
5 constitutes a process processing section 56.

The operation of the imaging apparatus of this embodiment configured as described above will be described.

This embodiment operates in the same way as the first embodiment.

Then, when the control signal CI controls the solid-state image sensor to transfer, the selectors 53 and 54 output the input side, that is, the next scanning line signal to be written to the IHDLs 51 and 52. Conversely, when the control signal C1 controls to stop the transfer of the solid-state image sensor l, the selector 53
- 54 outputs the B side, that is, the same IHDL signal to be written again. If the process processing unit 56 that operates in this way is replaced with the process circuit 3 in FIG. The same effects as in the first embodiment can also be achieved with a signal processing method, such as a camera, that is equipped with a delay line and generates a luminance signal or a color signal using vertical correlation.

In addition, in these embodiments, the case where the number of line memories is 3 lines and interpolation is performed using 2 lines in the vertical direction has been described, but if these numbers are increased,
It is also possible to perform higher order interpolation. At this time, the number of line memories should be one or more more than the number of scanning lines used for interpolation, and the selection of read/write to the line memory and the control of transfer of the solid-state image sensor should not be performed at the timing shown in Fig. 6. , even if the control signal CI is delayed by one line and shifted by one line as shown in FIG. 7, the effect remains the same.

Further, in the second embodiment, the output of the delay line is written to the same delay line to hold its contents, but the driving of the delay line may be stopped to hold its contents.

Effects of the Invention According to the present invention, even when performing enlargement processing of moving images such as electronic zoom, it can be realized with only a few line memories without using a frame memory, and the memory capacity is significantly reduced. It also reduces power consumption, etc.
Moreover, the configuration is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an imaging device in a first embodiment of the present invention, FIG. 2 is a block diagram of a control signal generation circuit in the same embodiment, and FIG. 3 is a horizontal enlargement control signal generation circuit in the same embodiment. FIG. 4 is a block diagram of the horizontal expansion interpolation circuit in the same embodiment, and FIG. 5 is a block diagram of the second embodiment of the present invention.
6 is a state diagram showing the control operation of the first embodiment, FIG. 7 is a state diagram showing the control operation of the second embodiment, and FIG. 8 is a block diagram of the conventional example. 9 are conceptual diagrams showing the concept of image enlargement processing. l...Solid-state image sensor, 4...Switcher, 5-7...
Line memory, 8... Selector, 9, 10... Multiplier, 11... Adder, 13... Control signal generation circuit. Name of agent: Patent attorney Toshio Nakao and one other person J, 44-
11 Karo Sango Diagram 4■ [phase] O@O■◎

Claims (4)

[Claims] (1) a solid-state image sensor including a vertical transfer section with a shift register structure; an image sensor drive circuit that controls transfer and stop of vertical transfer of the solid-state image sensor using a control signal C1;
The output signal S0 of the solid-state image sensor is transferred from the first line memory M1 to the n-th line memory Mn(n
≧3, n is an integer), a selector that selects the output signal of m lines (2≦m<n, m is an integer) of the line memories M1 to Mn by a control signal C3, and the selector m multipliers for multiplying the output signals S1 to Sm by weighting signals W1 to Wm, respectively; an adder for adding the m output signals of the multipliers; and the control signals C1, C2, C3, W1 to The signal stored in the remaining line memory Mx (1≦x≦n, x is an integer) selected by the selector is the most When the signal is an old signal, the switch is configured to perform vertical transfer of the solid-state image sensor to output a new one-line signal S0new, and to write the signal S0new into the line memory Mx. imaging device. (2) A process circuit that generates a luminance signal or a color signal/color difference signal from the output signal S0 of the solid-state image sensor, and the luminance signal or the color signal/color difference signal is input to a switching device. 1. The imaging device according to 1. (3) When the process circuit is equipped with a delay line and the vertical transfer of the solid-state image sensor is stopped and the signal S0 is not output,
3. The imaging apparatus according to claim 2, wherein the output of the delay line is configured to be inputted to the delay line again. (4) When the process circuit is equipped with a delay line and the vertical transfer of the solid-state image sensor is stopped and the signal S0 is not output,
3. The imaging device according to claim 2, wherein the imaging device is configured to stop driving the delay line and hold the signal.