JP3389385B2 - Video camera - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention
The present invention relates to a video camera capable of shooting. 2. Description of the Related Art The present applicant has disclosed in Japanese Patent Application Laid-Open No. 7-212657.
No., the drive timing of the CCD imager is controlled.
Control enables N times faster shooting than normal
Suggests a video camera. Below, this high-speed shooting method
The expression will be described in comparison with the normal shooting mode. A solid-state image sensor unit (CCD image)
2) The vertical direction 480 as shown in FIG.
, 720 photos in a horizontal direction
Diode 1 and a plurality of vertical transfer CCDs 2 and horizontal two rows
Transfer CCDs 4a and 4b are included. Vertical transfer CCD2
Is driven by a vertical drive circuit 3 and a horizontal transfer CCD 4
a and 4b are driven by the horizontal drive circuit 5. Also,
A drain 6 is arranged in parallel with the horizontal transfer CCDs 4a and 4b.
The drain 6 discharges unnecessary electric charge during high-speed shooting.
Used to sweep out. In other words, the sweep control game
Charge transmitted from the horizontal transfer CCD 4a through
Swept out of Rain 7. The vertical and horizontal drive circuits
Reference numerals 3 and 5 denote output signals from the timing generator 76.
Driven on the basis of the imaging signal. Each of the photoelectric conversion photodiodes 1
Any of R (red), G (green), B (blue)
A color filter 80 composed of the colors is arranged. still,
The arrangement of the color filters is as shown in FIG.
You. [0005] Normal speed shooting mode (normal shooting mode)
Then, such a solid-state imaging device unit is shown in FIG.
Operates according to the field accumulation mode. That is, 1
Once in the field, the charge stored in photodiode 1
After the load is read out by the vertical transfer CCD 2, the vertical transfer C
Into two vertical transfer pulses that are continuously output to CD2
Therefore, once every 1H (horizontal scanning period), two adjacent
The charges for the IN are transferred to the horizontal transfer CCDs 4a and 4b, respectively.
Transferred at the same time. The horizontal transfer CCDs 4a and 4b are used for horizontal transfer CCDs.
Output 1 line of charge per 1H according to clock
I do. That is, from the horizontal transfer CCD 4a, 1, 3, 5,.
..And the output of odd-numbered lines as the output of channel 1
From the horizontal transfer CCD 4b.
... and the output of the even line is the output of the second channel
And output. Note that in FIG.
H pulse is a 1H cycle
Equivalent to horizontal sync pulse, both are timing generators
76. The two-channel CCD output thus obtained is
The power is applied to the signal processing circuit 3 for each channel as shown in FIG.
0a and 30b are input. Here, the signal processing circuit 30
a and 30b both have the same circuit configuration.
Is CDS circuit (correlated double sampling circuit), AGC times
Path, A / D converter and clamp circuit, CD
After noise is removed by S circuit, it is amplified by AGC circuit
Digitized by the A / D converter and clamped
Output after being clamped by the circuit. Output from each signal processing circuit 30a, 30b
Are the contacts 132 of the switches 132 and 232
a and 232a, and the sorting circuit 34
a, 34b, contacts 1 of switches 132, 232
32b and 232b. The switches 132 and 232 are connected to a video camera.
Linked with the 4x speed switch 28 arranged in the cabinet
When the quadruple speed switch 28 is off, the contacts 132
a, 232a, and the quadruple speed switch 28 is turned on.
Is connected to the contacts 132b and 232b
You. Therefore, the quadruple speed switch 28 is output from the switch 132.
In the normal shooting mode in which is turned off, the signal processing circuits 30a and 3a
CCD output of each channel from 0b is output, 4 times
In the high-speed shooting mode with the speed switch 28 on,
Output of CCD output from circuits 34a and 34b
become. Therefore, in the normal photographing mode, the signal processing
The outputs of the paths 30a, 30b
After that, it is input to the interpolation processing circuit 35. This interpolation processing circuit
35 is configured as shown in FIG. That is, the switch 13
Output of CCD4a on the first channel side input through 2
Are D2 and D2 directly or via the 1H delay circuit 47, respectively.
0 is supplied to the selection circuit 48 and passed through the switch 232.
The CCD 4b output of the second channel, which is input to the
And D3 and D1 respectively via the 1H delay circuit 46
Then, it is supplied to the selection circuit 48. Each of the 1H delay circuits 46 and 47
This is a memory that can store CCD output for 1H period.
And a CCD that is delayed by 1H by passing through this circuit.
Output will be obtained. Note that this 1H delay circuit
Writing and reading of signals are performed by the horizontal transfer CCD 4a,
This is executed in synchronization with the horizontal transfer in 4b. The selection circuit 48 includes four adjacent D0 to D3.
Odd field or even field from digital signal for line
3 lines of digital signal depending on the field
Outputs L0, L1, and L2 are selected as odd-numbered filters.
Field, the signals D1, D2 and D3 are selected and the even-numbered fields are selected.
Field, the signals D0, D1, and D2 are selected.
And The three outputs L0, L1, L2 of the selection circuit 48
Are input to the delay circuit 49, respectively.
The nine outputs are input to the delay circuit 50, respectively. Where both late
The extension circuit is equal to the time required for one pixel to be transmitted.
Delay means having a long delay time.
50 outputs are complemented together with the selection circuit 48 outputs L0, L1, and L2.
Is input to the inter-operation circuit 51. Therefore, the interpolation operation circuit 5
1 includes three adjacent lines selected by the selection circuit 48.
Signals for a total of 9 pixels of 3 pixels adjacent to each other are simultaneously input
Is done. In the interpolation operation circuit 51, a color filter
Color filter array is a mosaic arrangement of the three primary colors.
By the way, any one of R, G, B from any pixel
Considering that only the signal of the other two colors can be obtained, the signals of the other two colors
From the surrounding pixels. At this time, CCD
The relationship between the array of pixels on the imager 112 and the selected pixels
FIG. 7 shows the relationship. As mentioned earlier, odd numbers
At the time of the field, the line signals D1, D2 and D3 are selected.
Odd pixels, counting from the left end of the effective pixel.
The raw pattern is as shown in FIG.
The pattern of the even-numbered pixels is as shown in FIG.
On the other hand, in an even field, the lines D0, D1, and D2 are used.
Signal is selected, so the pattern of the odd-numbered pixels is
(D), the pattern of the even-numbered pixels is as shown in (e).
You. (A) is a partial image on the CCD imager 112.
2 schematically shows an array of elements. As is apparent from FIG.
Depending on the signal, the field to be processed is odd or
Either of the even fields or the pixel to be processed is odd
Once the number or even number is determined, the pixel to be processed is
The pixel patterns of 9 pixels at the center are shown in (b) to (e).
The pixel pattern can be determined in advance.
Then, interpolation is performed using any of these pixel signals.
Can be determined in advance. For example, in the case of (b)
The G signal is obtained from the center pixel,
The R signal is output from the upper and lower two pixels in the center column.
The signal of these two pixels is averaged to obtain the R signal
The B signal is obtained from the left and right two pixels in the center row.
Therefore, the signals of these two pixels are averaged to a B signal.
Output. In the case of (c), the R and G signals are
It is obtained by averaging the same color signals of four adjacent pixels. In this way, the interpolation operation circuit 51
The two color signals missing from the pixel to be processed are
By creating from the pixel signals and interpolating, the R,
G and B signals are output. The signal processing circuit 54 converts each image into a predetermined arithmetic expression.
By substituting the elementary color signal levels, the luminance signals Y and
This is to create RY and BY color difference signals.
Indicates that the R, G, and B color signal levels are r, g, and b, respectively.
Y = 0.6g + 0.3b + 0.1r, RY = 0.9r
-0.6g-0.3b, BY = 0.7b-0.6g-
It is calculated by the equation of 0.1r. Calculated in this way
The video signal consisting of the luminance signal and the color difference signals
It is supplied to the recording circuit of the R section and recorded on the magnetic tape. Next, the quadruple speed switch 28 shown in FIG.
When the camera is turned on, that is, in the case of the 4 × high-speed shooting mode,
As shown in FIG. 9 (a), it is formed by CCD output during normal shooting.
Of the screen to be displayed, the upper left 1/4 area shown by diagonal lines, figure
On the CCD of No. 2, the photodiode in the lower left quarter area
The photoelectric output of the card is taken out and used. Further details
Then, in the high-speed shooting mode, as shown in FIG.
The read-out pulse is output once every 1/4 field,
It is supplied to CD2. And the vertical transfer pulse is 1 /
Horizontal blanking every 2H and every 1/4 field
Are output during the scanning period, and unnecessary charges are swept out.
In the same manner, two pulses are set for each 1/2 H and a 1/4 filter is set.
240 are output for each field. Therefore, the horizontal transfer CCDs 4a and 4b have:
One line of charge is transferred every 1 / 2H. Toes
Both horizontal transfer CCDs have the same horizontal
Since it is driven by the transfer clock, the charge in the first half of one line
When the charge of the latter half is still remaining after transferring
The charge of the next line is transferred from the vertical transfer CCD2.
Will be. On the other hand, at that time, the sweep pulse is supplied.
This sweep pulse causes the sweep control gate
7 is opened. Therefore, the charge in the latter half of one line is swept
It is swept out of the drain 6 through the output control gate. One
In short, in the high-speed shooting mode, the power of the first half of each line is
Only the load is output from each of the horizontal transfer CCDs 4a and 4b.
The charges in the latter half of the line are swept out of the drain 6. In this way, the CCD image is quadrupled.
When the speed switch 28 is not operated, the normal shooting mode
Mode, and the quad speed switch 28 is operated.
In this case, the camera operates in the high-speed shooting mode. In the high-speed shooting mode, the switches 132, 2
32 is switched to 132b, 232b side, respectively
Therefore, the rearranging circuits 34a, 34
The output from b is obtained. The rearrangement circuit 34a is configured as shown in FIG.
0, eight memories a1, a2, b1, b
2, c1, c2, d1 and d2, and a memory control circuit 3
6 is included. Each memory is a memory for 1/8 screen.
The eight regions A1, A2, B1, and B shown in FIG.
2, store C1, C2, D1 and D2 signals respectively
I do. That is, memories a1, a2, b1, b2, c1, c
At the time of writing 2, d1 and d2, as shown in FIG.
In response to the write enable signal,
In the field, the memory a1 and a2 are exchanged every 1 / 2H.
Signals are written to each other, and the next 1/4 field
A signal is alternately written to each of b1 and b2 every 1 / 2H
Then, similarly, all memories a1, a2, b1,.
CCD input to b2, c1, c2, d1 and d2
The output is written. At the time of reading, as shown in FIG.
In response to the lead enable signal, the first half
In the field period (first half field), the memories a1,
It is repeatedly read in the order of b1, a2, b2, and the next 1 /
In the two-field period (the latter half field), the memory c1,
The data is repeatedly read in the order of d1, c2, and d2. Ma
The sorting circuit 34b is completely the same as the sorting circuit 34a.
It has a single circuit configuration and is used for CCD output on the second channel side.
The same rearrangement work as described above is performed. Thus, each of the rearranging circuits 34a, 34b
The CCD output of each channel output from the
On the road 35, the same interpolation processing operation as in the normal photographing is executed, and
The above-mentioned predetermined operation is executed by the signal processing circuit 54 in advance.
As a result, the luminance of each pixel and both color difference signals are obtained. here
Then, the obtained luminance and color difference signals are
As a result of the rearrangement work in steps a and b, as shown in FIG.
It becomes a video signal constituting the screen. In this FIG.
4 screens by 4 exposures during the
And display the subject at high speed four times faster than normal
It becomes possible to catch. The above-mentioned high-speed photographing method
In the explanation, the principle is as described above, but the principle
The screens shown in FIGS. 9B and 9C are actually shown in FIG.
(B) and (c). That is, looking at the horizontal direction,
The first half of 1H is effective, and the accumulated charge in the second half is unnecessary charge.
To drain 6 completely and then by the next exposure
The first half of the accumulated charge is valid, and the second half is swept out.
The work will be repeated. In other words, in FIG.
By CCD output A1 and CCD output A2 as above
The screen is described as being located continuously,
During this time, according to the unnecessary charge sweeping pulse shown in FIG.
Needs some time to sweep out all charges in the second half of 1H
It becomes. Therefore, taking this time into account in advance,
Horizontal effective pixels are set slightly shorter than 1 / 2H
There is a need to. Similarly, in the vertical direction, a 1/4 field
During the first half of the scan, the lower left 1 /
4 are recognized as effective charges,
The charge of the pixel will be swept out,
Considering the required period in advance,
Effective pixels are set slightly shorter than the 1/4 field period.
Need to be As described above, the effective pixels are set in the horizontal and vertical directions.
Slightly shorter than 1 / 2H and 1/4 field respectively
As a result, the screen finally obtained is as shown in FIG.
Unnecessary charges are shown at the right and bottom edges of each 1/4 screen as shown.
In a strip corresponding to the blanking period for sweeping away
Bras with various colors that may appear regardless of image content
An unclear area occurs and the screen becomes very unsightly. According to the present invention, there is provided a high-speed photographing mode.
Image composed of effective charges in the 1 / N screen
Image is enlarged by electronic zoom to the size of 1 / N screen
Is set to compensate for the sweep period of the reactive charge.
Occurs at the end of the 1 / N screen during the blanking period
It is characterized in that a blanking area is removed. Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
An example will be described. FIG. 1 is a block diagram of the apparatus of the present embodiment.
The difference from the conventional example shown in FIG.
A zoom processing circuit 61 is added after the logic circuit 54.
It is the only point. FIG. 14C shows the zoom processing circuit 61.
Each of the four regions set by dividing into four shown in FIG.
Predetermined in the right and downward directions with one point at the upper left corner of
Enlarge by performing electronic zoom at the zoom magnification of
The blanking area was removed for each of
An operation for creating a screen as shown in (c) is executed. Therefore, the zoom processing circuit 61
This will be described in detail. FIG. 13 shows the zoom processing circuit in detail.
FIG. That is, the zoom processing circuit 61
The memory circuit 81 and the
A write control circuit 82 for controlling writing of a video signal;
Read designated line designated by the coefficient setting circuit 90
The video signal on the nth line indicated by the signal
Read from the memory circuit 81 to the output line 100a.
Sometimes, the video signal of the (n + 1) th line adjacent to this is
A read control circuit 83 for reading to the output line 100b;
The coefficient (1-K) is added to the video signal of the nth line of 100a.
Multiplier 84 for multiplication and readout of output line 100b
Multiply the obtained video signal of the (n + 1) th line by the coefficient K
Multiplier 85 and the outputs of these multipliers are added.
Adder 86 and coefficients for setting the coefficients of (1-K) and K
The setting circuit 90 and one line of the output of the adder 86 are stored.
And a line memory circuit 87 connected to this line memory circuit.
A write control circuit 88 for controlling signal writing;
Line based on readout pixel designation signal from setting circuit 94
One line of video signal stored in the memory circuit 87
The m-th and (m +
1) The video signal output line 110 of the adjacent two pixels
a, a read system for executing simultaneous read to 110b
Control circuit 89 and the m-th image output to the output line 110a.
Multiplication for multiplying a raw video signal by a coefficient of (1-L)
Unit 91 and the (m + 1) th output to output line 110b
Multiplier 9 for multiplying the video signal of the pixel by the coefficient of L
2 and an adder 93 for adding the outputs of both multipliers 91 and 92
And a coefficient setting circuit 9 for setting coefficients of (1-L) and L
And 4. Further, the coefficient setting circuit 90 is shown in FIG.
It has such a structure. That is, the selected zoom ratio Z
Register 20 that holds the reciprocal value of
Register 21 to hold as initial value and screen vertically
When creating the first line of the upper and lower half when dividing into two
Temporarily switch to the register side to select the initial value,
Is switched to the register 20 side when the line of
And selector 22 for selecting the value of / Z.
The selected value is used as one input and the addition output is fed.
Back and add both inputs as the other input, then add
The value after the decimal point of the result is output as a FLOOR output
An adder 23 to be supplied to an adder 24;
Which outputs the value after the decimal point of the addition output of
The setting circuit 25 subtracts this coefficient K from 1 (1−
K) and a FLOOR output to one of
The output from a reference value setting circuit 27 described later is used as the input.
Adder 24, which is an input of, and a timing generator 7
Reset by V pulse from 6 and count H pulse
The pixel currently being created by the zoom process
Output a count value indicating whether the line
Under preparation from the counter 28 and the count value of this V counter
Of the pixel in the vertical direction is the upper half as shown in FIG.
, That is, H (high) in the regions R1 and R2.
The region identification signal of the level is also transmitted to the lower half region, that is, the region.
In the region R3 or R4, the L (low) level
An area identification circuit 29 for outputting an identification signal;
While the signal is at the H level, the first vertical
Output the value corresponding to the
It comprises a quasi-value setting circuit 27. Here, in each field, the zoom processing is performed.
The video signal input to the logic circuit 61 is composed of 240 lines.
Therefore, when creating the regions R1 and R2, 1 to 120
Is created, and when creating the regions R3 and R4,
Lines 121 to 240 are created. Therefore,
The reference value for the regions R1 and R2 is 1, and the reference value for the regions R3 and R4
Is set to 121. Similarly, the coefficient setting circuit 94 is shown in FIG.
Has basically the same form as the coefficient setting circuit 90
You. That is, a level holding the reciprocal value of the selected zoom ratio Z.
Hold the register 40 and the origin of the enlargement work as initial values
When the screen is divided into two in the horizontal direction, the right
Register 41 temporarily when the first pixel of the left half is created.
Side to select the initial value, and when creating other pixels
Switch to the register 40 side to select the value of 1 / Z
The value selected by the selector 42 and the selector 42
Input and feed back the added output and input to the other
Then, both inputs are added and output, and the added output
Subsequent adder 4 outputs the value after the decimal point as FLOOR output
4 and an addition output from the adder 43
Setting circuit 4 for outputting the value after the decimal point as a coefficient L
5 and the coefficient L is subtracted from 1 to calculate (1-L).
Subtractor 46 and the FLOOR output as one input,
The output from the reference value setting circuit 47 is used as the other input.
The adder 44 and the H signal from the timing generator 76
Reset and count the horizontal transfer clock.
The horizontal direction of the pixel being created by the current zoom process
An H counter 48 that outputs the position of the counter as a count value;
Based on the count value of the H counter, as shown in FIG.
The area where the horizontal position of the pixel being formed is the left half, that is, the area
In the case of R1 and R3, the H-level area identification signal is
In addition, when in the right half, that is, in the region of the regions R2 and R4,
Is a region identification circuit 49 that outputs an L-level identification signal,
While this area identification signal is at the H level, the horizontal
The value corresponding to the first pixel in the horizontal direction as the horizontal reference value
It comprises a reference value setting circuit 47 for outputting. Here, in each field, the zoom processing is performed.
The video signal input to the logical circuit 61 is 72
Since the number of pixels is zero, the regions R1 and R3
At the time of formation, 1 to 360 pixels are created, and the region R2,
When creating R4, 361-720 lines were created.
It is. Therefore, the reference value of the regions R1 and R3 is 1, and the region R
The reference values of 2 and R4 are set to 361. Next, the zoom processing circuit configured as described above will be described.
Removal of blanking area due to enlargement work on road
explain. Here, in each of the four divided areas,
The scanning area is longer in the horizontal direction than in the vertical direction.
Direction blanking area is the horizontal line in each area.
Approximately 10% to 20% of length, 1.25 zoom magnification
Then, the blanking period can be sufficiently removed.
Therefore, a zoom processing operation at a zoom magnification of Z = 1.25 is performed.
Explain the expansion work by the work. The video signal input from the signal processing circuit 54
The signal is written for each pixel by the write control in the write control circuit 82.
The data is written to the field memory circuit 81. Thus 1
Read when writing of video signal for field is completed
Is started, the field memory circuit 8
When reading from 1, select
The selector 22 selects an initial value, and the initial output of the adder is 0.
And the first addition ends. The result of this addition
The first FLOOR output is 0. First, first
Are created, the region identification circuit 29
Signal becomes H level and the reference value is set to 1.
As a result, the output of the adder 24 becomes 1, and the added output becomes
A read line designation signal that designates a read line
And supplied to the read control circuit 83. The read control circuit 83 receives the instruction signal
The video signal of the first line corresponding to the value
0a, and at the same time,
The video signal of the second line is output to the output line 100b at the same time.
Power. As described above, the coefficient K is 0, and (1-
K) is 1, so the first line from the multiplier 84 is
The output is output as is, but the output from the multiplier 85
Cannot be obtained, and the output of the adder 86 is
The video signal is output as shown in FIG.
The signal of the first line after program processing is expanded in the vertical direction.
Will not be. Next, when creating the second line, the area
Since the identification signal still maintains the H level, the reference value
1 is output from the setting circuit 27 and simultaneously the selector 22
Is the value of 1 / Z on the register 20 side, that is, 1 / 1.25 (=
0.8) and the result of the addition in the adder 23 is 0 + 0.
8 = 0.8, FLOOR output = 0, K = 0.8,
(1−K) = 0.2, and the read line designation signal is
1 and one line is output line 100a, 100b.
The video signals of the first and second lines are read out,
At 84 and 85, the signal of the first line is multiplied by 0.2, respectively.
After the signal of the second line is multiplied by 0.8, the adder 86
Will be added. Here, as shown in FIG.
The second line is the first and second lines of the original line
Interpolation from both lines at a distance of 4: 1 from each
Equivalent to output. When the third line is further created, the area
Since the identification signal still maintains the H level, the reference value
The setting circuit 27 outputs 1 and the selector 22 outputs 1 /
The value of Z is selected, and the addition result in the adder 23 is 0.8+
0.8 = 1.6, FLOOR output = 1, K = 0.
6, (1-K) = 0.4, and the read line designation signal
Since the signal indicates 2, the output lines 100a and 100b
The video signals on the second and third lines are read out,
The second line is multiplied by 0.4 by the calculators 84 and 85, and 3 lines
The signal of the second signal is multiplied by 0.6 and then added by the adder 23.
Will be. Here, as shown in FIG.
From the second and third lines of the original line
Equivalent to interpolation output from both lines at a distance of 3: 2
I do. By repeating such an operation, 1
Upper half of all lines in the field, ie 1-120
The line expansion is completed. Then, the point of creation of the 121st line is reached
Then, the area identification signal is
Goes to the L level, and the output of the reference value setting circuit changes to 121.
And the selector 22 switches to the register 21 side.
To select an initial value of 0, and at the same time, the adder 22 is reset.
Then, the addition result becomes 0, the FLOOR output becomes 0, and K =
0, (1-K) = 1, and the read line designation signal is
121 and a signal from the field memory circuit 81
Lines 121 and 122 in stages 100a and 100b, respectively
Is read out, and the adder 23 outputs 121 video signals.
Only the in-th signal is output, and 121 lines are output.
When creating the second line, the original 121st line signal is
Used, line 121 is vertical as well as line 1.
It will not be expanded in the direction. When the 122nd line is created, a reference value is set.
The output of the circuit 27 is maintained at 121, and the selector 22
Switch to select 1 / Z again, and adder
The result is 0.8, the FLOOR output is 0, K = 0.
2, (1-K) = 0.8, and 121 and 122 la
Interpolation by both lines at a distance of 4: 1 from the in
The output forms the 122nd line. Less than
The same operation is repeated up to the lowermost line. From the above, as shown in FIG.
The video signal of 1 to 120 lines, which is the upper half of
With the first line as the origin, the original
Created by enlarging the video signal by a factor of 1.25,
Video signal of the lower half, 121-240 lines
Is the original 121-240 lane with the 121st line as the origin.
Video signal up to 1.25x down
Created by The video signal thus expanded in the vertical direction
Are sequentially line memos controlled by the write control circuit 88.
The data is written to the re-circuit 87, and then the reading is started.
However, reading from this line memory circuit 87
In this case, before the reading is started, the selector 42 sets the initial value.
Select and add to the initial output of the adder 43, 0, first
Is terminated. The result of this addition is the first FLOO
The R output is 0, the coefficient L = 0, and (1-L) = 1. Ma
Since the first pixel in the horizontal direction is created first,
The identification signal from the area identification circuit 49 becomes H level,
By setting the reference value to 1, the adder output becomes 1.
This addition output indicates the readout image that specifies the readout pixel.
The read control circuit 89 is supplied as an element designation signal. The read control circuit 89 supplies the instruction signal
The video signal of the first pixel corresponding to the value
a and the next pixel of this pixel, ie, 2 pixels
The video signals of the eyes are simultaneously output to the output line 110b. As described above, the coefficient L is 0 and (1-
Since L) is 1, the output of the first pixel is output from the multiplier 91.
Is output as it is, but the output from the multiplier 92 is not obtained.
The output of the adder 93 is the pixel of the first pixel.
The video signal is output as is and the first pixel after zoom processing
Will not be expanded at all in the horizontal direction. Next, when creating the second pixel, the area
Since the other signal still maintains the H level, the reference value is set.
The constant circuit 47 outputs 1 and at the same time the selector 42
The value of 1 / Z on the register 40 side, that is, 1 / 1.25 (=
0.8) and the result of the addition in the adder 43 is 0 + 0.
8 = 0.8, FLOOR output = 0, L = 0.8,
(1−L) = 0.2, and the read pixel designation signal is 1
And output lines 110a and 110b each have one pixel.
The video signal of the first and second pixels is read out, and the multiplier 91,
At 92, the signal of the first pixel is multiplied by 0.2 and the signal of the second pixel is multiplied by 0.2.
No. is multiplied by 0.8 and added by adder 93
become. Here, the second pixel is the first pixel of the original line.
And both images at a distance of 4: 1 from each of the second pixels
It corresponds to the interpolation output from the element. When the third pixel is further created, the region identification
Since the other signal still maintains the H level, the reference value is set.
The constant circuit 47 outputs 1 and the selector 42 outputs 1 / Z
And the result of the addition in the adder 43 is 0.8 + 0.
8 = 1.6, FLOOR output = 1, L = 0.6,
(1-L) = 0.4, and the finger of the readout pixel designation signal
Since the number of pixels shown is 2, the output lines 110a and 110b
Simultaneously read the video signals of the second and third pixels respectively.
And the second pixel is multiplied by 0.4 by the multipliers 91 and 92.
The signal of the third pixel is multiplied by 0.6,
Will be added. Here, the third pixel is
A distance of 3: 2 from each of the second and third pixels
Corresponds to the interpolation output from both pixels. By repeating such an operation, 1
The left half of all pixels of one line in the field, that is, 1
The creation of up to 360 pixels is completed. Then, the point of creation of the 361st pixel is reached.
And the region identification signal is assuming that we moved to the creation of the right half of the screen
The level shifts to the L level, and the output of the reference value setting circuit 47 becomes 361.
Changed, selector 42 switches back to register 41
Instead, the initial value of 0 is selected, and at the same time, the adder 42 is reset.
And the addition result becomes 0, the FLOOR output becomes 0,
L = 0, (1-L) = 1, and the read-out pixel designation signal
Indicates 361, and a signal stage is output from the line memory circuit 87.
110a, 110b video of 361 and 362 pixels
The signal is read out and the adder 93 outputs the signal of the 361st pixel.
Is output only when the 361st pixel is created.
The original signal of the 361 pixel is used as it is
The 361st pixel is not enlarged in the vertical direction as well as the bare pixels
Will be. When the 362nd pixel is created, the reference value is set
The output of the path 47 is maintained at 361, and the selector 40
/ Z is selected, and the addition of the adder 43 is performed.
The result is 0.8, the carry output is 0, L = 0.8,
(1-L) = 0.2, and from 361 and 362 pixels
By interpolation output by both pixels at a distance of 4: 1
The 362nd pixel is configured. Below right pixel
Until the same operation is repeated. From the above, the left half of the screen, 1 to
The video signal up to 360 pixels starts from the first pixel
The original video signal of 1 to 360 pixels is expanded 1.25 times.
It is created by exaggeration, and the right half 361-72
For the video signal up to 0 pixel, the origin is at line 361
The original video signal of 361 to 720 pixels is
It is created by magnifying 25 times. The output from the zoom processing circuit 61 is
The video signal is P1 for each of the regions R1 to R4.
From 倍 P4 to the origin, expand 1.25 times downward and to the right
The blanking area is removed as shown in FIG.
The left high-speed shooting screen is obtained. In the above embodiment, the zoom magnification is set to 1.2.
Although the description has been made with setting to 5, it is not limited to this.
And the lowest magnification within the range that can eliminate the blanking area
preferable. In all of the above-described embodiments, every field
Read out the charge of all pixels at
Interpolation of missing color signals on odd lines in odd fields
By using signals for adjacent even lines
Interpolation and conversely, even lines are missing in even fields
Interpolation of color signals is complemented by using signals for adjacent odd lines.
A high-resolution video signal.
The so-called dual-channel all-pixel readout method C
The CD imager has been described as an example.
It is particularly limited to this method if it can realize
For example, Japanese Patent Application Laid-Open No. 7-212657
Odd and even fields per field as also disclosed
One channel that outputs the signal of only one of the lines
Use a CCD imager and replace the primary color filters.
Instead, a more general complementary color filter may be used.
Needless to say. In the above embodiment, the high-speed shooting mode
Specifically, quadruple speed shooting was described as an example,
The present invention is not limited to this,
As disclosed in Japanese Patent Application Publication No. 57-57, the half-feel
Once the stored charge of the photodiode is read out.
Of these charges, only the lower half of the CCD imager is effective
It is also useful when shooting at 2x speed where the screen is divided into two and displayed.
When shooting at 2x speed, the blanking area is 2
Since it occurs only at each lower end of the split screen, the effective pixel
There is no need to enlarge the image due to charges in the horizontal direction. In the above embodiment, the zoom processing circuit
Performed on video signals consisting of luminance and color difference signals
However, the present invention is not limited to this.
It is also possible to perform the same processing at the color signal stage within
You. As described above, according to the present invention, when shooting at high speed
The blanking area that appears on the screen
Larger removal from the screen makes the screen easier to see.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall block diagram of an embodiment of the present invention. FIG. 2 is an explanatory diagram of a CCD imager according to an embodiment of the present invention and a conventional example. FIG. 3 is an explanatory diagram of a color filter according to an embodiment of the present invention and a conventional example. FIG. 4 is an explanatory diagram of an operation of a CCD imager in a normal photographing mode according to an embodiment of the present invention and a conventional example. FIG. 5 is an overall block diagram of a conventional example. FIG. 6 shows an interpolation processing circuit 3 according to an embodiment of the present invention and a conventional example.
It is a principal part block diagram of No. 5. FIG. 7 is an explanatory diagram of the interpolation processing operation of FIG. 6; FIG. 8 is a diagram illustrating the operation of the CCD imager in a high-speed shooting mode according to an embodiment of the present invention and a conventional example. FIG. 9 is an explanatory diagram of a screen based on signals of respective units according to an embodiment of the present invention and a conventional example. FIG. 10 is a main block diagram of a rearrangement circuit according to one embodiment of the present invention and a conventional example. FIG. 11 is an operation explanatory diagram of the rearrangement circuit of FIG. 10; 12 is an operation explanatory diagram of the rearrangement circuit of FIG. 10; FIG. 13 is a main block diagram of the zoom processing circuit of FIG. 1; FIG. 14 is an explanatory diagram of a blanking area in a high-speed shooting mode. FIG. 15 is a block diagram of a main part of a coefficient setting circuit 90 of FIG. 13; FIG. 16 is an explanatory diagram of an area identification signal according to one embodiment of the present invention. FIG. 17 is a main part block diagram of a coefficient setting circuit 94 in FIG. 13; FIG. 18 is a diagram illustrating a vertical zoom operation of the zoom processing circuit according to one embodiment of the present invention. [Description of Signs] 112 CCD imager 28 4 × speed switch 61 Zoom processing circuit

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Claims (1)

(57) [Claims 1] A CCD imager having a plurality of photoelectric conversion elements, and in a normal shooting mode, a charge stored in a plurality of photoelectric conversion elements is read out once in one field period to provide a high-speed shooting mode. In the above, the electric charge accumulated in an element in a specific area in the photoelectric conversion element is read out N times (N is an integer of 2 or more) as an effective charge in a field other than the specific area. The accumulated charge is regarded as an ineffective charge of 1
CCD to discharge to drain N times during field period
Driving means for driving an imager; and in the high-speed shooting mode, an intersection of one end in the horizontal direction and one end in the vertical direction of each of the images formed by the effective charges in the 1 / N screen is set as the origin of the zoom processing. / N digital zoom processing is performed on each of the images constituted by the effective charges in the screen at a predetermined magnification to remove blanking regions existing at the other end in the horizontal direction and the other end in the vertical direction. Video camera equipped.