WO2017086218A1 - Camera control device and television camera - Google Patents

Camera control device and television camera Download PDF

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Publication number
WO2017086218A1
WO2017086218A1 PCT/JP2016/083208 JP2016083208W WO2017086218A1 WO 2017086218 A1 WO2017086218 A1 WO 2017086218A1 JP 2016083208 W JP2016083208 W JP 2016083208W WO 2017086218 A1 WO2017086218 A1 WO 2017086218A1
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unit
video signal
converter
frames
camera control
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PCT/JP2016/083208
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French (fr)
Japanese (ja)
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昭宏 加藤
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株式会社日立国際電気
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

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  • the present invention relates to a camera control device and a television camera.
  • Patent Document 1 discloses an invention of a camera system capable of obtaining a video signal of 24 frames per second while using a camera operating at a frame rate of 60 frames per second.
  • An object of the present invention is to simultaneously generate a 24K 4K video signal and a 24 HD video signal at the same time from a video signal of a dual green television camera operating at 60 frames per second.
  • the camera control apparatus of the present invention has a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel serial conversion unit.
  • the 24P converter unit outputs an HD video signal of 24 frames per second, and performs pixel interpolation.
  • the unit generates and outputs a 4K video signal of 24 frames per second from the output of the 24P converter unit.
  • the camera control device of the present invention is the above-described camera control device, further including a cross converter unit, which generates a 720 pixel video signal of 60 frames per second from the output of the buffer memory unit. It is characterized by outputting.
  • the camera control device of the present invention is the camera control device described above, and further includes a PI converter unit and a down-converter unit, and the PI converter unit performs vertical scanning of 60 frames per second from the output of the buffer memory unit.
  • a video signal of 1080 pixels is generated and output, and the down converter unit generates and outputs a video signal of 480 pixels of interlaced scanning at 60 frames per second from the output of the PI converter unit.
  • the television camera of the present invention includes a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel / serial conversion unit, and the 24P converter unit outputs an HD video signal of 24 frames per second
  • the pixel interpolation unit includes a camera control unit that generates and outputs a 24K 4K video signal from the output of the 24P converter unit, and the camera control unit performs the first predetermined number of frames of the 60p video. It is characterized by comprising a frame extracting means for making a 24p video by sequentially repeating the frames for every predetermined number of frames.
  • the television camera of the present invention includes a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel / serial conversion unit, and the 24P converter unit outputs an HD video signal of 24 frames per second
  • the pixel interpolation unit includes camera control means for generating and outputting 24 frames per second of 4K video signals from the output of the 24P converter unit, and from the 60p frame, two first frames, the next three first frames, the next The 24p video is output by repeatedly pulling down sequentially such as the first two frames, the next three first frames, and so on.
  • FIG. 1 is a block diagram of a camera system including a camera control device according to an embodiment of the present invention. It is a block diagram of the camera control apparatus which concerns on one Example of this invention. 4 is a timing chart in units of frames of the camera control device according to the embodiment of the present invention. 4 is a timing chart for each line of the camera control device according to the embodiment of the present invention.
  • FIG. 1 is a block diagram of a camera system including a camera control device according to an embodiment of the present invention.
  • an imaging apparatus 100 and a camera control unit (Camera Control Unit) 200 are connected by an optical fiber cable 300.
  • the connection between the imaging device 100 and the camera control device 200 is not limited to an optical fiber cable.
  • the imaging apparatus 100 includes a color separation optical system 112, a first green (G1, Green1) imaging element 111G1, a second green (G2, Green2) imaging element 111G2, a red (R, Red) imaging element 111R, and a blue (B, Blue).
  • a color separation optical system 112 a first green (G1, Green1) imaging element 111G1, a second green (G2, Green2) imaging element 111G2, a red (R, Red) imaging element 111R, and a blue (B, Blue).
  • An image sensor 111B, a video signal processor 113, an image sensor driver 114, and a CPU (Central Processing Unit) 115 are configured.
  • incident light 102 is imaged by a lens 101 and color-separated for four plates by a color separation optical system 112, and a first green (G1) imaging element 111G1 and a second green (G2) imaging element 111G2 It is photoelectrically converted by the red (R) image sensor 111R and the blue (B) image sensor 111B, subjected to various signal processing by the video signal processing unit 113, and HD / 60Px2 (horizontal 1920 ⁇ vertical 1080 pixels, 60 Progressive, two outputs) Output a signal.
  • the image pickup apparatus 100 operates an image pickup device having an effective number of pixels of horizontal 1920 ⁇ vertical 1080 using four pieces of red, green 1, green 2 and blue at 60 frames per second, and parallel-serial conversion of the obtained video signal Then, the data is transmitted to the camera control unit (CCU) 200 via the optical fiber cable 300.
  • CCU camera control unit
  • the camera control apparatus 200 inputs HD / 60Px2 and outputs 4K / 24p, HD / 24p, HD / 60p, 720 / 60p, HD / 60i (interlace or interlaced scan), and 480 / 60i signals simultaneously.
  • FIG. 2 is a block diagram of a camera control apparatus according to an embodiment of the present invention.
  • the camera control apparatus 200 includes an S / P (serial / parallel conversion unit) unit 201, a buffer memory unit 202, a 24P converter unit 203, a frame memory unit 204, a pixel interpolation unit 205, a cross converter unit 206, a PI converter ( Progressive-Interlace conversion unit) 207, down converter 208, and P / S (parallel serial conversion units) 209-1 to 209-6.
  • the frame memory 204 is, for example, a DDR2 (Double-Data-Rate2) DRAM (Dynamic Random Access Memory).
  • the camera control device 200 receives HD / 60Px2, converts it into a 20-bit parallel video signal by the S / P unit 201, and writes it into the buffer memory unit 202.
  • the 24P converter 203 converts the video from 60p to 24p while buffering the video in units of frames using the frame memory unit 204.
  • FIG. 3 is a timing chart for each frame of the camera control apparatus according to the embodiment of the present invention.
  • the frame memory 204 unit writes all the frames of the 60p video, and reads (5n) frames and (5n + 2) frames with a delay of 2 frames at the time of reading (n is a positive integer). This is to extract a frame to make a 24p video from a 60p video, and from the 60p frame, two first frames, next three first frames, next two first frames, next three By sequentially pulling down the first frame, etc., 24p video is obtained.
  • the first two frames (that is, two frames of 0 and 1) of the 60p video in FIG. 3 play a role of a buffer for stabilizing and giving a margin in the pull-down described above.
  • FIG. 4 is a timing chart for each line of the camera control device according to the embodiment of the present invention.
  • the frame memory unit 204 writes all lines line by line at the time of writing. At the time of 60p reading, the upper half and the lower half of the screen are alternately read for each line.
  • the upper half of 4K / 24p signal at (5n) line the odd number of 2K / 24p signal at (5n + 1) line
  • the lower half of 4K / 24p signal at (5n + 2) line and (5n + 3) line Read 2K / 24p of even lines.
  • the bandwidth required for 4K / 60p reading and the bandwidth required for simultaneously reading 4K / 24p and 2K / 24p are the same, so 24p reading is performed at the 5mth (m is an integer of 1 or more) of 60p reading. It is possible to switch between 60p reading and 24p reading according to the purpose of photographing.
  • the frame memory unit 204 performs frame readout for extracting 24p video from 60p video, so that the 24p video output can be performed with the 60p memory without increasing the dedicated memory for 24p. Can respond.
  • the output 4K / 24p (or 60p) signal of the 24P converter unit 203 is converted from a 2K red / green 1 / green 2 / blue signal to a horizontal / vertical double 4K red / green / A blue signal is generated by interpolation from surrounding pixels.
  • the P / S unit 209-1 converts the signal into an SDI (Serial Digital Interface) signal and outputs it as a 4K / 24p (24K frame 4K video signal) signal.
  • SDI Serial Digital Interface
  • HD / 24p (24 video images per second) is directly converted from a parallel signal to a serial signal by the P / S unit 209-2 from the 24P converter unit 6203 and output.
  • the input signal of the 24P converter unit 203 can also be used as an HD / 60p (60 frames per second HD video signal) signal.
  • 720 / 60p vertical 720 pixel video signal at 60 frames per second
  • HD / 60i vertical 1080 pixel video signal at 60 frames per second
  • 480 / 60i (vertical scanning 480 at 60 frames per second)
  • the camera control apparatus can simultaneously generate a 24K frame 4K video signal and a 24 frame HD video signal from a video signal of a dual green television camera operating at 60 frames per second. It is also possible to switch to a 4K video signal of 60 frames per second.
  • Imaging device 101: lens, 102: incident light, 111G1: G1 imaging device, 111G2: G2 imaging device, 111R: R imaging device, 111B: B imaging device, 112: color separation optical system, 113: video signal processing 114: Image sensor driving unit 115: CPU unit 200: Camera control unit 201: S / P unit 202: Buffer memory unit 203: 24P converter unit 204: Frame memory unit 205: Pixel interpolation unit 206: Cross converter section, 207: PI converter section, 208: Down converter section, 209-1 to 209-6: P / S section, 300: Optical fiber cable.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Devices (AREA)
  • Television Systems (AREA)

Abstract

The purpose of the present invention is to generate a 24-frames-per-second 4K video signal and a 24-frames-per-second HD video signal at the same time from a video signal from a dual-green system television camera operating at 60 frames per second. This camera control device is characterized by having a serial-to-parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel-to-serial conversion unit, the 24P converter unit outputting a 24-frames-per-second HD video signal, the pixel interpolation unit generating a 24-frames-per-second 4K video signal from the output of the 24P converter unit and outputting the generated 4K video signal.

Description

カメラ制御装置およびテレビジョンカメラCamera control device and television camera
　本発明は、カメラ制御装置およびテレビジョンカメラに関するものである。 The present invention relates to a camera control device and a television camera.
　近年、従来のＨＤ（High　Definition、水平１９２０ｘ垂直１０８０）の４倍の画素数（水平３８４０ｘ垂直２１６０）の４Ｋテレビジョンカメラが注目を浴びている。その用途はフレーム周波数６０ｐ（progressive）で撮影するスポーツ中継等だけでなく、２４ｐで撮影する映画やドラマ等多岐に渡るが、４Ｋカメラはまだまだ高価なこともあり、６０ｐと２４ｐのカメラを別々に購入するのではなく、一台のカメラで切り替えて使用できることが望ましい。
　従来、６０ｐと２４ｐを同じシステムで切り替えて運用させる場合、テレビジョンカメラの撮像素子を６０ｐと２４ｐを切り替えることから、テレビジョンカメラおよびカメラ制御装置にそれらの走査モードに対応する回路を全て持たせる必要があった。 In recent years, a 4K television camera having four times the number of pixels (horizontal 3840 × vertical 2160) of HD (High Definition, horizontal 1920 × vertical 1080) has attracted attention. Its use is not limited to sports broadcasts that shoot at a frame frequency of 60p (progressive), but also a wide range of movies and dramas shot at 24p, but 4K cameras are still expensive, and 60p and 24p cameras can be separated separately. Instead of purchasing, it is desirable to be able to switch and use with a single camera.
Conventionally, when 60p and 24p are switched and operated in the same system, the television camera imaging device is switched between 60p and 24p, so that the television camera and the camera control device have all circuits corresponding to their scanning modes. There was a need.
　先行技術文献としては、例えば、特許文献１に、毎秒６０フレームのフレームレートで動作するカメラを用いつつ、毎秒２４フレームの映像信号を得ることが可能なカメラシステムの発明が開示されている。 As a prior art document, for example, Patent Document 1 discloses an invention of a camera system capable of obtaining a video signal of 24 frames per second while using a camera operating at a frame rate of 60 frames per second.
特開２０１３－１６５３１３号公報JP 2013-165313 A
　カメラシステムに毎秒２４コマおよび毎秒６０コマの回路を持たせた場合は、回路規模が膨大になってしまい、コストアップや消費電力の増加につながる。また、撮像素子が一部のＣＭＯＳ（Complementary　Metal　Oxide　Semiconductor）等の場合、画素の読出し時間のズレにより高速移動被写体が歪むローリングシャッター効果が、毎秒コマ数が低くなると目立ちやすくなる。
　本発明の目的は、毎秒６０コマで動作するデュアルグリーン方式テレビジョンカメラの映像信号から、毎秒２４コマの４Ｋ映像信号と毎秒２４コマのＨＤ映像信号を同時に生成することである。 If the camera system has circuits of 24 frames per second and 60 frames per second, the circuit scale becomes enormous, leading to increased costs and increased power consumption. In addition, when the image pickup device is a part of a CMOS (Complementary Metal Oxide Semiconductor) or the like, the rolling shutter effect in which a high-speed moving subject is distorted due to a shift in pixel readout time becomes more conspicuous when the number of frames per second becomes low.
An object of the present invention is to simultaneously generate a 24K 4K video signal and a 24 HD video signal at the same time from a video signal of a dual green television camera operating at 60 frames per second.
　本発明のカメラ制御装置は、シリアルパラレル変換部とバッファメモリ部と２４Ｐコンバータ部と画素補間部とパラレルシリアル変換部を有し、２４Ｐコンバータ部は毎秒２４コマのＨＤ映像信号を出力し、画素補間部は２４Ｐコンバータ部の出力から毎秒２４コマの４Ｋ映像信号を生成して出力することを特徴とする。 The camera control apparatus of the present invention has a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel serial conversion unit. The 24P converter unit outputs an HD video signal of 24 frames per second, and performs pixel interpolation. The unit generates and outputs a 4K video signal of 24 frames per second from the output of the 24P converter unit.
　また、本発明のカメラ制御装置は、上述のカメラ制御装置であって、さらにクロスコンバータ部を有し、クロスコンバータ部はバッファメモリ部の出力から毎秒６０コマの７２０画素の映像信号を生成して出力することを特徴とする。 The camera control device of the present invention is the above-described camera control device, further including a cross converter unit, which generates a 720 pixel video signal of 60 frames per second from the output of the buffer memory unit. It is characterized by outputting.
　さらに、本発明のカメラ制御装置は、上述のカメラ制御装置であって、さらにＰＩコンバータ部とダウンコンバータ部を有し、ＰＩコンバータ部はバッファメモリ部の出力から毎秒６０コマの飛越し走査の垂直１０８０画素の映像信号を生成して出力し、ダウンコンバータ部はＰＩコンバータ部の出力から毎秒６０コマの飛越し走査の４８０画素の映像信号を生成して出力することを特徴とする。 Furthermore, the camera control device of the present invention is the camera control device described above, and further includes a PI converter unit and a down-converter unit, and the PI converter unit performs vertical scanning of 60 frames per second from the output of the buffer memory unit. A video signal of 1080 pixels is generated and output, and the down converter unit generates and outputs a video signal of 480 pixels of interlaced scanning at 60 frames per second from the output of the PI converter unit.
　本発明のテレビジョンカメラは、シリアルパラレル変換部とバッファメモリ部と２４Ｐコンバータ部と画素補間部とパラレルシリアル変換部を有し、前記２４Ｐコンバータ部は、毎秒２４コマのＨＤ映像信号を出力し、前記画素補間部は、前記２４Ｐコンバータ部の出力から毎秒２４コマの４Ｋ映像信号を生成して出力するカメラ制御手段を備え、該カメラ制御手段は、６０ｐ映像の最初の所定数のフレーム分の後のフレームより所定のフレーム数毎にフレームを順次繰り返して抽出することで２４ｐ映像とするフレーム抽出手段を備えたことを特徴とする。 The television camera of the present invention includes a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel / serial conversion unit, and the 24P converter unit outputs an HD video signal of 24 frames per second, The pixel interpolation unit includes a camera control unit that generates and outputs a 24K 4K video signal from the output of the 24P converter unit, and the camera control unit performs the first predetermined number of frames of the 60p video. It is characterized by comprising a frame extracting means for making a 24p video by sequentially repeating the frames for every predetermined number of frames.
　本発明のテレビジョンカメラは、シリアルパラレル変換部とバッファメモリ部と２４Ｐコンバータ部と画素補間部とパラレルシリアル変換部を有し、前記２４Ｐコンバータ部は、毎秒２４コマのＨＤ映像信号を出力し、前記画素補間部は、前記２４Ｐコンバータ部の出力から毎秒２４コマの４Ｋ映像信号を生成して出力するカメラ制御手段を備え、６０ｐフレームから２つの最初のフレーム、次の３つの最初のフレーム、次の２つの最初のフレーム、次の３つの最初のフレーム、・・・というように繰り返しの順次プルダウンしていくことで２４ｐ映像を出力するものである。 The television camera of the present invention includes a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel / serial conversion unit, and the 24P converter unit outputs an HD video signal of 24 frames per second, The pixel interpolation unit includes camera control means for generating and outputting 24 frames per second of 4K video signals from the output of the 24P converter unit, and from the 60p frame, two first frames, the next three first frames, the next The 24p video is output by repeatedly pulling down sequentially such as the first two frames, the next three first frames, and so on.
　本発明によれば、毎秒６０コマで動作するデュアルグリーン方式テレビジョンカメラの映像信号から、毎秒２４コマの４Ｋ映像信号と毎秒２４コマのＨＤ映像信号を同時に生成することができ、毎秒６０コマの４Ｋ映像信号との切り替え使用も可能である。 According to the present invention, it is possible to simultaneously generate a 4K video signal of 24 frames per second and a HD video signal of 24 frames per second from a video signal of a dual green television camera operating at 60 frames per second. Switching to 4K video signal is also possible.
本発明の一実施例に係るカメラ制御装置を含むカメラシステムのブロック図である。1 is a block diagram of a camera system including a camera control device according to an embodiment of the present invention. 本発明の一実施例に係るカメラ制御装置のブロック図である。It is a block diagram of the camera control apparatus which concerns on one Example of this invention. 本発明の一実施例に係るカメラ制御装置のフレーム単位のタイミングチャートである。4 is a timing chart in units of frames of the camera control device according to the embodiment of the present invention. 本発明の一実施例に係るカメラ制御装置のライン単位のタイミングチャートである。4 is a timing chart for each line of the camera control device according to the embodiment of the present invention.
　以下、本発明の実施形態について図面を参照して詳細に説明する。
　図１は本発明の一実施例に係るカメラ制御装置を含むカメラシステムのブロック図である。
　図１のカメラシステムは、撮像装置１００とカメラ制御装置（Camera　Control　Unit）２００が光ファイバーケーブル３００で接続されている。
　なお、撮像装置１００とカメラ制御装置２００の接続は、光ファイバーケーブルに限定するものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram of a camera system including a camera control device according to an embodiment of the present invention.
In the camera system of FIG. 1, an imaging apparatus 100 and a camera control unit (Camera Control Unit) 200 are connected by an optical fiber cable 300.
The connection between the imaging device 100 and the camera control device 200 is not limited to an optical fiber cable.
　撮像装置１００は、色分解光学系１１２、第１緑色（Ｇ１、Green1）撮像素子１１１Ｇ１、第２緑色（Ｇ２、Green2）撮像素子１１１Ｇ２、赤色（Ｒ、Red）撮像素子１１１Ｒ、青色（Ｂ、Blue）撮像素子１１１Ｂ、映像信号処理部１１３、撮像素子駆動部１１４、ＣＰＵ（Central　Processing　Unit）部１１５で構成されている。 The imaging apparatus 100 includes a color separation optical system 112, a first green (G1, Green1) imaging element 111G1, a second green (G2, Green2) imaging element 111G2, a red (R, Red) imaging element 111R, and a blue (B, Blue). ) An image sensor 111B, a video signal processor 113, an image sensor driver 114, and a CPU (Central Processing Unit) 115 are configured.
　撮像装置１００は、入射光１０２がレンズ１０１で結像され、色分解光学系１１２で４板用に色分解され、第１緑色（Ｇ１）撮像素子１１１Ｇ１と第２緑色（Ｇ２）撮像素子１１１Ｇ２と赤色（Ｒ）撮像素子１１１Ｒおよび青色（Ｂ）撮像素子１１１Ｂで光電変換され、映像信号処理部１１３で各種信号処理が施され、ＨＤ／６０Ｐｘ２（水平１９２０×垂直１０８０画素、６０ Progressive、２出力）信号を出力する。 In the imaging apparatus 100, incident light 102 is imaged by a lens 101 and color-separated for four plates by a color separation optical system 112, and a first green (G1) imaging element 111G1 and a second green (G2) imaging element 111G2 It is photoelectrically converted by the red (R) image sensor 111R and the blue (B) image sensor 111B, subjected to various signal processing by the video signal processing unit 113, and HD / 60Px2 (horizontal 1920 × vertical 1080 pixels, 60 Progressive, two outputs) Output a signal.
　撮像装置１００は、毎秒６０コマで有効画素数：水平１９２０×垂直１０８０の撮像素子を赤・緑１・緑２・青の４個を用いて動作させ、得られた映像信号をパラレル－シリアル変換して、光ファイバーケーブル３００を経てカメラ制御装置（ＣＣＵ）２００へ伝送する。 The image pickup apparatus 100 operates an image pickup device having an effective number of pixels of horizontal 1920 × vertical 1080 using four pieces of red, green 1, green 2 and blue at 60 frames per second, and parallel-serial conversion of the obtained video signal Then, the data is transmitted to the camera control unit (CCU) 200 via the optical fiber cable 300.
　カメラ制御装置２００は、ＨＤ／６０Ｐｘ２を入力して、４Ｋ／２４ｐ，ＨＤ／２４ｐ，ＨＤ／６０ｐ，７２０／６０ｐ，ＨＤ／６０ｉ（interlaceまたはinterlaced　scan），４８０／６０ｉ信号を同時に出力する。 The camera control apparatus 200 inputs HD / 60Px2 and outputs 4K / 24p, HD / 24p, HD / 60p, 720 / 60p, HD / 60i (interlace or interlaced scan), and 480 / 60i signals simultaneously.
　図２は本発明の一実施例に係るカメラ制御装置のブロック図である。
　図２において、カメラ制御装置２００は、Ｓ／Ｐ（シリアルパラレル変換部）部２０１、バッファメモリ部２０２、２４Ｐコンバータ部２０３、フレームメモリ部２０４、画素補間部２０５、クロスコンバータ部２０６、ＰＩコンバータ（Progressive-Interlace変換部）部２０７、ダウンコンバータ部２０８、Ｐ／Ｓ（パラレルシリアル変換部）部２０９－１～２０９－６で構成されている。
　なお、フレームメモリ２０４部は、例えば、ＤＤＲ２（Double-Data-Rate2）のＤＲＡＭ（Dynamic　Random　Access　Memory）である。 FIG. 2 is a block diagram of a camera control apparatus according to an embodiment of the present invention.
In FIG. 2, the camera control apparatus 200 includes an S / P (serial / parallel conversion unit) unit 201, a buffer memory unit 202, a 24P converter unit 203, a frame memory unit 204, a pixel interpolation unit 205, a cross converter unit 206, a PI converter ( Progressive-Interlace conversion unit) 207, down converter 208, and P / S (parallel serial conversion units) 209-1 to 209-6.
The frame memory 204 is, for example, a DDR2 (Double-Data-Rate2) DRAM (Dynamic Random Access Memory).
　カメラ制御装置２００は、ＨＤ／６０Ｐｘ２を入力して、Ｓ／Ｐ部２０１で２０ビットのパラレル映像信号に変換し、バッファメモリ部２０２に書き込む。
　２４Ｐコンバータ２０３部は、フレームメモリ部２０４を用いてフレーム単位で映像をバッファリングしながら、６０ｐから２４ｐに変換する。 The camera control device 200 receives HD / 60Px2, converts it into a 20-bit parallel video signal by the S / P unit 201, and writes it into the buffer memory unit 202.
The 24P converter 203 converts the video from 60p to 24p while buffering the video in units of frames using the frame memory unit 204.
　図３は本発明の一実施例に係るカメラ制御装置のフレーム単位のタイミングチャートである。
　フレームメモリ２０４部は、６０ｐ映像の全フレームを書き込み、読出し時は２フレーム遅れで、（５ｎ）フレームと（５ｎ＋２）フレームを読み出す（ｎは正の整数）。
　これは、６０ｐ映像より２４ｐ映像とするためのフレームの抽出を行うものであり、６０ｐフレームから２つの最初のフレーム、次の３つの最初のフレーム、次の２つの最初のフレーム、次の３つの最初のフレーム、・・・というように順次プルダウンしていくことで２４ｐ映像となる。
　ここで、図３の６０ｐ映像の最初の２フレーム分（すなわち０、１の２フレーム）は前述したプルダウンの際に安定させて余裕を持たせるためのバッファ的役割を担うものである。 FIG. 3 is a timing chart for each frame of the camera control apparatus according to the embodiment of the present invention.
The frame memory 204 unit writes all the frames of the 60p video, and reads (5n) frames and (5n + 2) frames with a delay of 2 frames at the time of reading (n is a positive integer).
This is to extract a frame to make a 24p video from a 60p video, and from the 60p frame, two first frames, next three first frames, next two first frames, next three By sequentially pulling down the first frame, etc., 24p video is obtained.
Here, the first two frames (that is, two frames of 0 and 1) of the 60p video in FIG. 3 play a role of a buffer for stabilizing and giving a margin in the pull-down described above.
　図４は本発明の一実施例に係るカメラ制御装置のライン単位のタイミングチャートである。
　フレームメモリ部２０４は、書き込み時は全ラインを１ライン毎に書き込む。６０ｐ読出し時は、１ライン毎に画面の上半分と下半分を交互に読み出す。また２４ｐ読出し時は、（５ｎ）ラインで上半分の４Ｋ／２４ｐ信号、（５ｎ＋１）ラインで奇数ラインの２Ｋ／２４ｐ信号、（５ｎ＋２）ラインで下半分の４Ｋ／２４ｐ信号、（５ｎ＋３）ラインで偶数ラインの２Ｋ／２４ｐを、各々読み出す。このように４Ｋ／６０ｐ読出しに必要な帯域と、４Ｋ／２４ｐと２Ｋ／２４ｐを同時に読み出すのに必要な帯域は同じであるため、６０ｐ読出しの５ｍ（ｍは１以上の整数）番目では２４ｐ読出しを行わず、撮影目的に合わせて６０ｐ読出しと２４ｐ読出しを切り替えて使用することができる。
　上述した図３の説明と併せて、６０ｐ映像から２４ｐ映像を抽出するフレーム読み出しをフレームメモリ部２０４で行うことで、２４ｐ用の専用のメモリを増加することなく、６０ｐ用メモリで２４ｐ映像出力に対応することができる。 FIG. 4 is a timing chart for each line of the camera control device according to the embodiment of the present invention.
The frame memory unit 204 writes all lines line by line at the time of writing. At the time of 60p reading, the upper half and the lower half of the screen are alternately read for each line. When reading 24p, the upper half of 4K / 24p signal at (5n) line, the odd number of 2K / 24p signal at (5n + 1) line, the lower half of 4K / 24p signal at (5n + 2) line, and (5n + 3) line Read 2K / 24p of even lines. As described above, the bandwidth required for 4K / 60p reading and the bandwidth required for simultaneously reading 4K / 24p and 2K / 24p are the same, so 24p reading is performed at the 5mth (m is an integer of 1 or more) of 60p reading. It is possible to switch between 60p reading and 24p reading according to the purpose of photographing.
In conjunction with the description of FIG. 3 described above, the frame memory unit 204 performs frame readout for extracting 24p video from 60p video, so that the 24p video output can be performed with the 60p memory without increasing the dedicated memory for 24p. Can respond.
　次に、図２を用いて、２４Ｐコンバータ部２０３以降の動作について説明する。
　２４Ｐコンバータ部２０３の出力４Ｋ／２４ｐ（または６０ｐ）の信号は、画素補間部２０５で、２Ｋの赤・緑１・緑２・青の信号から、水平・垂直２倍の４Ｋの赤・緑・青の信号を、周囲の画素から補間して生成する。その後、Ｐ／Ｓ部２０９－１でＳＤＩ（シリアル・デジタル・インターフェース）信号に変換し、４Ｋ／２４ｐ（毎秒２４コマの４Ｋ映像信号）信号として出力する。 Next, the operation after the 24P converter unit 203 will be described with reference to FIG.
The output 4K / 24p (or 60p) signal of the 24P converter unit 203 is converted from a 2K red / green 1 / green 2 / blue signal to a horizontal / vertical double 4K red / green / A blue signal is generated by interpolation from surrounding pixels. Thereafter, the P / S unit 209-1 converts the signal into an SDI (Serial Digital Interface) signal and outputs it as a 4K / 24p (24K frame 4K video signal) signal.
　また、ＨＤ／２４ｐ（毎秒２４コマのＨＤ映像信号）は、２４Ｐコンバータ部６２０３からＰ／Ｓ部２０９－２で直接パラレル信号からシリアル信号に変換して出力する。
　さらに、２４Ｐコンバータ部２０３の入力信号は、ＨＤ／６０ｐ（毎秒６０コマのＨＤ映像信号）の信号としても使用でき、クロスコンバータ部２０６やＰＩコンバータ部２０７やダウンコンバータ部２０８を用いることで、各々７２０／６０ｐ（毎秒６０コマの垂直７２０画素の映像信号）、ＨＤ／６０ｉ（毎秒６０コマの飛越し走査の垂直１０８０画素の映像信号）、４８０／６０ｉ（毎秒６０コマの飛越し走査の垂直４８０画素の映像信号）の信号として出力する。 Also, HD / 24p (24 video images per second) is directly converted from a parallel signal to a serial signal by the P / S unit 209-2 from the 24P converter unit 6203 and output.
Furthermore, the input signal of the 24P converter unit 203 can also be used as an HD / 60p (60 frames per second HD video signal) signal. By using the cross converter unit 206, the PI converter unit 207, and the down converter unit 208, 720 / 60p (vertical 720 pixel video signal at 60 frames per second), HD / 60i (vertical 1080 pixel video signal at 60 frames per second), 480 / 60i (vertical scanning 480 at 60 frames per second) Output as a pixel image signal).
　本発明の実施形態であるカメラ制御装置は、毎秒６０コマで動作するデュアルグリーン方式テレビジョンカメラの映像信号から、毎秒２４コマの４Ｋ映像信号と毎秒２４コマのＨＤ映像信号を同時に生成することができ、毎秒６０コマの４Ｋ映像信号との切り替え使用も可能である。 The camera control apparatus according to an embodiment of the present invention can simultaneously generate a 24K frame 4K video signal and a 24 frame HD video signal from a video signal of a dual green television camera operating at 60 frames per second. It is also possible to switch to a 4K video signal of 60 frames per second.
　以上、本発明の一実施形態について詳細に説明したが、本発明は上述した実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲で種々変更して実施することができる。 As mentioned above, although one embodiment of the present invention was described in detail, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
　毎秒６０コマで動作するデュアルグリーン方式テレビジョンカメラの映像信号から、毎秒２４コマの４Ｋ映像信号と毎秒２４コマのＨＤ映像信号を同時に生成することによって、複数の映像フォーマットの映像信号を同時に使用する用途に適用できる。この出願は、２０１５年１１月１７日に出願された日本出願特願２０１５－２２４８７５を基礎として優先権の利益を主張するものであり、その開示の全てを引用によってここに取り込む。 Simultaneously use video signals in multiple video formats by simultaneously generating 24K 4K video signals and 24 HD video signals per second from the video signals of a dual green television camera operating at 60 frames per second Applicable to usage. This application claims the benefit of priority based on Japanese Patent Application No. 2015-224875 filed on November 17, 2015, the entire disclosure of which is incorporated herein by reference.
　１００：撮像装置、１０１：レンズ、１０２：入射光、１１１Ｇ１：Ｇ１撮像素子、１１１Ｇ２：Ｇ２撮像素子、１１１Ｒ：Ｒ撮像素子、１１１Ｂ：Ｂ撮像素子、１１２：色分解光学系、１１３：映像信号処理部、１１４：撮像素子駆動部、１１５：ＣＰＵ部、２００：カメラ制御装置、２０１：Ｓ／Ｐ部、２０２：バッファメモリ部、２０３：２４Ｐコンバータ部、２０４：フレームメモリ部、２０５：画素補間部、２０６：クロスコンバータ部、２０７：ＰＩコンバータ部、２０８：ダウンコンバータ部、２０９－１～２０９－６：Ｐ／Ｓ部、３００：光ファイバーケーブル。 100: imaging device, 101: lens, 102: incident light, 111G1: G1 imaging device, 111G2: G2 imaging device, 111R: R imaging device, 111B: B imaging device, 112: color separation optical system, 113: video signal processing 114: Image sensor driving unit 115: CPU unit 200: Camera control unit 201: S / P unit 202: Buffer memory unit 203: 24P converter unit 204: Frame memory unit 205: Pixel interpolation unit 206: Cross converter section, 207: PI converter section, 208: Down converter section, 209-1 to 209-6: P / S section, 300: Optical fiber cable.

Claims (4)

  1. 　シリアルパラレル変換部とバッファメモリ部と２４Ｐコンバータ部と画素補間部とパラレルシリアル変換部を有し、
    　前記２４Ｐコンバータ部は、毎秒２４コマのＨＤ映像信号を出力し、
    　前記画素補間部は、前記２４Ｐコンバータ部の出力から毎秒２４コマの４Ｋ映像信号を生成して出力することを特徴とするカメラ制御装置。     A serial-parallel converter, a buffer memory, a 24P converter, a pixel interpolator, and a parallel-serial converter;
    The 24P converter unit outputs an HD video signal of 24 frames per second,
    The camera control device, wherein the pixel interpolation unit generates and outputs a 24K frame 4K video signal from the output of the 24P converter unit.
  2. 　請求項１に記載のカメラ制御装置であって、
    　さらにクロスコンバータ部を有し、
    　前記クロスコンバータ部は、前記バッファメモリ部の出力から毎秒６０コマの７２０画素の映像信号を生成して出力することを特徴とするカメラ制御装置。     The camera control device according to claim 1,
    Furthermore, it has a cross converter part,
    The cross converter unit generates and outputs a video signal of 720 pixels of 60 frames per second from the output of the buffer memory unit.
  3. 　請求項１に記載のカメラ制御装置であって、
    　さらにＰＩコンバータ部とダウンコンバータ部を有し、
    　前記ＰＩコンバータ部は、前記バッファメモリ部の出力から毎秒６０コマの飛越し走査の垂直１０８０画素の映像信号を生成して出力し、
    　前記ダウンコンバータ部は、前記ＰＩコンバータ部の出力から毎秒６０コマの飛越し走査の４８０画素の映像信号を生成して出力することを特徴とするカメラ制御装置。     The camera control device according to claim 1,
    Furthermore, it has a PI converter part and a down converter part,
    The PI converter unit generates and outputs a vertical 1080 pixel video signal of interlaced scanning at 60 frames per second from the output of the buffer memory unit,
    The down converter unit generates and outputs a video signal of 480 pixels of interlaced scanning at 60 frames per second from the output of the PI converter unit.
  4. 　テレビジョンカメラにおいて、シリアルパラレル変換部とバッファメモリ部と２４Ｐコンバータ部と画素補間部とパラレルシリアル変換部を有し、
    　前記２４Ｐコンバータ部は、毎秒２４コマのＨＤ映像信号を出力し、
    　前記画素補間部は、前記２４Ｐコンバータ部の出力から毎秒２４コマの４Ｋ映像信号を生成して出力するカメラ制御手段を備え、
    　該カメラ制御手段は、６０ｐ映像の最初の所定数のフレーム分の後のフレームより所定のフレーム数毎にフレームを順次繰り返して抽出することで２４ｐ映像とするフレーム抽出手段を備えたことを特徴とするテレビジョンカメラ。     The television camera has a serial / parallel conversion unit, a buffer memory unit, a 24P converter unit, a pixel interpolation unit, and a parallel / serial conversion unit,
    The 24P converter unit outputs an HD video signal of 24 frames per second,
    The pixel interpolation unit includes camera control means for generating and outputting a 24K frame 4K video signal from the output of the 24P converter unit,
    The camera control means includes frame extraction means for 24p video by sequentially repeating frames for a predetermined number of frames from frames after the first predetermined number of frames of 60p video. TV camera.
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