JP2001083928A - Display device and method for converting frame rate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of avoiding the display of images of different frames in the upper and lower parts of a screen by detecting the time difference between the reset time of a writing address and the reset time of a reading address, and stopping the write to a frame memory when the occurrence of memory passing is judged. SOLUTION: A timing difference detection part 42 detects the difference between the reset times of a writing address and a reading address. A memory passing judgment part 43 transmits, when it judges the occurrence of memory passing in the next writing frame, the judgment result to a writing address generation part 24. The writing address generation part 24 sets the writing address in a fixed state for one frame in the next writing frame when the judgment result of the occurrence of overtaking of memory is received, and stops the writing for one frame of an input signal to the area for writing the effective line of the frame memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device and a frame rate conversion method.

[0002]

2. Description of the Related Art The frame rate of a plasma display is generally 60 Hz or 50 Hz, and cannot support all frame rates. This is because, in a display device such as a cathode ray tube, the brightness is changed depending on the intensity of the electron beam, whereas in the plasma display, the light emission intensity is always kept constant and the light emission time is changed to change the brightness. Because. Here, the maximum luminance of the plasma display is as follows. One frame period Tf is divided into an address period Ta and a light emission period Tb, and the maximum brightness is expressed by using the address period Ta and Equation 1 below.

[0003]

(Equation 1)

In Equation 1, K is a proportional constant. Since the address period Ta is constant, the maximum luminance depends on one frame period Tf as can be seen from Expression 1. The longer the one-frame period Tf, that is, the lower the frame rate, the higher the maximum luminance. In the case of a plasma display, this maximum brightness is lower than that of a cathode ray tube,
It is necessary to increase the maximum brightness even a little. Therefore, the frame rate cannot be increased, and the PAL signal, NT
It is general to operate at 50 Hz or 60 Hz in consideration of the frame rate of the SC signal and the high definition signal.

However, there are various types of frame rates of personal computers (60 to 85 Hz) at present, and unless the frame rate is converted, it cannot be displayed on the plasma display. To cope with this, a display device using a plasma display uses a frame memory and converts the frame rate to, for example, about 60 Hz.

FIG. 1 shows a configuration of a frame rate conversion unit in a display device. FIG. 6 shows the configuration of a conventional frame rate conversion control unit 14.

Analog RG input from a personal computer or the like
The B signal is converted into digital video data (Write-Data) by the AD converter 11. AD converter 1
1 (Write Write)
-Data) is the write address (W-Address)
And is written into the frame memory 12 based on the write clock (WCLK).

A write address (W-Address) and a write clock (WCLK) are generated by the following methods, respectively. The write clock (WCLK) is output from the PLL circuit 2
1 is generated. The PLL circuit 21 generates a write clock (WCLK) using the horizontal synchronization signal (Signal-Hs) of the input signal as a reference signal.

The write address (W-Address) is
It is generated by the write address generation unit 24. The write address generation unit 24 receives a write clock (WCLK) as an input and a vertical synchronization signal (Signal-Vs) of an input signal.
On the basis of the count value of the write vertical counter 22 which is reset by the write clock counter (WCLK) and the count value of the write horizontal counter 23 which is reset by the horizontal synchronization signal (Signal-Hs).
Generate a write address (W-Address).

Reading of digital video data (Read-Data) from the frame memory 12 is performed by using a read address (R-Address) and a read clock (RC).
LK). Read address (R-Add
res) and the read clock (RCLK) are generated by the following methods, respectively. Read clock (RCLK)
Is the same clock as a reference clock for operating the plasma display 13, and the crystal oscillator 2
5 or the like. Read clock (RCLK)
Is a write clock (WCL) generated by the PLL circuit 21.
K) is an asynchronous clock.

The read address (R-Address) is
It is generated by the read address generation unit 28. The read address generation unit 28 receives the read clock (RCLK) as input, resets the counter value of the read vertical counter 26 reset in the same cycle as the vertical synchronization signal (PDP-Vs) for the plasma display 13, and the read clock ( RCL
K), and generates a read address (R-Address) based on the horizontal synchronizing signal (PDP-Hs) for the plasma display 13 and the counter value of the read horizontal counter 27 reset in the same cycle. .

The reading vertical counter 26 is reset at the frame rate of the plasma display, such as 50 Hz or 60 Hz. Read clock (RCLK) and read address (R-Address)
s), digital video data (Read-Data) is read from the frame memory 12, and a read clock (RCLK), a vertical synchronizing signal (PDP-Vs) for the plasma display 13, and a digital clock for the plasma display 13 are read. Display on the plasma display 13 is performed based on the horizontal synchronization signal (PDP-Hs).

By the way, in the conventional frame rate conversion method, the overtaking phenomenon of the memory occurs once every several frames, and at that time, images of different frames are displayed at the top and bottom of the screen. If it is a still image, no problem occurs even if images of different frames are displayed at the top and bottom of the screen. However, in recent years, personal computers have been able to handle not only still images but also moving images. When images of different frames are displayed at the top and bottom of the screen when inputting a moving image, the boundary between those frames is displayed. Is recognized, and the screen becomes difficult to see.

For example, when converting the frame rate to 60 Hz, the frequency of occurrence of the memory overtaking phenomenon decreases as the frame rate of the input signal approaches 60 Hz, and the frequency of occurrence of the memory overtaking phenomenon increases as the frame rate of the input signal increases from 60 Hz.
Currently, the frame rate of personal computers is shifting to higher ones, and it is expected that the frequency of occurrence of memory overtaking phenomenon will increase in the future.

Regarding the frequency of occurrence of the memory overtaking phenomenon,
This will be described more specifically. The frame rate of the plasma display is 60 Hz, the number of lines is 525, and the number of effective lines is 480. The frame rate of the input signal is Fi, the number of lines is 525, and the number of effective lines is 480. The memory capacity is N frames.

Under such conditions, the number of overtakings of the memory occurring in one second is expressed by the following equation (2). The result is shown in Table 1.

[0017]

(Equation 2)

[0018]

[Table 1]

A method of deriving Equation 2 will be described.

When the overtaking of the memory outside the effective area is considered (when the overtaking of the memory is considered not only in the effective area but also in the entire area), the frame rate of the input signal is set to Fi and the capacity of the memory is set to Fi. Assuming one frame, overtaking occurs (Fi-60) times per second.
When the memory capacity is N frames, the number of overtaking of the memory decreases in proportion to N. Therefore, the number of overtakings of the memory per second is (Fi-60) / N.

When the overtaking of the memory outside the effective area is not considered (when only the overtaking of the memory inside the effective area is considered), if the number of lines is 525 and the number of effective lines is 480, the outside of the effective area is considered. Memory overtaking times per second in consideration of memory overtaking of ｛(F
i-60) / N}, the occurrence probability is 480/525
Becomes Therefore, the number of overtaking of the memory per second when the overtaking of the memory outside the effective area is not considered is [{(Fi-60) / N} × (480/525)].
And 32 × (Fi-60) / (35 × N).

When the capacity of the frame memory is one frame and the frame rate of the input signal is 65 Hz, the overtaking phenomenon of the memory occurs at a frequency of 4.6 times per second (out of 60 frames). Further, when the frame rate of the input signal is 80 Hz, the memory overtaking phenomenon occurs 18.6 times per second. Increasing the capacity of the frame memory reduces the frequency of memory overtaking phenomena, but it is necessary to reduce the capacity of the frame memory in consideration of cost. Generally, a frame memory having a capacity of one or two frames is used.

[0023]

SUMMARY OF THE INVENTION The present invention provides a display device and a frame rate conversion method capable of avoiding the occurrence of a memory overtaking phenomenon and of preventing images of different frames from being displayed at the top and bottom of a screen. The purpose is to provide.

[0024]

A first display device according to the present invention is a display device that performs frame rate conversion by using a frame memory. The display device detects a frame rate of an input video signal, and converts the input video signal into an A / D signal. Means for converting, means for generating a write address for writing the digital-converted digital video data to the frame memory, means for generating a read address for reading the digital video data written to the frame memory, writing Means for detecting a time difference between the reset time of the address and the reset time of the read address; means for determining, based on the detected time difference, whether or not memory eviction occurs in the next write frame; If it is determined that memory overtaking will occur in one write frame, the next write frame In over arm, characterized in that it comprises means to stop writing to the frame memory of the data of one frame.

The second display device according to the present invention includes a frame memory having a capacity of two frames, and writes data to each memory area of one frame capacity.
A display device that performs frame rate conversion by alternately reading data for each frame and reading data alternately for each frame in each memory area of one frame capacity detects the frame rate of the input video signal. Means for converting an input video signal into an analog signal,
Means for generating a write address for writing the converted digital video data to the frame memory; means for generating a read address for reading the digital video data written to the frame memory; reset time of the write address; Means for detecting a time difference between the reset address of the read address and the reset time, means for determining whether or not memory eviction occurs in the next read frame based on the detected time difference, and memory for the next read frame. When it is determined that overtaking occurs, in a next read frame, there is provided a means for reading one frame of data from the same memory area as the memory area from which one frame of data was read immediately before. I do.

The third display device according to the present invention includes a frame memory having a capacity of three frames or more, and writes data in each memory area of one frame capacity one by one in order. In a display device that performs frame rate conversion by sequentially reading data from each memory area of one frame capacity for each frame, means for detecting the frame rate of the input video signal, Means to convert,
Means for generating a write address for writing the A / D converted digital video data to the frame memory; means for generating a read address for reading the digital video data written to the frame memory; reset time of the write address Means for detecting a time difference between the reset time of the read address and the reset time of the read address, means for determining whether or not memory eviction occurs in the next read frame based on the detected time difference, and If it is determined that memory overtaking will occur,
In the next read frame, there is provided a means for reading data from a memory area whose read order is one ahead of a memory area in which data is to be read in the frame.

According to a first frame rate conversion method according to the present invention, in the frame rate conversion method using a frame memory, the reset time of the write address of the frame memory and the reset of the read address of the frame memory. The time difference from the time is detected, and it is determined whether or not the memory overtaking phenomenon occurs in the next frame based on the detected time difference.If it is determined that the memory overtaking phenomenon occurs in the next writing frame, In the next write frame, writing of one frame of data into the frame memory is stopped.

According to the second frame rate conversion method of the present invention, a frame memory having a capacity of two frames is provided, and data is written alternately for each frame in each memory area of one frame capacity. In a frame rate conversion method of performing frame rate conversion by alternately reading data from each memory area of one frame capacity for each frame, a reset time of a write address of the frame memory, Detects the time difference from the reset time of the read address of the memory, determines whether or not the memory overtaking phenomenon occurs in the next read frame based on the detected time difference, and the memory overtake occurs in the next read frame. If so, in the next read frame, one frame immediately before And characterized in that the same memory region that was read out data beam component to read out one frame of data.

In the third frame rate conversion method according to the present invention, a frame memory having a capacity of three frames or more is provided, and data is written to each memory area of one frame capacity one by one in order. In addition, in a frame rate conversion method of performing frame rate conversion by sequentially reading data from each memory area of one frame capacity for each memory area, a reset time of a write address of a frame memory,
The time difference from the reset time of the read address of the frame memory is detected, and it is determined whether or not the memory overtaking phenomenon occurs in the next read frame based on the detected time difference, and the memory is overtaken in the next read frame. Is determined, the data is read from the memory area in the next read frame, which is one step ahead of the memory area from which the data should be read in that frame.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

[1] Description of First Embodiment

FIG. 1 shows the configuration of the frame rate conversion unit in the display device.

The frame rate conversion unit includes an AD converter 11 for AD-converting an input video signal, a frame memory 12 in which AD-converted digital video data is written, and a plasma for displaying digital video data read from the frame memory 12. A display 13 and a frame rate conversion control unit 1 for controlling writing of digital video data to the frame memory 12 and reading of digital video data from the frame memory 12
4 is provided.

FIG. 2 shows the configuration of the frame rate conversion control section 14. 2, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

A write address (W-Address) for the frame memory 12, a write clock (WCLK),
Read address (R-Add) for frame memory 12
res) and the generation method of the read clock (RCLK) are the same as the conventional method.

FIG. 3 shows a timing chart of writing and reading.

The solid line in FIG. 3A indicates the write address (WA).
address) and the double line indicates the read address (R-Add).
res). In addition, between the two inner broken lines, the number of effective lines 48 out of the number of horizontal lines 525 is 48.
The part corresponding to zero is shown.

In the effective line portion, memory overtaking occurs at a portion where the solid line and the double line overlap, and another frame is displayed above and below one frame. That is, as shown in FIG. 3B, when passing of the memory occurs, the F2 frame and the F3 frame of the input signal are mixed in the data of one frame read from the frame memory 13. Become.

The conditions under which memory overtaking occurs will be described. The overtaking of the memory is performed at the write address (W-Add).
) and the read address (R-Address) meet predetermined conditions. This condition depends on which of the input signal frame rate and the plasma display frame rate is higher. However, since the frame rate of the input signal is usually high, the following description is based on the assumption that the frame rate of the input signal is high. .

Overtaking of the memory occurs in the next write frame when the following two conditions are satisfied.

Read address (R-Address)
(Ta) when the address value (Ax) indicating the first pixel of the first line of the effective line group is the write address (W).
−Address) is the first line of the first line of the active line group.
Be earlier than the time (Tb) when the address (Ax) indicating the pixel is reached

Read address (R-Address)
Is the address (Ac) indicating the last pixel of the last line of the effective line group, the write address (W-
Address) is later than the time (Tb) when the address (Ay) indicating the last pixel of the last line of the effective line group is reached.

The frame memory has a capacity of a plurality of frames, and data is written into each memory area of the capacity of one frame in order of one frame at a time.
In the case where data reading is performed sequentially for each frame in each memory area corresponding to one frame capacity, the above two conditions are satisfied in a state where writing and reading are performed for the same memory area. When the condition is satisfied, memory overtaking occurs.

The start line of the effective line is the Ln line. Ln = 20 and the read address (R-Addr
Assuming that the time when ess) is reset is T0, the time when the write address (W-Address) is first reset after time T0 is T1, and the time difference between T1 and T0 is ΔT [sec], the following: When Expression 3 is satisfied, overtaking of the memory occurs in the next write frame. However, the frame rate of the plasma display is 60
Hz.

[0045]

(Equation 3)

A method for deriving Equation 3 will be described.

When the overtaking of the memory outside the effective area is considered, the time for one cycle of writing data to the memory is 1 / Fi, and the time for one cycle of reading data from the memory is 1/60. Therefore, the read address (RA)
The time (ΔT) from the time (T0) when the address is reset to the time (T1) when the write address (W-Address) is reset is the time (1 / Fi) of one cycle of writing data to the memory. Difference (1 / 60-1) from one cycle time (1/60) of reading data from the memory
If / Fi) or more, memory overtaking does not occur.

As a result, when the overtaking of the memory outside the effective area is considered, the condition under which the overtaking of the memory occurs is expressed by the following equation (4).

[0049]

(Equation 4)

When the overtaking of the memory outside the effective area is not considered, the time Ta and the time Tb in FIG.
If Tb is earlier in time than when と matches, memory overtaking does not occur. Assuming that Ta and Tb match (Ta = Tb), the read address (R−
Address (T0) at which (Address) is reset is ｛(1/60) × (Ln /
525) The time becomes a time earlier by｝ [sec].

The write address (W-Address)
s) is reset at time (T1) at time Ta (= T
b), {(1 / Fi) × (Ln / 525)}
The time becomes a time earlier by [sec]. Therefore,
ΔT when Ta and Tb match is ΔT = T1−T
0 = Ln (Fi-60) / (525 × 60 × Fi) [s
ec].

Here, if the time T1 is later than the time Ta (= Tb) by {(1 / Fi) × (Ln / 525)} sec, the memory overtakes. Therefore, the following Equation 5 is the first condition in which overtaking occurs.

[0053]

(Equation 5)

Next, when Tc and Td match,
If Tc is earlier in time, memory overtaking does not occur. Assume that Tc and Td match (Tc = Td)
Then, the time (T0) at which the read address (R-Address) is reset is [(1/60) × {(Ln + 480) / 525}] with respect to time Tc (= Td).
The time becomes a time earlier by [sec].

The write address (W-Address)
s) is reset at time (T1) at time Tc (= T
d), [(1 / Fi) × ｛(Ln + 480) /
525 °] [sec] is the previous time. Therefore, ΔT when Tc and Td match is ΔT
= T1-T0 = (Ln + 480) (Fi-60) / (5
25 × 60 × Fi) sec.

Here, [(1 / Fi) × {(Ln + 480) / 525}] se with respect to time Tc (= Td).
If the time of T1 is later than the time by c in time, memory overtaking occurs.
This is the second condition in which overtaking occurs.

[0057]

(Equation 6)

The condition expressed by the above equation (5) and the condition expressed by the above equation (6)
The condition that satisfies both the condition represented by
It is represented by

[0059]

(Equation 7)

In Equation 7, if Ln = 20, Equation 7 becomes Equation 3 above.

As can be seen from Equation 3, the overtaking of the memory depends on the frame rate of the input signal. Therefore,
As shown in FIG. 2, the frame rate conversion control unit 14 includes a vertical synchronizing signal (Signal-V) of the input signal.
A frame rate detector 41 for detecting the frame rate Fi of the input signal based on s) is provided.

The write address (W-Address)
s) and a timing difference detector 42 for detecting a difference ΔT between the reset times of the read address (R-Address).

Further, based on the frame rate Fi of the input signal, the difference ΔT, and the above equation 3, there is provided a memory overtaking judging section 43 for judging whether or not memory overtaking occurs in the next writing frame. I have. When the memory overtaking determination unit 43 determines that the memory overtaking will occur in the next write frame, it sends the determination result to the write address generation unit 24.

When the write address generator 24 receives the determination result that the overtaking of the memory occurs in the next write frame, as shown in FIG. 3C, the write address generator 24 writes the write address in the next write frame. (W-Addre
ss) is fixed for one frame, and the frame memory 1
The writing of one frame of the input signal to the area where the second valid line is written is stopped.

As a result, the frame displayed on the plasma display 13 is as shown in FIG. 3D, and it is possible to prevent the images of different frames from being mixedly displayed on one screen.

[2] Description of Second Embodiment

Next, a second embodiment will be described.
The frame rate conversion method according to the first embodiment is applied when the frame memory 12 has a capacity of one frame or more. The frame rate conversion method according to the second embodiment is applied when the frame memory 12 has a capacity of two frames or more.

In the frame rate conversion method according to the first embodiment, reading from the frame memory 12 is performed constantly, and there is a difference between the time when the write address is reset and the time when the read address is reset. Is satisfied, the writing to the effective area of the frame memory 12 is stopped for one frame so that the overtaking of the memory does not occur.

In the frame rate conversion method according to the second embodiment, writing is performed at a constant rate and read addresses are controlled so that overtaking of memory does not occur.

FIG. 4 is a block diagram of the frame rate conversion control unit 14. 4, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

Write address (W-Address) for frame memory 12, write clock (WCLK),
Read address (R-Add) for frame memory 12
res) and the read clock (RCLK) are the same as the conventional method.

FIG. 5 is a timing chart for writing and reading when the frame memory 12 has a capacity for two frames. In FIG. 5, two areas for one frame in the frame memory 12 are represented as a memory 1 and a memory 2, respectively.

The solid line in FIG. 5A indicates the write address (WA).
address) and the double line indicates the read address (R-Add).
res). In addition, between the two inner broken lines, the number of effective lines 48 out of the number of horizontal lines 525 is 48.
The part corresponding to zero is shown.

In the effective line portion, memory overtaking occurs at a portion where the solid line and the double line overlap, and another frame is displayed at the top and bottom of one frame. That is, as shown in FIG. 5B, when passing of the memory occurs, the F1 frame and the F3 frame of the input signal are included in the data of one frame read from the frame memory 12.
Frames are mixed.

The conditions under which memory overtaking occurs will be described. The overtaking of the memory is performed at the write address (W-Ad).
address) and the read address (R-Address) satisfy predetermined conditions. This condition depends on which of the input signal frame rate and the plasma display frame rate is higher, but since the normal input signal frame rate is high, here it is assumed that the input signal frame rate is high. explain.

Overtaking of a memory occurs in the next read frame when both of the following two conditions are satisfied.

Read address (R-Address)
Is the address value (Ax2) indicating the first pixel of the first line of the active line group, the write address (W-Address) indicates the first pixel of the first line of the active line group. The time when the address (Ax2) is reached (T
b) earlier

Read Address (R-Address)
Becomes the address (Ay2) indicating the last pixel of the last line of the effective line group, the write address (Wc)
(Address) becomes the address (Ay2) indicating the last pixel of the last line of the effective line group (Td).
Slower

The start line of the effective line is the Ln line. Assuming that Ln = 20, the read address (R-Add
If the time when the write address (W-Address) is first reset after T0 is T1 and the time difference between the times T1 and T0 is ΔT, the following equation 8 is obtained. When this is satisfied, memory overtaking occurs in the next read frame. However, the frame rate of the plasma display is 60 Hz.

[0080]

(Equation 8)

A method for deriving Equation 8 will be described.

When considering the overtaking of the memory outside the effective area, the time for one cycle of writing data to the memory is 1 / Fi [sec], and the time for reading data from the memory is 1
The cycle time is 1/60 [sec]. Therefore,
From the time (T0) when the read address (R-Address) is reset, the write address (W-Address)
The time (ΔT) up to the time (T1) when is reset is
One cycle time for writing data to memory (1 / Fi) and one cycle time for reading data from memory (1/60)
If the difference is (1 / 60-1 / Fi) [sec] or more,
No overtaking of memory occurs.

As a result, when the overtaking of the memory outside the effective area is considered, the condition under which the overtaking of the memory occurs is expressed by the following equation (9).

[0084]

(Equation 9)

In the case where overtaking of the memory outside the effective area is not considered, the time Ta and the time Tb in FIG.
If Tb is earlier in time than when と matches, memory overtaking does not occur. Assuming that Ta and Tb match (Ta = Tb), the read address (R−
Address (T0) at which (Address) is reset is ｛(1/60) + (1/6) with respect to time Ta (= Tb).
0) × (Ln / 525)｝ [sec].

The write address (W-Address)
s) is reset at time (T1) at time Ta (= T
b), ｛(1 / Fi) + (1 / Fi) × (Ln
/ 525) 時刻 [sec] is the previous time in time.
Therefore, ΔT when Ta and Tb match is ΔΔ
T = T1-T0 = (1 / 60-1 / Fi) + Ln (Fi
−60) / (525 × 60 × Fi) = (Ln + 525)
× (Fi-60) / (525 × 60 × Fi) [sec]
Becomes

Here, {(1 / Fi) + (1 / Fi) × (Ln / 525)} with respect to time Ta (= Tb).
If the time of T1 is later than the time earlier by [sec], memory overtaking occurs. Therefore, the following equation 10 is the first condition in which overtaking occurs.

[0088]

(Equation 10)

Next, when Tc and Td match,
If Tc is earlier in time, memory overtaking does not occur. Assume that Tc and Td match (Tc = Td)
Then, the time (T0) at which the read address (R-Address) is reset is [(1/60) + (1/60) × ｛(Ln + 48) with respect to time Tc (= Td).
0) / 525}] [sec].

The write address (W-Address)
s) is reset at time (T1) at time Tc (= T
d), [(1 / Fi) + (1 / Fi) × ｛(L
n + 480) / 525５] [sec]. Therefore, ΔT when Tc and Td match is ΔT = T1−T0 = (1 / 60−1 / Fi)
+ (Ln + 480) (Fi-60) / (525 × 60 ×
Fi) = (Ln + 1005) × (Fi−60) / (52)
5 × 60 × Fi) [sec].

Here, with respect to the time Tc (= Td), [(1 / Fi) + (1 / Fi) × ｛(Ln + 480) /
525 °] [sec] from the time earlier by T1
If the time becomes too late, memory overtaking will occur, so the following equation 11 is the second condition for overtaking.

[0092]

[Equation 11]

A condition that satisfies both the condition represented by the above equation 10 and the condition represented by the above equation 11 is represented by the following equation 12.

[0094]

(Equation 12)

In Expression 12, when Ln = 20,
Equation 12 becomes like Equation 8 above.

As can be seen from Equation 8, the overtaking of the memory depends on the input frame rate Fi. Therefore,
As shown in FIG. 4, the frame conversion control unit 14 is provided with a frame rate detection unit 51 for detecting a frame rate Fi of an input signal based on a vertical synchronization signal (Signal-Vs) of the input signal. I have.

The write address (W-Address)
s) and a timing difference detector 52 for detecting a difference ΔT between the reset times of the read address (R-Address).

Further, based on the frame rate Fi of the input signal, the difference ΔT, and the above equation (8), a memory overtaking determination section 53 for determining whether or not memory overtaking occurs in the next read frame is provided. I have. When the memory overtaking determination unit 53 determines that memory overtaking will occur in the next read frame, it sends the determination result to the read address generation unit 28.

When the read address generation unit 28 receives the result of the determination that the overtaking of the memory will occur in the next read frame, the read address generation unit 28, as shown in FIG. The digital video data (Read-Data) is read from the same memory area as the memory area from which the data was read.

Therefore, the digital video data (Read-Data) is read from the same memory area twice consecutively. Even if data is read twice consecutively from the same memory area, the content of the memory area is 1
Since the data is rewritten during the reading of the second data, different data is read in the second reading of the data from the reading of the first data. Therefore, even if data is read from the same memory area twice consecutively, the same digital video data is not read.

As described above, when it is determined that overtaking of the memory occurs in the next read frame, the digital video data is read from the same memory area as the memory area from which the data was read immediately before in the next read frame. By reading (Read-Data), the frame displayed on the plasma display 13 becomes as shown in FIG. 5D, and it is possible to avoid that the images of different frames are mixedly displayed on one screen. You.

[0102]

According to the present invention, it is possible to avoid the occurrence of the overtaking phenomenon of the memory, and it is possible to prevent the images of different frames from being displayed on the upper and lower sides of the screen.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame rate conversion unit.

FIG. 2 is a block diagram illustrating a configuration of a frame rate conversion control unit according to the first embodiment of the present invention.

FIG. 3 is a time chart for explaining an operation of a frame rate conversion control unit in FIG. 2;

FIG. 4 is a block diagram showing a configuration of a frame rate conversion control unit according to a second embodiment of the present invention.

FIG. 5 is a time chart for explaining an operation of the frame rate conversion control unit in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional frame rate conversion control unit.

[Explanation of symbols]

 Reference Signs List 11 AD converter 12 Frame memory 13 Plasma display 14 Frame rate conversion control unit 24 Write address generation unit 28 Read address generation unit 41, 51 Frame rate detection unit 42, 52 Timing difference detection unit 43, 53 Memory overtaking determination unit

Claims (6)

[Claims] 1. A display device for performing frame rate conversion using a frame memory, comprising: means for detecting a frame rate of an input video signal; means for A / D converting the input video signal; Means for generating a write address for writing to the frame memory, means for generating a read address for reading digital video data written to the frame memory, a time difference between a reset time of the write address and a reset time of the read address. Means for detecting, based on the detected time difference, means for determining whether or not memory overrun occurs in the next write frame, and when determining that overtaking of memory occurs in the next write frame. Is the frame of data for one frame in the next write frame. Means for stopping writing to the system memory. 2. A frame memory having a capacity of two frames is provided, data is alternately written to each memory area of one frame capacity one frame at a time, and data is read out of one memory capacity of one frame capacity. A display device for performing frame rate conversion by alternately performing one frame for each memory area, a means for detecting a frame rate of an input video signal, a means for AD converting an input video signal, Means for generating a write address for writing video data to the frame memory; means for generating a read address for reading digital video data written to the frame memory; reset time of the write address; Means for detecting a time difference from the reset time, based on the detected time difference, Means for determining whether or not memory overrun will occur in the next readout frame; and, if it is determined that memory overrun will occur in the next readout frame, one frame immediately before in the next readout frame. Means for reading one frame of data from the same memory area as the memory area from which the data was read. 3. A frame memory having a capacity of three frames or more is provided, data is sequentially written to each memory area of one frame capacity by one frame, and data is read by one frame capacity. A frame rate conversion means for detecting a frame rate of an input video signal, an A / D conversion means for an input video signal, Means for generating a write address for writing digital video data to the frame memory, means for generating a read address for reading digital video data written to the frame memory, reset time of the write address, and read address For detecting the time difference from the reset time of the device, based on the detected time difference Means for determining whether or not memory overrun will occur in the next readout frame, and if it is determined that memory overrun will occur in the next readout frame, Means for reading data from a memory area whose reading order is one ahead of a memory area in which data is to be read. 4. A frame rate conversion method using a frame memory, wherein a time difference between a reset time of a write address of the frame memory and a reset time of a read address of the frame memory is detected and detected. It is determined whether or not a memory overtaking phenomenon occurs in the next frame based on the time difference, and if it is determined that a memory overtaking phenomenon occurs in the next writing frame, one frame worth of the next writing frame is determined. A frame rate conversion method, wherein writing of data to a frame memory is stopped. 5. A frame memory having a capacity of two frames is provided, data is written alternately by one frame to each memory area of one frame capacity, and data is read out by one frame capacity. In the frame rate conversion method for performing frame rate conversion by alternately performing one frame at a time for each memory region, the reset time of the write address of the frame memory and the reset time of the read address of the frame memory are different. A time difference is detected, and based on the detected time difference, it is determined whether or not a memory overtaking phenomenon occurs in the next read frame. If it is determined that a memory overtaking phenomenon occurs in the next read frame, the next read is performed. In the frame, the same memory as the memory area from which data for one frame was read immediately before Frame rate conversion method is characterized in that so as to read out the data of one frame from Li region. 6. A frame memory having a capacity of three frames or more is provided, data is written to each memory area of one frame capacity one by one in order, and data is read by one frame capacity. In the frame rate conversion method of performing frame rate conversion by sequentially performing one frame at a time for each memory area of the memory area, the reset time of the write address of the frame memory, the reset time of the read address of the frame memory, Is determined based on the detected time difference, and whether or not the memory overtaking phenomenon occurs in the next read frame.If it is determined that the memory overtaking phenomenon occurs in the next read frame, the next In a read frame, the memory in which the data should be read in that frame Frame rate conversion method characterized by readout order from frequency has to read data from one previous memory areas.