JPH09269762A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the display read-out performance by detecting whether a display device is in a picture display period or a picture non-display period, and suppressing a refresh request for holding the data when it is in the picture display period. SOLUTION: The counter of a refresh reservation circuit 4 counts up the number of refresh reservation times by one when it receives a refresh request signal for holding the data from a refresh request circuit 3 to send the number of reservation times to a refresh control circuit 6. The refresh control circuit 6 decides whether or not the number of reservation times are zero, and decides whether or not the refresh request is reserved. Then, when a blanking signal from a display timing control circuit 4 shows the display period, the circuit 6 gives priority to display read-out to suppress the refresh request signal. Thus, the time for reading out is secured sufficiently in the display period, and high display performance is obtained.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device,
In particular, the present invention relates to a display device including a single port memory in which a display request for screen display and a refresh request for holding data are sent through the same port.

[0001]

2. Description of the Related Art When a dynamic memory device such as a single-port type DRAM is used as a frame memory for screen display, the frame memory has a refresh operation for display read request for screen display and data retention. Is input. However, since the single-port memory has only one port, it is not possible to input two or more requests to the single-port memory at the same time. Therefore, it is necessary to arbitrate and input the two requests of the display read request and the refresh request.

Conventionally, in this type of technique, the timing of the refresh request is generated at an independent timing that has no correlation with the timing of the display read request. Therefore, when the refresh operation request and the display read request conflict with each other, the refresh operation request is prioritized (hereinafter referred to as "prior art 1").

Further, according to another conventional technique of this type, as described in, for example, Japanese Patent Laid-Open No. 4-136985, a frame display is refreshed in a screen display system using a multiport DRAM as a frame buffer. The operation is executed a predetermined number of times in synchronization with the horizontal non-display period (hereinafter, referred to as "prior art 2").

[0004]

When the refresh request is generated at an independent timing which has no correlation with the display read request as in the above-mentioned prior art 1, the memory refresh operation is requested during the display read operation period. There is a case to be seen. For this reason, there is a problem that the time for display readout is reduced and the display readout performance is deteriorated.

Further, when the refresh operation is performed a fixed number of times in synchronization with the screen non-display period as in the prior art 2, the refresh timing required for the memory is different from the original refresh timing required for the memory. There is no choice but to execute more than the number of operations. For this reason, there is a problem that the time available for writing data is reduced and the performance of writing data to the memory is deteriorated.

An object of the present invention is to provide a display device with improved display read performance.

Another object of the present invention is to provide a display device with improved memory access efficiency.

[0008]

In order to solve the above-mentioned problems, a display device of the present invention generates a display request for displaying a frame memory and a display request for screen display, and a refresh request for holding data. A refresh request generating means for transmitting the display request and the refresh request to the frame memory through the same port, and whether the screen display or the screen non-display is performed. A display period detecting means for detecting the refresh request, and a suppressing means for suppressing the refresh request when the display period detecting means detects that the period is the screen display period.

Another display device of the present invention includes a frame memory, a display request generating means for generating a display request for screen display, and a refresh request generating means for generating a refresh request for holding data. A display device in which the display request and the refresh request are sent to the frame memory through the same port, and display period detection means for detecting which of the screen display period and the screen non-display period, Hold means for holding the refresh request when the display period detecting means detects that it is the screen display period, and holding when the display period detecting means detects the screen non-display period Refresh request sending means for sequentially sending the refresh requests held by the means, and the refresh request sending means Based on the refresh request and a memory access unit for executing the refresh operation for the frame memory.

Further, in another display device of the present invention, the holding means includes a counter for counting the number of times of holding the refresh request, and the refresh request sending means has the number of holding times of the holding requests stored in the counter. And a refresh number management means for sequentially sending

Further, in another display device of the present invention, a horizontal non-display period indicating a horizontal blanking non-display period and a vertical blanking non-display period are displayed with respect to the display unit in which the contents of the frame memory are displayed. And a blanking signal supply means for supplying a blanking signal including a vertical non-display period, and the display period detection means, in any period of the screen display or the screen non-display based on the blanking signal. It is characterized by detecting whether there is.

Further, in another display device of the present invention, the display period detecting means detects that the blanking signal is in the screen non-display period when the blanking signal is in the horizontal non-display period. To do.

Further, in another display device of the present invention, the display period detecting means detects that the blanking signal is in the screen non-display period when the blanking signal is in the vertical non-display period. To do.

Further, in another display device of the present invention, the display period detecting means is a period of the screen non-display in either a horizontal non-display period or a vertical non-display period of the blanking signal. Is detected.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a display device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a frame memory 1 and a memory control circuit 2.
The refresh request circuit 3, the refresh hold circuit 4, the display timing control circuit 5, the refresh control circuit 6, and the display unit 7 are included.

The frame memory 1 may be a dynamic type memory having one port, and in this embodiment, D
It is assumed to be RAM. Display data is stored in the frame memory 1. The memory control circuit 2 controls access to the frame memory 1. An access to the frame memory 1 is sent from a device such as a CPU or a drawing accelerator via the memory control circuit 2 to generate data to be displayed on the display unit 7. The refresh request circuit 3 generates a refresh request signal for a refresh operation necessary for holding data in the frame memory 1. The refresh hold circuit 4 counts and holds the number of refresh requests generated by the refresh request circuit 3 during the display period.
The display timing control circuit 5 determines the timing of display on the display unit 7. The refresh control circuit 6 controls the sending of a refresh request to the memory control circuit 2 based on the number of holdings held in the refresh holding circuit 4 and the display timing from the display timing control circuit 5. Data is displayed on the display unit 7.

Referring to FIG. 2, the memory control circuit 2 includes
The access arbitration circuit 21, the data control circuit 22, the address control circuit 23, the timing control circuit 24, and the display buffer 25 are included.

The access arbitration circuit 21 exclusively determines a memory cycle. The data control circuit 22 controls input / output of data to / from the frame memory 1. The address control circuit 23 generates an access address to the frame memory 1. The timing control circuit 24 generates the timing required for access to the frame memory 1 to generate the RAS / C.
It outputs a control signal such as AS. Display buffer 25
Temporarily stores the display data read from the frame memory 1.

The access arbitration circuit 21 arbitrates an access request to the frame memory 1 from a device such as a CPU, a refresh request from the refresh control circuit 6 and a display read request from the display timing control circuit 5, and then performs the next operation. Exclusively determines the memory cycle. This determination result is notified to the data control circuit 22, the address control circuit 23, and the timing control circuit 24, and the operation of each circuit is designated. When accepting the refresh request, the access arbitration circuit 21 sends an acknowledge signal to the refresh control circuit 6 to notify that the refresh request has been accepted.

The data control circuit 22 includes the frame memory 1
The display unit 7 is connected to the display unit 7 to write data from a device such as a CPU and read display data from the display unit 7. The read display data is sent to the display buffer 25.

The address control circuit 23 receives access address information from these devices in the case of access from devices such as a CPU. In the case of display reading, the display read address information is received from the display timing control circuit 5 and an access address to the frame memory 1 is generated.

The display data read into the display buffer 25 is output to the display unit 7 at regular intervals according to an instruction from the display timing control circuit 5.

Referring to FIG. 3, the display timing control circuit 5 includes a clock generation circuit 51, an X counter 52, and
It is composed of a Y counter 53 and a display comparison circuit 54.

The clock generation circuit 51 generates a clock signal for displaying on the display section 7. The clock signal generated by the clock generation circuit 51 is supplied as a clock for synchronous operation of the X counter 52 and the Y counter 53.

The X counter 52 is a clock generation circuit 51.
The current horizontal display position on the display unit 7 is determined by counting the clock signals from the.

The Y counter 53 determines the current vertical display position on the display unit 7 by counting the signal from the X counter 52.

The display comparison circuit 54 includes an X counter 52 and a Y counter.
The horizontal display position and the vertical display position output from the counter 53 are compared with various predetermined timing values. From the result of this comparison, a horizontal synchronizing signal, a vertical synchronizing signal, and a blanking signal indicating whether or not it is the display timing at the current display unit 7 are generated,
To send to. The blanking signal is also sent to the refresh control circuit 6 and used for determining whether or not the refresh request should be suppressed. The display comparison circuit 54 also generates a display read request signal that determines the timing of display data read from the frame memory 1 to the display buffer 25 and a display address that indicates the address of the data stored in the frame memory 1 and stores the display address. Output to the control circuit 2. The display comparison circuit 54 generates a display output signal that determines the timing of display readout from the display buffer 25 to the display unit 7, and outputs it to the memory control circuit 2.

Referring to FIG. 4, the blanking signal 500 generated in the display comparison circuit 54 is used to erase the horizontal blanking line and the vertical blanking line,
It shows whether or not it is the timing to display the present display unit 7. The blanking signal 500 has a vertical non-display period V.
b and the vertical display period Vd. The vertical display period Vd is
It consists of a horizontal non-display period Hb and a horizontal display period Hd. The vertical blanking period is erased during the vertical non-display period Vb, and no display is made on the display unit 7 during this period. The horizontal display period Hd is a period during which the screen is displayed, and the horizontal non-display period Hb is a period during which the screen is not displayed. Therefore, the blanking signal 500 is used as a signal for determining which of the display period and the non-display period is being performed on the display unit 7. The horizontal sync signal 501 includes a plurality of horizontal sync periods Hs. The vertical synchronization signal 502 is a signal that gives a display start timing on the display unit 7, and one frame is displayed during the vertical cycle V.

Referring to FIG. 5, A is an enlarged view of A in FIG. The horizontal synchronization signal 501 is a signal that gives a display start timing on the display unit 7, and one horizontal line is displayed during the horizontal period H. Display output signal 503
Is a signal that gives the timing of transmitting display data from the display buffer 25 to the display unit 7.

Referring to FIG. 6, the refresh hold circuit 4 comprises a counter 41 for counting the number of refresh hold times. The counter 41 is initialized at the time of system reset and counts up by one each time the refresh request signal from the refresh request circuit 3 is received. One is counted down by the subtraction signal from the refresh control circuit 6.

Referring to FIG. 7, the refresh control circuit 6 includes a comparator 61 for determining whether or not a refresh request is held, and a logic circuit 62 for sending a refresh request signal to the memory control circuit 2 during a non-display period. Composed of and.

The comparator 61 compares the number of times the refresh is held sent from the refresh holding circuit 4 with 0, and when it matches with 0, sends a match signal to the logic circuit 62.

The logic circuit 62 receives the refresh request signal to be output to the memory control circuit 2 and the subtraction signal to be output to the refresh hold circuit 4 from the coincidence signal from the comparator 61 and the blanking signal 500 from the display timing control circuit 5. To generate. When the coincidence signal is sent from the comparator 61 when the blanking signal 500 is in either the horizontal non-display period Hb or the vertical non-display period Vb, the logic circuit 62 causes the memory control circuit 2 to refresh the request signal. Is sent to the refresh hold circuit 4. The logic circuit 62 waits until it receives an acknowledge signal from the memory control circuit 2, and continues to hold the refresh request state. When the acknowledge signal is received,
The logic circuit 62 again uses the coincidence signal from the comparator 61 and the blanking signal 500 from the display timing control circuit 5 to determine whether or not to send the refresh request, and repeats a series of operations. Blanking signal 500
However, when the horizontal display period Hd is indicated, the logic circuit 62 does not send the refresh request signal even if the coincidence signal is sent from the comparator 61, and functions to suppress the refresh request.

Next, the operation of one embodiment of the display device of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 6, when the counter 41 of the refresh hold circuit 4 receives the refresh request signal from the refresh request circuit 3, the counter 41 counts up the number of refresh hold times by one. Each time the counter 41 receives the refresh request signal, the counter 41 continues to count up the number of holdings and sends the number of holdings to the refresh control circuit 6.

Referring to FIG. 7, in the refresh control circuit 6, whether or not the refresh request is suspended is determined by the comparator 61 receiving the suspension count and determining whether or not the suspension count is 0. Make a decision. When the number of holding times is 1 or more and the refresh operation is held, the comparator 61 sends a coincidence signal to the logic circuit 62.

When receiving the coincidence signal from the comparator 61, the logic circuit 62 sends a refresh request signal to the memory control circuit 2 when the blanking signal from the display timing control circuit 5 indicates the non-display period. Then, the reduction signal is sent to the refresh holding circuit 4. Logic circuit 62
When the refresh request signal is sent, the device keeps the refresh request state until the memory control circuit 2 returns an acknowledge signal. When the acknowledge signal is returned from the memory control circuit 2, the logic circuit 62 again determines that the refresh hold count is 0 from the coincidence signal from the comparator 61 and the blanking signal from the display timing control circuit 5.
It is determined whether it is not the non-display period and the refresh request signal and the subtraction signal are output.

Referring to FIG. 6, the counter 41 of the refresh holding circuit 4 decrements the held number of refresh holdings by one when receiving the subtraction signal.

Referring to FIG. 2, the refresh request from the refresh control circuit 6 is sent to the access arbitration circuit 21 of the memory control circuit 2. Access arbitration circuit 21
Arbitrates the refresh request, the access request to the frame memory 1 from a device such as a CPU, and the display read request from the display timing control circuit 5. At this time, the refresh request or the display read request from the display timing control circuit 5 is prioritized over the access request to the frame memory 1 from a device such as a CPU. The refresh request and the display read request from the display timing control circuit 5 do not conflict with each other. This is because the refresh request is sent during the non-display period. The request arbitrated by the access arbitration circuit 21 is sent to the data control circuit 22, the address control circuit 23, and the timing control circuit 24. Further, when the access arbitration circuit 21 receives the refresh request from the refresh control circuit 6, the access arbitration circuit 21 sends an acknowledge signal to the refresh control circuit 6 to notify that the refresh request has been received. The timing control circuit 24 generates the timing necessary for accessing the frame memory 1. With this timing, the address control circuit 2
3 to the address of the frame memory 1 generated by No. 3 via the data control circuit 22
Data is written to or read from.

Referring to FIG. 8, the blanking signal 70
0 corresponds to the IBM-VGA display standard. I
According to the BM-VGA display standard, the horizontal cycle is about 31.78μ.
sec, and the horizontal blanking period is about 6.36 μs.
ec, the horizontal display period is about 25.42 μsec.

DRA used as a frame memory
In order to hold the data of M, 102 within 16 msec.
If four refresh operations are required, one refresh operation is required every 15.625 μsec on average. The memory cycle 701 is a case where the refresh operation is executed a fixed number of times during the horizontal non-display period according to the conventional example. According to the IBM-VGA display standard, three refresh operations must be performed during the horizontal period, so that three refresh operations are always performed during the horizontal non-display period. The memory cycle 702 is a memory cycle by the display device of the present invention, and the refresh request signal from the refresh request circuit 3 is 15.625.
It is generated in a cycle of μsec, and refresh operation is executed twice or three times in one horizontal non-display period, and 16 msec.
When viewed in the period of, it is possible to make the number of times of refresh necessary and small.

As described above, according to the display device of one embodiment of the present invention, it is determined whether or not the display period is in progress by using the blanking signal, and if the display period is in progress, the display readout is prioritized. The refresh request is suppressed. Therefore, it is possible to secure a sufficient time for display readout during the display period and obtain high display performance.

Further, according to the present invention, the memory refresh request is held and the number of the held refresh requests is held in the counter 41. The refresh operation for the number of times that has been held is performed during the non-display period. For this reason, only the minimum number of refresh operations required for the memory is required, so that the time allocated to other accesses to the memory such as data writing can be sufficiently secured, and the memory access performance is improved.

[0045]

As is apparent from the above description, according to the present invention, the display read request is prioritized and the memory refresh request is suspended during the display period. Therefore, it is possible to secure a sufficient time for display readout during the display period and obtain high display performance.

Further, according to the present invention, the reserved number of memory refresh operations are performed in the non-display period.
As a result, only the number of refresh operations requested by the refresh request circuit is required, so that the refresh operation can be minimized. Therefore, the time allocated to other accesses to the memory such as data writing can be sufficiently secured, and the memory access performance is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a display device of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory control circuit 2 according to an embodiment of the present invention.

FIG. 3 is a display timing control circuit 5 according to an embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 4 is a diagram showing an example of a control signal according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a control signal according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a refresh hold circuit 4 according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a refresh control circuit 6 according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a memory cycle of a display device according to an embodiment of the present invention.

[Explanation of symbols]

 1 frame memory 2 memory control circuit 3 refresh request circuit 4 refresh hold circuit 5 display timing control circuit 6 refresh control circuit 7 display unit

Claims (7)

[Claims] 1. A display request generating means for generating a display request for displaying a frame memory and a screen, and a refresh request generating means for generating a refresh request for holding data, wherein the display request and the refresh request are In a display device sent to the frame memory through the same port, a display period detection unit that detects whether the screen display period or the screen non-display period, and the display period detection unit detects the screen display period. And a suppression unit that suppresses the refresh request. 2. The display request and the refresh request include a frame memory, a display request generating unit for generating a display request for screen display, and a refresh request generating unit for generating a refresh request for holding data. In a display device that is sent to the frame memory through the same port, a display period detection unit that detects whether the screen display period or the screen non-display period, and the display period detection unit is the screen display period. Holding means for holding the refresh request when it is detected, and refresh for sequentially sending the refresh request held by the holding means when the display period detecting means detects the screen non-display period Based on the request sending means and the refresh request from this refresh request sending means Display device which comprises a memory access means to execute the refresh operation for the serial frame memory. 3. The holding means includes a counter that counts the number of times the refresh request is held, and the refresh request sending means sequentially outputs refresh requests for the number of holding times stored in the counter. The display device according to claim 2, further comprising: 4. A display unit in which the contents of the frame memory are displayed includes a horizontal non-display period indicating a horizontal blanking non-display period and a vertical non-display period indicating a vertical blanking non-display period. A blanking signal supply means for supplying a blanking signal, wherein the display period detecting means detects whether the screen display period or the screen non-display period is based on the blanking signal. The display device according to claim 1 or 2. 5. The display period detecting means detects that the blanking signal is in the screen non-display period when the blanking signal is in the horizontal non-display period.
The display device according to the above. 6. The display period detecting means detects that the blanking signal is in the screen non-display period when the blanking signal is in the vertical non-display period.
The display device according to the above. 7. The display period detection means detects that the screen non-display period is either a horizontal non-display period or a vertical non-display period of the blanking signal. Item 4. The display device according to item 4.