JPH10283303A - Picture processor and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture processor in which the deterioration of the performance of CPU access can be minimized even during video input in a graphic board with a video input function (a graphic board with a video capture function). SOLUTION: This device is constituted of a picture memory circuit, picture memory control circuit which executes a read/write/refresh cycle to this picture memory circuit, and arbiter circuit 1 which arbitrates an access request for the picture memory circuit. The arbiter circuit 1 incorporates a selection storage circuit 4 which holds data indicating whether or not access is performed to the picture memory circuit and a priority order deciding circuit 5 which decides the priority order of access to the picture memory circuit. The priority order at the time of selecting access to the picture memory circuit is changed according to the content of the selection storage circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image processing apparatus such as a graphic board of a computer, which is capable of minimizing a decrease in performance of CPU access despite executing video input. The present invention relates to an image processing technique for the purpose of suppressing.

[0002]

2. Description of the Related Art In a graphic board with a video input function typified by a personal computer or the like (a graphic board with a video capture function), a refresh cycle request, a CPU access request, a video input cycle request, And various access requests such as a read cycle request for screen display.

[0003] The request signal will be described below. The refresh cycle request signal (hereinafter REF_REQ) is a signal for generating a refresh cycle for retaining data of the image memory circuit (RDRAM). Video input cycle request signal (hereinafter, VDO_REQ)
Is a signal for requesting generation of a write cycle for writing a video image to an image memory circuit (RDRAM).

A read cycle request signal for screen display (hereinafter referred to as DSP_REQ) is a read signal for displaying data of an image memory circuit (RDRAM) on a display screen.
This is a signal for requesting generation of a cycle. Then, a CPU access request signal (hereinafter, CPU_REQ)
Is a signal for requesting generation of a read / write cycle for rewriting data of an image memory circuit (RDRAM) in accordance with movement of a mouse cursor, movement of a window, and the like.

Generally, (1) a refresh cycle,
The priority is set for the access request in the order of (2) video input cycle, (3) screen display read cycle, and (4) CPU access cycle, thereby configuring the system.

[0006] The following contents are taken into consideration in determining the priority order. (1) Refresh Cycle If this cycle is not executed properly, the top priority is given to the contents of the image memory circuit (RDRAM) because they are not guaranteed (data is not held). (2) Video input cycle When a write request occurs, it is desirable to write immediately. This is because a write error occurs if the video input cycle is made to wait. (3) Read cycle for screen display A cycle request is periodically generated, and a normal screen is not displayed on the display unless the read cycle is executed. (4) CPU access cycle An access request occurs when screen processing is required.

[0007] In addition, the cycle of each cycle will be described. A refresh cycle is once every 30 μs, a video input cycle is once every 10 μs (in the case of NTSC),
The read cycle for screen display is once every 1 ms (HDTV
), And the CPU access cycle is irregular.

FIG. 4 shows an RDRAM cycle in an example of a conventional image processing apparatus. For the refresh cycle (FIG. 4: REF-1), all request signals (REF_REQ, VDO_REQ, D
When SP_REQ and CPU_SEL occur simultaneously, the refresh cycle (R
EF-1) is selected.

Video input cycle (FIG. 4: VDO-2)
When the refresh cycle is completed, the video input cycle (VDO-2) having the second priority is selected. Read cycle for screen display (Figure 4: DSP-
Regarding 3), when the video input cycle is completed, the request signal becomes the DSP_REQ signal and the CPU_REQ signal, and the read cycle for screen display (DSP-3) is selected.

Video input cycle (FIG. 4: VDO-4)
When the read cycle for screen display is completed, the request signal includes the VDO_REQ signal and the CPU_REQ signal.
As a signal, the video input cycle (VDO-4) is selected.

In the same manner, the video input cycle and the screen display read cycle are alternately selected, and the CPU accesses until the screen display read cycle disappears (until the blanking period) or It is not selected until there is no video input (a blanking period or until video input is stopped).

In the case of the above-mentioned system, while video input is being performed, problems such as slow access to the CPU and inputting a high-resolution video signal cause a problem such as a flickering display screen.

[0013]

By the way, in the above-described system, if the CPU access becomes slow or a high-resolution video signal is input during the video input, the display screen is flickered. Problems such as sticking occur. This is because, since the priority of memory access is fixed, if an access having a high priority (in this case, video input) frequently occurs, other accesses are not selected. In view of the above, the present invention has been made in view of the above points. Even when the video input is operated, the flickering of the display screen and the performance of CPU access are performed.
It is an object of the present invention to provide an image processing apparatus capable of minimizing a decrease in the performance.

[0014]

According to the present invention, as a means for achieving the above object, the priorities of access requests to an image memory circuit are dynamically controlled so that each access request can be uniformly selected. It is intended to provide a possible image processing device.

That is, according to the present invention, an image memory circuit, an image memory control circuit for executing a read / write / refresh cycle to the image memory circuit, and arbitration of an access request to the image memory circuit. Sure
In an image processing apparatus comprising a biter circuit, the arbiter circuit determines a priority of access to the image memory circuit and a selection storage circuit for holding data as to whether or not the image memory circuit has been accessed. An image processing apparatus is provided which incorporates a priority determining circuit for determining the priority, and changes the priority when selecting access to the image memory circuit in accordance with the contents of the selected storage circuit.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the priority when selecting the memory access is determined when the selection storage circuit selects a video input cycle request signal. The present invention provides an image processing apparatus wherein the priority determination circuit lowers the priority of the next video input cycle request signal so that another access request signal is selected.

According to a third aspect of the present invention, there is provided an image memory means, an image memory control means for executing a read / write / refresh cycle to the image memory means, and an arbiter means for arbitrating an access request to the memory means. In the image processing method, the arbiter means includes a selection storage means for holding data indicating whether or not the image memory means has been accessed, and a priority determination means for determining a priority of memory access. There is provided an image processing method which is built-in and changes a priority when memory access is selected according to the contents of the selection storage means.

According to a fourth aspect of the present invention, in the image processing method according to the third aspect, the priority when the memory access is selected is determined when the selection storage means selects a video input cycle request signal. Provides an image processing method in which the priority determining means lowers the priority of the next video input cycle request signal so that another access request signal is selected.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention. FIG. 1 is a configuration diagram of an embodiment of the image processing apparatus of the present invention. The image processing apparatus 10 of the present invention includes an arbiter circuit 1, an image memory control circuit 2, and an image memory circuit (Rambus DRAM: hereinafter referred to as RDRAM) 3.

The arbiter circuit 1 has a refresh cycle request signal (hereinafter, referred to as REF_REQ), a video input request signal (hereinafter, referred to as VDO_REQ), and a read request signal for screen display (hereinafter, referred to as DSP_REQ). , C
PU access request signal (hereinafter referred to as CPU_REQ)
, A refresh selection signal (hereinafter, referred to as REF_SEL), a video selection signal (hereinafter, referred to as VDO_SEL), a screen display selection signal (hereinafter, referred to as DSP_SEL), and a CPU selection signal (hereinafter, referred to as DSP_SEL). (Hereinafter, referred to as CPU_SEL).

The image memory control circuit 2 comprises an arbiter circuit 1
A selection signal output from the memory is detected, a command is generated from the selected access address line and data line, and data transfer to the image memory circuit (RDRAM) 3 is executed. The image memory circuit (RDRAM) 3 executes data transfer in response to a command (read / write / refresh, etc.) from the image memory control circuit 2.

FIG. 2 is a block diagram showing the inside of the arbiter circuit 1. The arbiter circuit 1 outputs the VDO_SEL signal, C
It comprises a selection storage circuit 4 to which a PU_SEL signal is supplied, and a priority determination circuit 5 to which a video cycle holding signal (hereinafter, VDO_HLD) is supplied. When the VDO_SEL signal is supplied and detected, the selection storage circuit 4 outputs a video cycle holding signal (hereinafter, VDO_HLD) to the priority determination circuit 5.

That is, when a video input request occurs and a video input cycle is selected, a VDO_HLD signal is output. The VDO_HLD signal is output from the CPU_S
Held until the EL signal is supplied and detected (C
It is held until the PU access cycle is executed.)

The priority determining circuit 5 supplies each of the supplied request signals (REF_REQ, VDO_REQ, DSP_RE
Q, CPU_REQ), and outputs a selection signal according to the input request signal. The priority of the selection signal is determined by: (A) VDO_HLD
When no signal is input, (1) REF_RE
Q, (2) VDO_REQ, (3) DSP_REQ,
(4) Follow the order of CPU_REQ.

The priority determination circuit 5 determines (B) VDO_H
When the LD signal is input, (1) REF_RE
Q, (2) DSP_REQ, (3) CPU_REQ,
(4) The order is VDO_REQ, with VDO_REQ last.

FIG. 3 shows an actual image memory circuit (RDRA).
3 shows a timing chart of each access cycle of M) 3. FIG. 3 shows a cycle of the RDRAM in the image processing apparatus. For the refresh cycle (FIG. 3: REF-1), all the request signals (R
EF_REQ, VDO_REQ, DSP_REQ, CP
When (U_REQ) occurs simultaneously, the refresh cycle (REF-1) having the highest priority is selected.

Video input cycle (FIG. 3: VDO-2)
When this refresh cycle is completed, the video input cycle (VDO-2) having the second priority is selected. Read cycle for screen display (Figure 3: DSP
With respect to (-3), when the video input cycle ends, the request signals become DSP_REQ and CPU_REQ, and the read cycle for screen display (DSP-3) is selected.

With respect to the CPU access (FIG. 3: CPU-4), when the screen display read cycle ends, the access requests are VDO_REQ and CPU_REQ.
Since VDO_HLD is output, CPU access (CPU-4) is selected.

Video input cycle (FIG. 3: VDO-5)
When CPU access ends, VDO_HL
Since D is not output, the priority of VDO_REQ becomes higher, and the video input cycle (VDO-5) is selected.

Thereafter, each cycle of the video input and the screen display read is alternately selected. Therefore, it is possible to provide an image processing apparatus capable of minimizing the flicker of the display screen and the deterioration of the performance of the CPU access even when the video input is operated.

[0031]

As described above, according to the present invention,
In a graphic board with a video input function typified by a personal computer or the like (a graphic board with a video capture function), the selection right does not concentrate only on a specific access request.
This has the effect of minimizing the reduction in performance of screen display leads and CPU access.

Thus, according to the present invention, by dynamically controlling the priority of access requests to the image memory, it is possible to perform image processing (video capture) in which each access request can be equally selected. I can do it.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a configuration diagram showing an embodiment of the image processing apparatus of the present invention.

FIG. 3 is a timing chart showing a memory cycle of the image processing apparatus of the present invention.

FIG. 4 is a timing chart illustrating a memory cycle of an example of a conventional image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Arbiter circuit (means) 2 Image memory control circuit (means) 3 Image memory circuit (means) 4 Selection storage circuit (means) 5 Priority determination circuit (means) 10 Image processing device

Claims (4)

[Claims] An image memory circuit, an image memory control circuit for executing a read / write / refresh cycle to the image memory circuit, and an arbiter circuit for arbitrating an access request to the image memory circuit. An arbiter circuit for storing data indicating whether or not the image memory circuit has been accessed; and a priority determining circuit for determining a priority order of access to the image memory circuit. Wherein the priority when selecting access to the image memory circuit is changed according to the contents of the selected storage circuit. 2. The image processing device according to claim 1, wherein the priority when selecting said memory access is determined, and said priority determining circuit is selected when said selection storage circuit selects a video input cycle request signal. An image processing apparatus wherein the priority of the next video input cycle request signal is lowered so that another access request signal is selected. 3. An image processing method comprising image memory means, image memory control means for executing a read / write / refresh cycle to the image memory means, and arbiter means for arbitrating an access request to the memory means. Wherein said arbiter means includes a selection storage means for holding data as to whether said image memory means has been accessed and a priority determination means for determining memory access priorities, and selects memory access. The image processing method according to claim 1, wherein the priority order of the image data is changed according to the contents of the selection storage means. 4. The image processing method according to claim 3, wherein a priority when said memory access is selected, and said priority determining means when said selection storage means selects a video input cycle request signal. Wherein the priority of the next video input cycle request signal is lowered so that another access request signal is selected.