JP2000181432A - Graphic processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To place respective circuits in correct operation by guaranteeing memory access time in the worst case for circuits which need to finish processes within a prescribed time without fail when an integrated memory system is employed. SOLUTION: A bus control circuit 200 performs bus arbitration while sequentially switching a priority decision circuit A210 and a priority decision circuit B220 which differ in priority in bus arbitration timing. Consequently, even when circuits which need to gain memory access within the prescribed time without fail like a display circuit 340 and a video input circuit 330 are incorporated, the memory access time can be guaranteed even in the worst case for the respective circuit, so the circuits can be placed in correct operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic processing apparatus for generating and displaying character and graphic data, and more particularly to an integrated processing apparatus for integrating a frame buffer for storing pixel data for display in a main storage device. More specifically, the present invention relates to a graphic processing device configured by a generalized memory system.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 4-1084192 discloses an example of a graphics processing apparatus constituted by an integrated memory system according to the prior art.
No., published in Japanese Unexamined Patent Publication No. In this method, when the display circuit wants to access the memory in preference to another circuit, a priority control signal is provided to notify the memory management unit of the priority, and the memory management unit displays when the priority control signal is input. This is a method in which the control for increasing the priority of memory access of the circuit is performed without interrupting the screen display on a CRT or the like even if memory access competition increases due to memory integration.

[0003]

In the above-mentioned technique, a circuit which needs to complete processing within a certain prescribed time is provided with a priority control signal as means for preferentially performing memory access. However, the above-mentioned invention does not describe a configuration in which there are a plurality of circuits that need to complete processing within a certain specified time. For example, considering a configuration in which a display circuit and a video input circuit are provided as circuits that need to complete processing within a certain specified time,
The display circuit needs to read the display data from the memory so that the display on the CRT is not interrupted. On the other hand, the video input circuit also needs to write the video input data to the memory so as not to miss the video data that is always input. is there. That is, the display circuit needs to read all display data for one screen from the memory within the time for displaying one screen. Similarly, the video input circuit also needs to read one screen within the time for inputting one screen of video input data. All video input data needs to be written to memory.

SUMMARY OF THE INVENTION An object of the present invention is to provide a graphic processing apparatus employing an integrated memory system and having a plurality of circuits which must complete processing within a certain specified time. Is to guarantee the worst-case memory access time for a plurality of circuits that need to be terminated, thereby operating each circuit correctly.

[0005]

SUMMARY OF THE INVENTION In the present invention, the above-mentioned object is to arbitrate a CPU connected to a bus for accessing a memory, a display control circuit, and a processing circuit which must terminate processing within a specified time. In addition, this is achieved by using a plurality of priority determination circuits having different priorities.

That is, by switching between the priority determination circuit that gives priority to the CPU, the priority determination circuit that gives priority to the display control circuit, and the priority determination circuit that gives priority to the processing circuit, the respective circuits are stored in the memory within a predetermined time. It becomes possible to access.

[0007]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an overall configuration diagram of a first embodiment of the present invention. In FIG. 1, 100 is a graphics processor, 110 is an internal bus, 200 is a bus control circuit, 21
0 is a priority determination circuit A, 220 is a priority determination circuit B, 2
40 is a bus control sequencer, 310 is a CPU I / F circuit, 320 is a drawing circuit, 330 is a video input circuit, 34
0 is a display circuit, 500 is a CPU, 510 is an I / O controller, 520 is a CDROM, 530 is a keyboard, 5
40 is a mouse, 550 is a CPU bus, 600 is an NTSC decoder, 610 is an antenna, 620 is a DAC, 630 is a CRT, 700 is a memory, 710 is a main memory, 720 is drawing data, 730 is video input data, and 740 is a frame. It is a buffer.

In FIG. 1, a main memory 710 is an area for holding programs, data, work areas, and the like necessary for the operation of the CPU 500, and the drawing data 720 is a drawing circuit.
320 is an area for holding commands, data, work areas, and the like necessary for operating the video input data 730.
Is an area for holding video input data created by the video input circuit 330, and is a frame buffer 740.
Is an area for holding display data to be read by the display circuit 340 and displayed on the CRT 630. Each circuit in the graphics processor 100 will be described below. C
When receiving a request to access the memory 700 from the CPU 500, the PU I / F circuit 310 outputs a request 311 to the bus control circuit 200 to acquire the bus right of the internal bus 110. The CPU I / F circuit 310 is connected to the bus control circuit 20.
In response to the output of the acknowledge 312 from 0, the memory 700 is accessed through the internal bus 110,
If the access content from the CPU 500 is a read access, the data read from the memory 700 is transferred to the CPU bus 550.
The data is transferred to the CPU 500 via the CPU 500, and the data is written to the memory 700 for write access. Drawing circuit 3
20 reads out a drawing command from the drawing data 720, creates graphic drawing data, and writes it to the frame buffer 740. When the drawing circuit 320 needs to read a drawing command or write the created graphic drawing data during the execution of the drawing process, the request 32
The memory 700 is accessed using 1 and the acknowledge 322. The video input circuit 330 reads the video data converted into digital data by the NTSC decoder 600 after being received by the antenna 610. The video input circuit 330 temporarily stores the input video data in a buffer, and outputs the data to the memory 700 using the request 331 and the acknowledge 332 before the buffer becomes full. Since the NTSC decoder 600 continuously outputs video data, the video input circuit 330 must always output data to the memory within a fixed time so as not to miss the data. The display circuit 340 reads display data and video input data from the memory 700,
Output to CRT630 through DAC620. The display circuit 340 is CR
In order not to interrupt the screen display on the T630,
The display data and the video input data need to be read from the memory 700 in accordance with the screen display. The display circuit 340
These data to be output to the CRT630 are temporarily stored in an internal buffer and output to the CRT630.However, these data must be stored in a fixed time according to the sweep frequency of the CRT630 so that the data in the buffer is not lost. Must be read from In the bus control circuit 200, the display circuit 340 has the highest priority judgment circuit A210 and the video input circuit 330 has the highest priority judgment circuit B220 in the bus arbitration of the internal bus 110. The priority determination circuit A210 and the priority determination circuit B220 determine the access request from the highest priority circuit among the received requests 311 to 341 in the determination results 211 and 221.
Respectively. For example, when the request 311 and the request 341 are output at the same time, the priority determination circuit A210 determines that the display circuit 34
0 indicates that a memory access request has been output,
The priority determination circuit B220 outputs the determination result 221 to the CPU.
It outputs that I / F circuit 310 is outputting a memory access request. The bus control sequencer 240 outputs acknowledgments 312 to 342 using the determination results 211 and 221 to permit use of the internal bus 110. At this time, when the bus control sequencer 240 uses the determination result 211, that is, the output value of the priority determination circuit A 210, for the bus arbitration at a certain timing, the bus control sequencer 240 determines the determination result 221, that is, the output of the priority determination circuit B 220 at the next bus arbitration timing. A value is used, and at the next bus arbitration timing, the determination result 211, that is, the output value of the priority determination circuit A210 is used. At this time, for example, the maximum value of the memory access time of the display circuit 340 can be obtained as follows.

The maximum value of the memory access time of the display circuit 340 = (the time during which the display circuit 340 cannot output the request 341 in time for performing the bus arbitration using the determination result 211 and the memory cannot be accessed) + (the determination result 2
Processing time of bus arbitration using 21) + (judgment result 221)
(The maximum value of the memory access time when a circuit having a higher priority than the display circuit 340 accesses the memory by the bus arbitration using), (the bus arbitration processing time using the second determination result 211) + (the second time) That is, the worst case memory access time of the display circuit 340 in this case is determined by the bus arbitration using the determination result 211 (= the priority of the display circuit 340). When performing the bus arbitration with the highest degree, the display circuit 340 cannot obtain the bus right because it cannot output the memory access request in time, and the bus arbitration using the subsequent determination result 221 (= the video input circuit 33)
When performing a bus arbitration having the highest priority of 0), the display circuit 340 cannot take the bus right because a memory access request is output from a circuit having a higher priority than the display circuit 340. Eventually, this is the case where the bus right can be finally acquired and the memory access can be executed by the bus arbitration using the second determination result 211. The maximum value of the memory access time can be similarly obtained for the video input circuit 330.

As described above, the display circuit 340 has the highest priority determination circuit A210 and the video input circuit 3
The bus arbitration is performed by switching and using the priority determination circuit B 220 having the highest priority every time the bus arbitration is performed, so that the memory is always stored within a specified time, such as the display circuit 340 or the video input circuit 330. Even when a plurality of circuits that need to be accessed are built in, the worst case memory access time can be guaranteed for each circuit, so that each circuit can operate properly. FIG. 2 shows the priority determination circuits A210 and B in FIG.
An example of setting the priority of 220 is shown.

FIG. 3 shows the bus control sequencer 2 in FIG.
FIG. 40 shows a state transition diagram 40. In FIG. 3, the display circuit priority bus arbitration is a bus arbitration using the determination result 211, and the video input circuit priority bus arbitration is a bus arbitration using the determination result 221.

In FIG. 3, when the display circuit priority bus arbitration is performed, the bus control sequencer 240 makes a state transition using the judgment result 211. In this case, for example, request 34
If 1 is set, the display circuit 340 is made to execute memory access, and after the memory access of the display circuit 340 is completed, the state transition is made to the video input circuit priority bus arbitration. If none of the requests 311 to 341 are set, the bus right is not given to any circuit, and the state immediately transitions to the next video input circuit priority bus arbitration. When performing video input circuit priority bus arbitration, the bus control sequencer 240 makes a state transition using the determination result 221. In this case, for example, if the request 331 is set, the video input circuit 330 is made to execute memory access, and after the memory access of the video input circuit 330 is completed, the state transition is made to the display circuit priority bus arbitration. If none of the requests 311 to 341 is set, the bus right is not passed to any circuit, and the state immediately transits to the next display circuit priority bus arbitration.

FIG. 4 shows a time chart of memory access of the display circuit 340 in FIG.

In FIG. 4, the number of cycles for executing the bus arbitration is one, and the CPU I / F circuit 310 and the drawing circuit 3
20, the video input circuit 330, and the display circuit 340 perform the memory access cycles Tc, Tr, and T, respectively.
v and Td. The number of memory access cycles of the display circuit 340 in this case is as follows.

The number of memory access cycles of the display circuit 340 = (When the display circuit 340 outputs the request 341 when the display circuit priority bus arbitration is performed, the display is performed by the CPU I / F circuit 310 performing the memory access. (Number of cycles in which circuit 340 cannot access memory) + (Number of cycles for performing video input circuit priority arbitration) + (Number of cycles for memory access of video input circuit 330) + (Number of cycles for performing second display circuit priority bus arbitration) + ( The number of memory access cycles of the display circuit 340) = Tc + 1 + Tv + 1 + Td = Tc + Tv + Td + 2 Considering the same, the worst value of the number of memory access cycles of the display circuit 340 is that the memory access request from the display circuit 340 cannot be made when the display circuit priority arbitration is performed. Cycles waited for Since the video input circuit priority arbitration is the sum of the number of cycles to wait for a circuit having higher priority than the display circuit 340 to output the memory access request and the number of cycles for executing bus arbitration, the display circuit 340 Worst value of the number of memory access cycles of: = (the longest number of memory access cycles when another circuit accesses the memory because the display circuit 340 cannot output the request 341 when the display circuit priority bus arbitration is performed) + (Number of cycles for performing video input circuit priority arbitration) + (Longest memory access cycle number when a circuit with higher priority than display circuit 340 accesses memory due to video input circuit priority arbitration) + (Second display circuit priority) Number of cycles for performing bus arbitration) + (Number of memory access cycles of display circuit 340) = max (Tc Tr, Tv) +1 + max (Tv, Tc, Tr) + 1 + Td = max (Tc, Tr, Tv) + max (Tv, Tc, Tr) + the Td + 2. Here, max (T1, T2,...) Is T1, T2,
It is a function that returns the maximum value from ... Video input circuit 3
Similarly, the worst value of the number of memory access cycles for 30 can be obtained.

FIG. 5 shows an overall configuration diagram of a second embodiment of the present invention. In FIG. 5, 11700 and 11800 are memories.

In FIG. 5, a memory 11800 is a memory for holding a main memory 11810, and a memory 11700 is for drawing data 11720, video input data 11730,
This is a memory that holds the frame buffer 11740.
Even in such a configuration, the bus control circuit 200 performs bus arbitration while sequentially switching a plurality of priority determination circuits having different priorities at each bus arbitration timing, thereby providing a display circuit 340 and a video input circuit 330. Even in the case where a plurality of circuits that need to perform memory access within the specified time are built in, the worst case memory access time can be guaranteed for each circuit, so that each circuit can be operated properly.

FIG. 6 shows an overall configuration diagram of a third embodiment of the present invention. Even in such a configuration, the bus control circuit 20
0 performs bus arbitration while sequentially switching a plurality of priority determination circuits having different priorities at each bus arbitration timing, so that memory access must be performed within a certain specified time as in the display circuit 340 and the video input circuit 330. Even when a plurality of circuits having the above-mentioned characteristics are incorporated, the worst case memory access time can be guaranteed for each circuit, so that each circuit can be operated correctly.

FIG. 7 shows an example of a display screen when the present invention is used. 7, reference numeral 7010 denotes a TV screen, and 7020 denotes a map screen. When the map is displayed at the same time as the TV on the car navigation system mounted on the car,
As shown in FIG. 7, a TV screen 7010 may be displayed on a map screen 7020 so as to be superimposed. In this case, the video input processing and the display processing need to be performed at the same time, and the memory access by the video input processing and the memory access by the display processing conflict. However, by using the present invention, it is necessary to correctly perform each memory access. Therefore, it is possible to prevent the image captured on the TV screen 7010 from being disturbed and the screen display from being disturbed.

[0021]

According to the present invention, the video input circuit 3
30, the worst case memory access time can be guaranteed for each circuit even when there are a plurality of circuits that must always perform memory access within a specified time, such as the graphics processor 100 including the display circuit 340. Each circuit can operate correctly.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is a setting example of priorities of a priority determination circuit A210 and a priority determination circuit B220 in FIG.

FIG. 3 is a state transition diagram of a bus control sequencer 240 in FIG.

FIG. 4 is a time chart of memory access of a display circuit 340 in FIG. 1;

FIG. 5 is an overall configuration diagram of a second embodiment of the present invention.

FIG. 6 is an overall configuration diagram of a third embodiment of the present invention.

FIG. 7 is an example of a display screen when the present invention is used.

[Explanation of symbols]

100, 12100 ... graphics processor, 11
0: Internal bus, 200: Bus control circuit, 210: Priority judgment circuit A, 220: Priority judgment circuit B, 240 ... Bus control sequencer, 310: CPU I / F circuit, 320 ...
Drawing circuit, 330: video input circuit, 340: display circuit,
500,12,500 ... CPU, 510,12510 ... I
/ O controller, 520 CDROM, 530 keyboard, 540 mouse, 550, 12550 CPU
Bus, 600 NTSC decoder, 610 antenna
620: DAC, 630: CRT, 700, 1170
0, 11800, 12700... Memory, 710, 118
10, 12710 ... main memory, 720, 11720, 12
720: drawing data, 730, 11730, 1273
0: Video input data, 740, 11740, 1274
0: frame buffer, 7010: TV screen, 7020
… Map screen.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Matsuo 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yasuhiro Nakatsuka 7-1 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Kazushige Yamagishi 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Division, Hitachi, Ltd. F-term (reference) 5C082 AA02 AA22 AA24 AA37 AA39 BA02 BA12 BA27 BB03 BB13 BB15 CA55 DA53 DA86 DA87 DA89 EA12 MM02 MM10

Claims (4)

[Claims] 1. A CPU for executing an arithmetic processing, a display control circuit for controlling display data for each pixel, and at least one or more of the display control circuits, the processing must be completed within a certain specified time. A processing circuit; a memory for storing at least the operation result created by the CPU and the display data; and a bus control circuit for arbitrating the memory, wherein the bus arbitration circuit has a priority of bus arbitration. A plurality of different priority determination circuits, wherein the bus arbitration circuit performs bus arbitration using one priority determination circuit from the plurality of priority determination circuits when performing bus arbitration, and the bus arbitration circuit Wherein the bus arbitration is performed by switching the priority determination circuit to be used each time bus arbitration is performed. 2. The bus arbitration circuit according to claim 1, wherein the bus arbitration circuit performs bus arbitration while sequentially switching the priority determination circuit used in bus arbitration.
A graphic processing device characterized by the following. 3. A graphic according to claim 1, further comprising a video input control circuit for fetching video data and outputting the video data to said memory, as a processing circuit which must end the processing within said prescribed time. Processing equipment. 4. A memory for storing at least a program to be executed by the CPU and display data to be displayed, and a CPU for executing the program read from the memory.
A display control circuit for reading display data from the memory; a processing circuit for writing display data read from the outside into the memory; and the memory, the CPU, the display control circuit, and the processing circuit. A bus composed of a plurality of signal lines, a higher priority one of the CPU, the display control circuit, and the processing circuit can occupy the bus, and both of the display control and the processing circuit can operate within a predetermined time. And a bus control circuit that performs arbitration so as to occupy the bus.