JPH06332867A - Bus interface inside buffer control system - Google Patents

Abstract

PURPOSE:To avoid dead lock and to reduce circuit scale in the case of controlling an internal buffer concerning the internal buffer control system for a bus interface in a system where plural processors are connected to a common bus. CONSTITUTION:Respective buffers 17 and 18 for transmission and reception of a bus interface part 13 for connecting a common bus 12 and a local bus 14 inside the processor are provided with an area 100 for start command transfer, area 200 for response command transfer and gray zone 300 to be switched for start command transfer and response command transfer, a flag register 25 is provided for displaying the state of the gray zone 300 under use and when the area 100 for start command transfer or the area 200 for response command transfer is made full while the processor 11 is operated, the gray zone 300 is switched for start command transfer or response command transfer by raising a flag at the flag register 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system of an internal buffer for a bus interface in a system in which a plurality of processing devices are connected to a common bus via a bus interface section.

In a multiprocessor system, each processing unit has a central processing unit (CPU) and a local memory (LM) connected from a bus interface unit via a local bus, and each processing unit The devices perform the required processing while exchanging information via the common bus, whereby the processing of the entire system is performed.

In such a case, it is desired that the control method of the internal buffer in each bus interface section does not cause a deadlock even when a plurality of accesses are concentrated on a specific processing device. To be done.

[0004]

2. Description of the Related Art FIG. 10 shows a schematic configuration of a multi-processor system. Reference _numerals 11 _1, 112 _2, ... Are processing devices, and are connected to the common bus 12. Reference numeral 13 is a bus interface unit in each processing device.

FIG. 11 shows a schematic configuration of the bus interface section. Reference numeral 11 denotes a processing device. In the processing device 11, the bus interface unit 13 connects the common bus 12 and the local bus 14 inside the processing device. The local bus 14 has a CPU 15 and an LM.
16 and 16 are connected.

In the bus interface section 13, 1
Reference numeral 7 denotes a transmission buffer including a queue buffer for temporarily holding information transmitted from the local bus 14 to the common bus 12, and 18 denotes the common bus 12 to the local bus 14.
It is a receiving buffer consisting of a queue buffer that temporarily holds information to be received by.

A common bus control unit 19 has a function of connecting the common bus 12 to the transmission buffer 17 and the reception buffer 18. Reference numeral 20 denotes a local bus control unit, which includes the local bus 14 and the transmission buffer 1
7. It has a function of connecting to the receiving buffer 18.

Conventionally, in such a bus interface section, when a plurality of accesses are concentrated, a deadlock avoiding method based on the buffer fullness is as a transmission buffer, a start command transmission buffer and a response command. A transmission buffer is provided, and as a reception buffer, a start command reception buffer and a response command reception buffer are provided so that transmission / reception of a start command and transmission / reception of a response command are performed by separate buffers. There is. This is because the response command is processed more preferentially than the start command in terms of system control efficiency, so it is divided to enable such processing. Regarding such a bus interface internal buffer control method, for example, Japanese Patent Application No.
No. 104113 is disclosed in detail.

[0009]

In the conventional bus interface internal buffer control method, two buffers are required for each of the transmission buffer and the reception buffer. There is a problem in that the area of the circuit portion such as the peripheral column control decoder is large and integration is difficult.

The present invention is intended to solve such a problem of the prior art, and by allocating and using one buffer field for activation command transfer and response command transfer, The buffer for transmission and the buffer for reception are configured by using one buffer each, and it is possible to reduce the hardware scale around the buffer by enabling the interface. The purpose is to facilitate integration of the interface section.

[0011]

[Means for Solving the Problems]

(1) FIG. 1 shows the basic configuration of the present invention.
A plurality of processing devices 11 transmit buffer 17 for accumulating start commands and response commands transferred to common bus 12.
And a system for connecting the common bus 12 and the internal local bus 14 via a bus interface unit 13 having a reception buffer 18 for accumulating a start command and a response command transferred from the common bus 12. In each of the transmission buffer 17 and / or the reception buffer 18, a start command transfer area 100, a response command transfer area 200, and a gray zone 300 convertible for start command transfer and response command transfer. And a flag register 25 for indicating that the gray zone 300 is in use are provided in association with the gray zone 300.
When the activation command transfer area 100 or the response command transfer area 200 becomes full during the operation of 1, the flag register 25 is flagged to convert the gray zone 300 for the activation command transfer or the response command transfer. Even if an unused area is generated in the converted area, the converted area is maintained.

(2) A plurality of processing devices 11 are connected to a common bus 12
Buffer 17 for storing the start command and the response command transferred to the receiver, and receiving buffer 1 for storing the start command and the response command transferred from the common bus 12.
In the system in which the common bus 12 and the local bus 14 inside the bus are connected via the bus interface unit 13 including the start command transfer area, the start command transfer area is provided in each of the transmission buffers 17 and / or the reception buffers 18. 10
0, a response command transfer area 200, a gray zone 300 that can be switched between a start command transfer and a response command transfer, and a flag register 25 that indicates that the gray zone 300 is in use. Is provided, and the activation command transfer area 1 is provided while the processing device 11 is operating.
00 or the response command transfer area 200 is full, a flag is set in the flag register 25 to convert the gray zone 300 for the start command transfer or the response command transfer, and the unused area is set in the converted area. When the error occurs, the converted area is restored and the flag of the flag register 25 is restored.

(3) A plurality of processing devices 11 are connected to a common bus 12
Buffer 17 for storing the start command and the response command transferred to the receiver, and receiving buffer 1 for storing the start command and the response command transferred from the common bus 12.
In the system in which the common bus 12 and the local bus 14 inside the bus are connected via the bus interface unit 13 including the start command transfer area, the start command transfer area is provided in each of the transmission buffers 17 and / or the reception buffers 18. 10
0, a response command transfer area 200, and a gray zone 300 composed of a plurality of areas that can be switched between a start command transfer and a response command transfer, and use thereof corresponding to each area of the gray zone 300. A plurality of flag registers 25 _{1 and} 25 ₂ for displaying the inside are provided, and when the activation command transfer area 100 or the response command transfer area 200 becomes full while the processing device 11 is operating, the flag register 25 _1, A plurality of areas of 25 ₂ are sequentially flagged and the gray zone 300 is converted for each corresponding area for transfer of a start command or transfer of a response command. Even if an unused area is generated in this converted area, conversion is performed. To maintain the designated area.

(4) A plurality of processing devices 11 are connected to the common bus 12
Buffer 17 for storing the start command and the response command transferred to the receiver, and receiving buffer 1 for storing the start command and the response command transferred from the common bus 12.
In the system in which the common bus 12 and the local bus 14 inside the bus are connected via the bus interface unit 13 including the start command transfer area, the start command transfer area is provided in each of the transmission buffers 17 and / or the reception buffers 18. 10
0, a response command transfer area 200, and a gray zone 300 composed of a plurality of areas that can be switched between a start command transfer and a response command transfer, and use thereof corresponding to each area of the gray zone 300. A plurality of flag registers 25 _{1 and} 25 ₂ for displaying the inside are provided, and when the activation command transfer area 100 or the response command transfer area 200 becomes full while the processing device 11 is operating, the flag register 25 _1, 25 ₂ to convert the gray zone 300 make a sequence flag into a plurality of areas to the start command transfer or response command for the transfer for each corresponding region, when the unused area is generated in the conversion region, converted The flag register 25 _1,
Restore the flag of 25 ₂ .

[0015]

FIG. 2 is a diagram for explaining the field allocation of the buffer in the method of the present invention. In the present invention, in the transmission buffer and the reception buffer, as shown in FIG. 2, for example, an activation field is provided on the left side for activation command transfer, a response field is provided on the right side for response command transfer, and at the center. A gray zone, which is a flexible area that can be used for both the transfer of the start command and the transfer of the response command, is provided in the part.

As shown in FIG. 2, the address assignment in each field is as follows.
The activation logical address is sequentially assigned from the left, and the response logical address is sequentially assigned to the response field from the right. Both the activation logical address and the response logical address are assigned to the gray zone.

Then, when the system is in operation and the gray zone is not used, for example, when the activation field is in the full use state, a signal is written in the flag in the flag register to activate the gray zone. Field to extend the activation field. When the response zone becomes full when the gray zone is not used, a signal is written to the flag in the flag register to assign the gray zone to the response field and extend the response field. .

Therefore, according to the present invention, even when a plurality of accesses are concentrated, the dead error due to the fullness of the buffer is caused.
Since there is no risk of locking and it is not necessary to increase the number of buffers, it is possible to prevent an increase in space.

In this case, after the flag register is once flagged, even if an unused area occurs in the extended area, the flag register and the extended area may be left as they are, or the unused area may be left untouched. When it does occur, the flag register may be restored and the extended area returned to the gray zone. Further, the number of flag registers corresponding to the gray zone may be one or may be plural.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 illustrates the processing of the embodiment (1) of the present invention, in which (a) is a state in which there is no entry in the buffer, (b) is a full write state, and (c) is a field. The expanded states are shown respectively. In the figure, 21 is a buffer for transmission or reception, 22 is a valid / invalid display part, 23 is an original address display part, 24 is a jump destination address display part, and 25 is a flag register. Although FIG. 3 illustrates the case of the start command, the same applies to the case of the response command.

In the original address display section 23, an original address which is a starting point for expanding a field is written,
In the jump destination address display section 24, the jump destination address to be jumped from the original address is written. Further, the valid / invalid display section 22 displays the valid / invalid of the original address and the jump destination address.

For example, in the buffer 21, when the activation command is written in the activation logical address 0 of the activation field and the buffer 21 becomes full,
A 0 is written in the original address display section 23, and a boot logical address (3 in the case of FIG. 3) in which the next boot command should be written is written in the jump destination address display section 24.

When there is no entry in the buffer shown in FIG. 3A, the valid / invalid display portion 22 is invalid ("0").
Is displayed, and the original address display section 23 and the jump destination address display section 24 are blank. Also, the flag register 25 is not filled.

As shown in FIG. 3B, the start field (start), the start command (start), and the start command (start) are sequentially displayed in the start fields corresponding to the start logical addresses 0, 1, and 2 of the buffer 21. ) Is written, the boot field becomes full, and when a boot command write request occurs, as shown in FIG.
Write the signal "*" as a flag in the flag register 25 to change the gray zone to a start field,
The start command (start) is written in the start field corresponding to the start logical address 3. Further, 2 is displayed on the original address display section 23 and the jump destination address display section 24 is displayed.
Is displayed at 3 and the valid / invalid display section 22 displays valid (“1”).

FIG. 4 shows a buffer write address creating circuit in the embodiment (1) of the present invention. The buffer write address creation circuit is provided in the common bus control unit 19 and the local bus control unit 20 in FIG. The following description will be given for the case of the start command, but the same applies to the case of the response command.

In FIG. 4, 31 and 32 are gate circuits,
33 is an adder, 34 and 35 are comparators, 36 is an OR circuit,
37 is a selector. Reference numeral 38 is a starting cyclic address generation circuit for cyclically generating a starting logical address.

(A) at the input of the gate circuit 31 is
It is "1" when the signal "*" is written in the flag register 25, and "0" when it is not written.
When the start field is not expanded, the signal "*"
, The output of the gate circuit 31 is 0, and the adder 33 outputs 2. When the count value of the cyclic address generation counter in the activation cyclic address generation circuit 38 becomes 2, the comparator 34 generates an output that detects a match and outputs the OR circuit 3
A load signal is output to the cyclic address generation counter via 6.

When the activation logical address in the buffer is not jumped, the valid / invalid signal is "0".
However, the gate circuit 32 does not generate an output. Also,
When "0" is given to S0 as a valid / invalid signal,
The selector 37 selects X0, and thus 0 is output to Y as the load value of the cyclic address generation counter.

The cyclic address generation counter is reset by a load signal and is loaded with 0. Therefore, the activation cyclic address generation circuit 38 sequentially and repeatedly outputs activation logical addresses 0 to 2. .

When the activation field is expanded, the signal "*" is written in the flag register 25.
The gate circuit 31 outputs 2, and the adder 33 adds 2 to this and outputs 4. The comparator 34, when the count value of the cyclic address generation counter in the activation cyclic address generation circuit 38 becomes 4,
Since an output that detects a match is generated and given as a load signal to the cyclic address generation counter, the activation cyclic address generation circuit 38 repeatedly generates activation logical addresses 0 to 4.

Further, when the activation logical address is jumped, the valid / invalid signal becomes "1" and the original address is designated, so that the gate circuit 32 outputs the original address. Here, the original address indicates the start logical address corresponding to the start command last written in the start field when the jump of the start field is necessary. The comparator 35 performs the comparison process when the input of the enable terminal EN is “1”, and does not perform the comparison process when the input is “0”. When the valid / invalid signal is “1”, the comparator 35 generates an output when the address value of the activation cyclic address generation circuit 38 matches the original address, and the output is generated via the OR circuit 36. -Supplied as a load signal to the address generation counter.

Further, the selector 37 is enabled / disabled in S0.
When the invalid signal is "1", X1 is selected. Therefore, the jump destination address is output as the load value of the cyclic address generation counter. As a result, the activation cyclic address generation circuit 38 jumps from the original address to the jump destination address and generates the activation logical address.

For example, when there is an untransferred start command in the start logical address 2 of the start field and the start command is written in the start logical addresses 0 and 1 and a start command write request is issued, the start command is started. It is necessary to expand the use field and jump the start logical address.

In this case, since the count value of the cyclic address generation counter is changed from 0 to 2 to 0 to 4 and 1 is input as the original address and 3 is specified as the jump destination address, the activation is started. The logical address jumps from 1 and 3 and 4 are sequentially output.

After writing the flag to the flag register, even if an unused area is generated in the gray zone, the activation field may be left expanded, or if an unused area is generated. , The extended activation field may be returned to the gray zone again, and depending on the mode of concentration of access to the processing device,
You can choose either.

FIG. 5 shows a buffer read address creating circuit in the embodiment (1) of the present invention. The buffer read address creation circuit is provided in the common bus control unit 19 and the local bus control unit 20 in FIG.

In FIG. 5, 41 and 42 are gate circuits,
43 is an adder, 44 and 45 are comparators, 46 is an OR circuit,
47 is a selector. Reference numeral 48 is a starting cyclic address generating circuit for cyclically generating a starting logical address. These are the gate circuits 31 and 32, the adder 33, the comparators 34 and 35, the OR circuit 36, the selector 37 and the starting cyclic circuit shown in FIG. 4, respectively.
It has the same function as the address generation circuit 38.

The buffer read address creating circuit shown in FIG. 5 has the same structure as the buffer write address creating circuit shown in FIG. 4, and after the operation of the buffer write address creating circuit, a similar delay occurs. By performing the operation, the start command is read from the buffer.
The operation in the case of a response command is similar.

FIG. 6 is a diagram for explaining the processing of the embodiment (2) of the present invention, in which (a) is a state where there is no entry in the buffer, (b) is a full write state, and (c) is field expansion. Each state is shown. In the figure, the same elements as those in FIG. 3 are indicated by the same numbers, and 25 _{1 and} 25 ₂ are flag registers. Although the case of the start command is described in FIG. 6, the same applies to the case of the response command.

When there is no entry in the buffer shown in FIG. 6A, the valid / invalid display portion 22 is invalid ("0").
Is displayed, and the original address display section 23 and the jump destination address display section 24 are blank. Also, the flag registers 25 _{1 and} 25 ₂ are not filled.

As shown in FIG. 6B, the start field (start), the start command (start), and the start command (start) are sequentially entered in the start fields corresponding to the start logical addresses 0, 1, and 2 of the buffer 21. ) Is written, the boot field becomes full, and when a boot command write request occurs, as shown in FIG. 6C,
A signal "*" is written in the flag register 25 ₁ as a flag to change the gray zone into a field for activation, and an activation command (occurrence) is written in the field for activation corresponding to the activation logical address 3. Further, 2 is displayed on the original address display section 23, 3 is displayed on the jump destination address display section 24, and valid (“1”) is displayed on the valid / invalid display section 22.

When the flag field is set in the flag register 25 ₁ and the activation field becomes full and a request to write the activation command is issued, the state shown in FIG.
Flag register 25 ₂ as in the procedure shown in FIG.
A signal "*" is written as a flag to the field, the gray zone is changed to a field for booting, a boot command is written in the boot logical address 4, and display is performed on the original address display section 23 and the jump destination address display section 24. , Valid (“1”) is displayed on the valid / invalid display portion 22.

FIG. 7 shows a buffer write address creating circuit in the embodiment (2) of the present invention. The buffer write address creation circuit is provided in the common bus control unit 19 and the local bus control unit 20 in FIG. The following description will be given for the case of the start command, but the same applies to the case of the response command. In the figure, the same elements as those in FIG. 4 are indicated by the same numbers, and 39 is a decoder which converts a 2-bit code input into a ternary signal and outputs it.

FIG. 8 shows correspondence between input and output in the decoder. In the decoder 39, the input (1) becomes "1" when "*" is written in the flag register 25 ₁ and becomes "0" when there is no writing. The input (2) becomes "1" when "*" is written in the flag register 25 ₂ and "0" when there is no writing.
Becomes The decoder 39 responds to these input states by
It produces the output as shown in FIG.

When both the inputs (1) and (2) are "0", it corresponds to the state in which the activation field is not expanded, and the output of the decoder 39 is 0. Therefore, the adder 33 outputs 2. . When the count value of the cyclic address generation counter in the activation cyclic address generation circuit 38 becomes 2, the comparator 34 generates an output that detects a match and the cyclic circuit passes through the OR circuit 36.・
A load signal is output to the address generation counter. Subsequent operations are similar to those of the circuit shown in FIG.

Input (1) is "1" and input (2) is "0".
In this case, the adder 33 outputs 3 because the output of the decoder 39 is 1, which corresponds to the state in which the field for activation corresponding to the activation logical address 3 is extended. Comparator 34
Generates a match-detected output when the count value of the cyclic address generation counter in the activation cyclic address generation circuit 38 becomes 3,
The load signal is output to the cyclic address generation counter via the OR circuit 36. Subsequent operations are similar to those of the circuit shown in FIG.

When both the inputs (1) and (2) are "1", the output of the decoder 39 is 2 when the activation field corresponding to the activation logical address 4 is extended.
Therefore, the adder 33 outputs 4. In the comparator 34, the count value of the cyclic address generation counter in the activation cyclic address generation circuit 38 is 4
When it becomes, an output for which a match is detected is generated, and a load signal is output to the cyclic address generation counter via the OR circuit 36. Subsequent operations are similar to those of the circuit shown in FIG.

FIG. 9 shows a buffer read address creating circuit in the embodiment (2) of the present invention. The buffer read address reproducing circuit is provided in the common bus control unit 19 and the local bus control unit 20 in FIG. In the figure, the same parts as those in FIG. 5 are indicated by the same numbers, and 49 is a decoder for converting a 2-bit code input into a ternary signal and outputting it.

The buffer read address creating circuit shown in FIG. 9 has the same structure as the buffer write address creating circuit shown in FIG. 7, and after the operation of the buffer write address creating circuit, a similar delay occurs. By performing the operation, the start command is read from the buffer.
The operation in the case of a response command is similar.

In the present invention, the number of unit areas provided in the gray zone is not limited to 2 as shown in the embodiments (1) and (2), but may be arbitrary. In the case of the embodiment (2), depending on the number of unit areas provided in the gray zone,
The number of areas of the flag register may be increased.

[0051]

As described above, according to the present invention, in a system in which a plurality of processing devices are connected to a common bus via a bus interface unit, a plurality of accesses are concentrated in a specific processing device. If you do
Since the gray zone is converted and used for the transfer of the start command or the transfer of the response command, there is no possibility of causing the deadlock due to the fullness of the buffer.

In the present invention, by allocating the fields of the buffer to the start command and the response command and using them, the transmission buffer and the reception buffer are each configured by one buffer to perform the interface. Since it is possible to reduce the hardware around the buffer, it is easy to integrate the bus interface unit.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram for explaining field allocation of a buffer in the system of the present invention.

FIG. 3 is a diagram for explaining the processing of the embodiment (1) of the present invention, in which (a) is a state in which there is no entry in the buffer, and (b) is a diagram.
Indicates a full write state, and (c) indicates a field expansion state.

FIG. 4 is a diagram showing a buffer write address creation circuit in the embodiment (1) of the present invention.

FIG. 5 is a diagram showing a buffer read address creation circuit in the embodiment (1) of the present invention.

FIG. 6 is a diagram for explaining the processing of the embodiment (2) of the present invention, in which (a) is a state in which there is no entry in the buffer, and (b) is a diagram.
Indicates a full write state, and (c) indicates a field expansion state.

FIG. 7 is a diagram showing a buffer write address creation circuit in an embodiment (2) of the present invention.

FIG. 8 is a diagram showing correspondence between input and output in a decoder.

FIG. 9 is a diagram showing a buffer read address creation circuit in an embodiment (2) of the present invention.

FIG. 10 is a diagram showing a schematic configuration of a multi-processor system.

FIG. 11 is a diagram showing a schematic configuration of a bus interface unit.

[Explanation of symbols]

11 Processor 12 Common Bus 13 Bus Interface 14 Local Bus 17 Transmit Buffer 18 Receive Buffer 25 Flag Register 25 ₁ Flag Register 25 ₂ Flag Register 100 Start Command Transfer Area 200 Response Command Transfer Area 300 Gray zone

Claims (4)

[Claims] 1. A transmission buffer (17) for accumulating a start command and a response command transferred by a plurality of processing devices (11) to a common bus (12), and a start command transferred from the common bus (12). In a system in which the common bus (12) and a local bus (14) inside the common bus (12) are connected via a bus interface unit (13) including a reception buffer (18) for accumulating and a response command, In each transmission buffer (17) and / or reception buffer (18), an activation command transfer area (100),
A response command transfer area (200) and a gray zone (300) capable of converting between a start command transfer and a response command transfer are provided, and the gray zone (30
0) is provided with a flag register (25) for indicating its use, and the activation command transfer area (100) or the response command transfer area (200) is provided while the processing device (11) is operating.
Is full, a flag is set in the flag register (25) to convert the gray zone (300) for transfer of a start command or transfer of a response command, and an unused area is generated in the converted area. The bus interface internal buffer control method is characterized in that the converted area is maintained even if it is. 2. A transmission buffer (17) for storing a start command and a response command transferred to a common bus (12) by a plurality of processing devices (11), and a start command transferred from the common bus (12). In a system in which the common bus (12) and a local bus (14) inside the common bus (12) are connected via a bus interface unit (13) including a reception buffer (18) for accumulating and a response command, In each transmission buffer (17) and / or reception buffer (18), an activation command transfer area (100),
A response command transfer area (200) and a gray zone (300) capable of converting between a start command transfer and a response command transfer are provided, and the gray zone (30
0) is provided with a flag register (25) for indicating its use, and the activation command transfer area (100) or the response command transfer area (200) is provided while the processing device (11) is operating.
Is full, a flag is set in the flag register (25) to convert the gray zone (300) for transfer of a start command or transfer of a response command, and an unused area is generated in the converted area. When this is done, the converted area is restored and the flag register (25)
Bus interface internal buffer control method characterized by recovering the above flag. 3. A transmission buffer (17) for accumulating a start command and a response command transferred by a plurality of processing devices (11) to a common bus (12), and a start command transferred from the common bus (12). In a system in which the common bus (12) and a local bus (14) inside the common bus (12) are connected via a bus interface unit (13) including a reception buffer (18) for accumulating and a response command, In each transmission buffer (17) and / or reception buffer (18), an activation command transfer area (100),
A response command transfer area (200) and a gray zone (300) composed of a plurality of areas that can be switched between a start command transfer and a response command transfer are provided, and each area of the gray zone (300) is supported. Then, a plurality of flag registers (25 _1, 25 ₂ ) for indicating the use thereof are provided, and the activation command transfer area (100) or the response command transfer area (200) is provided while the processing device (11) is operating.
Is full, the flag register (25 _1, 25
₂ ) Sequentially flag a plurality of areas to convert the gray zone (300) into a corresponding area for activation command transfer or response command transfer, and an unused area is generated in the converted area. Also, the bus interface internal buffer control method is characterized in that the converted area is maintained. 4. A transmission buffer (17) for accumulating a start command and a response command transferred by a plurality of processing devices (11) to a common bus (12), and a start command transferred from the common bus (12). In a system in which the common bus (12) and a local bus (14) inside the common bus (12) are connected via a bus interface unit (13) including a reception buffer (18) for accumulating and a response command, In each transmission buffer (17) and / or reception buffer (18), an activation command transfer area (100),
A response command transfer area (200) and a gray zone (300) composed of a plurality of areas that can be switched between a start command transfer and a response command transfer are provided, and each area of the gray zone (300) is supported. Then, a plurality of flag registers (25 _1, 25 ₂ ) for indicating the use thereof are provided, and the activation command transfer area (100) or the response command transfer area (200) is provided while the processing device (11) is operating.
Is full, the flag register (25 _1, 25
₂ ) When a plurality of areas are sequentially flagged and the gray zone (300) is converted for each corresponding area for transfer of start command or transfer of response command, and an unused area is generated in the converted area. The flag register (25 _1, 25 ₂ ) while restoring the converted area
Bus interface internal buffer control method characterized by recovering the above flag.