JPS61151781A - Vector processor - Google Patents

Abstract

PURPOSE:To decrease the time of the vector processing by executing the second reading action in parallel to the first reading action by one vector register and sending the reading data to the resource to execute a separate vector instruction. CONSTITUTION:A vector instruction, which is decided not to be able to execute through a signal line 11, is successively given to a vector register control unit 1, a necessary decoding is executed by a vector register starting circuit 2 and a vector register control circuit 3 is started. Next, a vector register data unit 4 reads the contents of a vector register 6 by a signal 32 from the circuit 3 at the time of the first reading action, and reads them by a signal 33 at the time of the second reading action, and sends them as operand data 7. Thus, for one vector register, the second reading action is executed in parallel to the first reading action, respective reading data are sent to the resource to execute a separate instruction, thereby being able to decrease the time of the vector processing.

Description

[Detailed description of the invention] [Subject of invention] The present invention relates to a vector processing device.

[Background of the invention]

In order to process large matrix calculations that frequently appear in scientific and technical calculations at high speed, it has multiple vector registers and multiple arithmetic units, and the vector register that is being written with one vector instruction can be read with another vector instruction. Set it to 5,
A vector processing device having a function of chaining these two vector instructions has been proposed. See*fore
sample, a 1iteration of Re
chard, M, R+ussel@The Cray-
I Computer System=in”Comm
unicatinns of the ACM'197
8. JAN, Vol, 21. A1. PP63-72゜In such a vector processing device, one factor that determines the vector processing time is how many chains can be realized, and the number of chains is determined by the This is a contention situation between memory requesters. Below, one adder is used as an arithmetic unit,
The case where there is one multiplier and five memory requesters will be explained using an example. Below, vector register is V
R, E3i, and the memory requester are referred to as resources.

Example I Y(”)=A(”)10 B(”)+C(
”) (x=1.2.-・L) The time chart of this example is shown in Figure 1. Since there is only one adder for two vector addition instructions, there is a bottleneck in the adder, and one vector addition Since the instruction is forced to wait until the completion of other vector addition instructions, execution is divided into two chain groups.If the number of vector elements is L, the processing time is (2XL).
It becomes the cycle plus the overhead.

Example 2 Y(”)=A(”)+(B(”)XB(”))
(1=1.2...L) Set the time chart to the second
As shown in the figure. The execution is done in one chain group. The execution time is approximately L cycles.

Example s y(”)=(A(”)+B(1))xB(x
) (Engine = 1.2...L) The time chart is shown in Figure 3. The execution is about (zx
L)? It takes a cycle. Like Example 2, Example 5 requires about twice as much time as Example 2, even though it includes two vector load instructions, one vector addition instruction, one vector multiplication instruction, and one vector store instruction. The reason for this is that when reading VR1 loaded with vector B, a vector addition instruction and a vector multiplication instruction compete with each other, so that the multiplication is forced to wait until the end of the addition, and the multiplication is divided into two chain groups.

flJa Y(x)=(A(x)+B(x))XBO
)-4-B('') (z=q, 2, 10.L) The time chart is shown in Figure 4. Since the execution is in 3 chains, approximately (
3XL) cycles.

In the fourth example, vector B is further added to Example 3, but the readout of VRl conflicts with the vector multiplication instruction and the next vector addition instruction, so the adder is in a free state at the time of the second chain group. However, it cannot be started during this period.

As can be seen from the above description, conventional vector processing devices cannot read one VR in parallel and send it to multiple resources. Therefore, as shown in Example 3.4,
When executing a program that refers to the contents of a VR with many vector instructions, a conflict occurs when reading that VR.
Since the start of the vector instruction is waited for, the chainer is divided and the processing time is extended.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems of the conventional technology.

[Summary of the invention]

The present invention is capable of performing a second read operation in parallel with respect to a VR that is undergoing a read operation, and sending data resulting from the first read and the second read to resources that execute separate vector instructions. It is characterized by being made possible. In this case, the second read operation may be performed in a plurality of sequences, each of which may be sent to a resource that executes a separate vector instruction.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 5 is a diagram showing a schematic configuration of an instruction execution determination section of a vector processing device according to an embodiment of the present invention. Main memory (
Vector instructions read from the memory (not shown) are sequentially set in the instruction register 8. OP is the instruction code, Yu and part are 2
The number of the VR from which to read the operand, R1, is the number of the VR to which the data loaded by the memory requester from the main memory or the operation result from the arithmetic unit is to be written. 36 is a VR management circuit provided corresponding to each VR. This means that the corresponding VR is in the writing state, the first
It has a function of displaying whether it is in the read state or the second read state. Each of the VR official circuits 36 is
In order to display the five states, that is, the write state, the first read state, and the second start-up state, flip-flops (hereinafter abbreviated as FF) 1 and F corresponding to the respective states are used.
F2, FF5, and input terminals WS, R8, R
When a signal is given to FF1. FF2, F
When F'3 is set and signals are applied to input terminals WE, E, and E', FF1, FF2, . FF5
is reset. 9 is a resource management circuit provided corresponding to each resource. This has a function of displaying whether the corresponding resource is in use. Each of the resource management circuits 9 has one OFF to indicate that it is in use. 10 determines whether the VR and resources necessary for executing the vector instruction set in the instruction register 8 can be used, based on the signals of the VR management circuit 56 and the resource management circuit 9, and if it is executable, starts the operation. This is an instruction execution determination circuit that adds the number R8N of the executable resource (computer or memory requester) to the vector instruction from the instruction register 8 and outputs it to the signal line 11.

FIG. 46 is a diagram showing a schematic configuration of the VR section of a vector processing device that is an embodiment of the present invention. In the instruction execution determination section shown in FIG. 5, vector instructions determined to be executable are sequentially given to the VR control unit 1 via the signal line 11. The V start circuit 2 in the VR control unit 1 performs necessary decoding and outputs the V through signal lines 21 and 22.
Wake up R control circuit 5! help Therefore, during the write operation, the Th data unit 4 follows the write instruction signal 51 from the vR control circuit 3 and writes data sent from the signal #5 provided separately for each resource to the VR 6. During the first read operation, the contents of V& are read out and sent out as operand data 7 in accordance with the first read instruction signal 52 from the control circuit 3. Similarly, during the second read operation,
According to the second read instruction signal 33 from the VR%IJH circuit 3, the contents of V& are read out and sent out as operand data 7.

The details of the configurations of the VR starting circuit 2, the VR control circuit 5, and the data unit 4 will be described below with reference to FIGS. 7 to 9.

FIG. 7 is a configuration diagram of the VR startup circuit 2. 25 is the fifth
This is an instruction register that receives vector instructions via the signal line 11 from the instruction execution determination section shown in the figure.

54 indicates that each VB is in the first read state.
This is a signal line for receiving a read state signal from the VB control circuit 3, and is designed to detect via the selection circuit 240% 241 whether or not 2, from which a bipolar operand is to be read, is in the first read state.

For example, when ■ specified by R2 is not in the first read state, the decode circuit 250 is enabled through the NOT circuit 290, and the first read start signal line group 210 of VR is enabled.
Of these, '1°' is sent to the signal line corresponding to R2. The same applies to the old one, and 251 and 291 are the same decoding circuit and inverting circuit as above, respectively. Conversely, V of R2
When R is in the first read state, the decoding circuit 260
is enabled, and the second read activation signal line group 2 of VR is enabled.
Out of 11, 1 is sent to the signal line corresponding to the decoding result of y. The same applies to losses, and 261 is a decoding circuit.

The operand data synchronization signal sent to the VR data unit 4 via the signal 5I220 is used to synchronize data when one of the two operands is in the first read state and the other is in the second read state. This is a signal that indicates.

For example, the VR of R2 is in the first read state, and the VR of loss is in the first read state.
When not in the read state, the AND circuit 281 enables the decoding circuit 271 and sends 1° to the operand data synchronization signal line 220 corresponding to the VB of the data. Similarly, if the raccoon in R2 is not in the first read state and the output VR is in the first read state, the operand data synchronization signal corresponding to the VR in R5 is sent via the decoding circuit 270. 1” is sent to fM220.
The operand data synchronization signal is not sent unless both VRs of 5 are in the first read state or both are in the first read state.

265 starts the VB into which the data loaded from the main memory or the calculation result from the arithmetic unit is to be loaded.
This is a decoding circuit that decodes R1. The output of this decoder circuit 263 is sent as "1" to the signal line corresponding to R2 of the VR write activation signal line group 212. Also, 264 decodes R8N to activate the resource for executing the instruction. This is a decoding circuit.The output of this decoder circuit 264 is connected to the resource activation signal line group 213.
Among them, it is sent to the traffic signal corresponding to R3N with a value of 1".

@ In Figure 7, the vR write activation signal line group 212, the rinse activation signal line group 213, and the decoding circuits 265 and 264 connected to these are originally provided, and in order to realize the present invention, the R2° loss is Decoding circuits 250, 251, 260, 261° 270, 2 related to
71. It should be noted that the circuit consisting of the selection circuits 240, 241, etc. has been devised. FIG. 8 is a block diagram of the VR and control circuit 5. First read start signal line group 21
When 1' is sent to a certain signal line among 0, the corresponding VR
is input to the management circuit 660 input terminal R8, and the first
Read status display FF2 is set. Further, when 1° is sent to a certain signal line in the second read start signal line group 211, it is input to the input terminal section' of the corresponding VR-i7 embedded circuit 36, and the second read state display FF5 therein is inputted to the input terminal section' of the corresponding VR-i7 embedded circuit 36 but '
Set. Further, when 1" is sent to a certain signal line in the write activation signal line group 212, the corresponding VR management circuit 3
60 input terminal WS, and the write status display FFI therein is set. The output of each VB and the second read status display FF5 of the management circuit 56 is sent to the VR activation circuit 2 from the output terminal via the signal line 54.

350 converts the set of the write instruction signal applied to the input terminal VR and the priority end signal applied to the input terminal E to the VR corresponding to VB, which is the data supply destination of each resource.
, the input terminal V of the management circuit.

North register (hereinafter referred to as S-) for inputting WBK
(abbreviated as G) conversion circuit. This SG conversion circuit 3
50 controls the operation based on command information received via a signal from the command register 25 and the urine 21.

The write instruction signal is output from the resource in synchronization with the output of data (vector elements) one by one from the resource, and the vR management circuit 66 updates the pointer therein every time it receives the write instruction signal. . The write end signal is issued when the resource processes all the elements (vector elements) to be processed by one vector instruction, and when the vn4 logic circuit 56 receives the write end signal,
Reset the write status FFI therein. The VR management circuit 36 outputs the read permission signal from the output terminal VO as many times as indicated by the pointer, and returns the pointer by the number of read permission signals output.

Each operand control circuit 38 is provided corresponding to each resource, and when the corresponding resource receives data, the operand control circuit 38 corresponds to the VR that is the data supply source.
A read permission signal is received from the 1 processing path 56. Therefore,
The operand control circuits 38 corresponding to the operands have separate V
The read permission signal from the B management circuit 56 is received at the input terminals V12 and Vl5, respectively, but the operand control circuit corresponding to the memory requester for storing VR data in the main memory is received from one management circuit 36. Only the read permission signal of is received at the input terminal v12.

371 receives the read permission signal from the VR management circuit 36, and the VR corresponding to the management circuit 36 receives the command R, 2.
This is a register resource (hereinafter abbreviated as 3-8) conversion circuit for inputting data to the input terminal V12 of the operand control circuit 38 corresponding to the destination resource when data is sent as a flower specified by. Also, 372
is the operand control circuit corresponding to the resource that is the destination when the VR corresponding to the VR management circuit 56f sends data as the VR specified in the instruction part. 38 input terminals v
This is a G-8 conversion circuit for inputting to 13. G-8
The conversion circuits 371 and 572 both control the operations based on command information received from the command register 23 via the signal line 21.

The operand control circuit 58 compares the read permission signals inputted to the input terminal V12 and the cutting edge terminal V13, and outputs a read instruction signal from the output terminal v2 for each cycle an equal number of times. The operand control circuit 38 corresponding to the requester has an input terminal V12.
Based on the read permission signal inputted to , a read instruction signal is outputted to the output terminal v2 every cycle by the number of times.

555 is an S for sending a read instruction signal from the operand control circuit 58 to the VR when the resource corresponding to the operand control circuit 58 receives data in the first read state from the VR specified by R2 of the instruction. -G conversion circuit. 356 is the above smell
-G conversion circuit. 557 is operand control circuit 3
8, the read instruction signal from the operand control circuit 3
This is an SG conversion circuit for sending Vl: when the resource corresponding to No. 8 receives data in the second read state from the VB specified by the command frame.

Reference numeral 558 is an S-G conversion circuit in which Yu is replaced by Gen in the above.

The signal lines to which the read instruction signals from the SG conversion circuits 555 and 356 are output are those whose destination is the same VR,
each connected to an OR gate 594, and this output is connected to the first
This becomes a read instruction signal 52.

Also, the SG conversion circuit 35? The signal lines to which the read instruction signals from 592 and 558 are output are connected to each other that has the same destination as the VR. This output is delayed by one cycle in the FF 395 for time adjustment, and becomes the second read instruction signal 33.

The read instruction signal from each operand control circuit 38 is sent to its corresponding resource via signal M 560. Based on this read instruction signal, each resource detects that data will be read from the VR after a predetermined time and waits for data from the VR.

Each operand control circuit 38 holds the number of elements (vector elements) to be processed by one vector instruction, and outputs a read end signal from the output terminal U after outputting a read permission signal corresponding to the number of elements (vector elements).

Reference numeral 551 indicates the V storage management corresponding to the VR when the resource corresponding to the operand control circuit 58 receives the read end signal from the operand control circuit 38 in the first read state from "B" specified by R2 of the instruction. 552 is an 8-G conversion circuit for sending to the circuit 36. 552 is an 8-G conversion circuit in which R2 replaces loss in the above.
is the read end signal from the operand control circuit 38,
5-(3 conversion circuit) for sending to the V management circuit 56 corresponding to the VB when the resource corresponding to the operation 2) code control circuit 58 is received in the second read state from the VR specified by R2 of the instruction. 554 in the above,
R2 is an SG conversion circuit replacing R5K.

The read end signals from the 8-G conversion circuits 551 and 352 are output to OR gates 561 and 561, respectively, to which VB corresponds.
The input terminal ratio g of the corresponding VR management circuit 56 is ORed with
<Input. Further, the read end signals from the SG conversion circuits 353 and 554 are ORed by the OR gate 362, respectively, to the corresponding VR, and the corresponding VB is input to the management circuit 560! lli'. When each of the VR management circuits 36 receives the input Mizuko R1: read end signal, it resets the first read state FF2 therein, and also receives the read end signal at the input terminal section' and outputs the read end signal therein. The second read state FF5 is reset.

In addition, in the V-box control circuit 3, in order to realize the present invention,
In particular, it should be noted that the second read state FF5 is provided in the vR management circuit 56, and that the 8-G conversion circuits 553, 554, 557, and 558 are provided.

FIG. 9 is a configuration diagram of a VB data unit. In one case, the starting address register (kllt
c) 41G holds the read address in the first read state and is updated by the first read instruction signal S2 from the vR control circuit 3.

412 is a +1 circuit for this update. On the other hand, the write address register (WAC) 411 holds the rewrite address during writing, is updated by the write instruction signal 51 from the VB and control circuit 6, or holds the read address in the second read state, and controls the vR. circuit 5
It is updated by the second read instruction signal 55 from . 41
3 is a +1 circuit for these updates. 414 is VR
This is an OR circuit that ORs the subtraction instruction signal 51 from the control circuit 3 and the second read instruction signal 33. The 1st shift of BAC410 and the value of WAC411 are alternately switched by address selectors 420 and 421 every cycle, and the values of
Two memory panchromatic 0.61 R4 consisting of m are seen. These memory panchromatic 0.61 read data are alternately switched by data selectors 450 and 451,
It is input to read data registers 460 and 461. Data from the first read is set in the read data register 460, and data from the second read K is set in the read data register 461, respectively. However, during the Sogomo operation,
The data input to read data register 461 is meaningless.

441 directly outputs the data from the first read K set in the read data register 460, or
This is a data selector for switching whether to output via 62. Register 462 is for delaying the data from the first read by one cycle. The data selector 441 is controlled by the output of the FF 44 to select which input. FF 44 is set by an operand data synchronization signal from VR activation circuit 2 applied via signal line 220.

45 is a double clock circuit that generates a clock twice as fast as one cycle. Address selector 420.
421 is controlled by the direct output of the double clock circuit 43. Further, the data selectors 450 and 451 are controlled by the output of the double clock circuit 45 via the inverter 415. 416 and 417 are AND gates which respectively apply the write instruction signal 31 from the VR control circuit 3 to the memory panchromatic 0.61 in synchronization with the output of the double clock circuit 43. 70 and 71 are write data registers into which write data cassettes are respectively stored for memory panchromatic 0.61. When a write instruction signal is given from the memory panchromatic registers 70.61 and 416 and 417, the write data registers 70.7
Write the data set to 1.

With the above configuration, in vRA, when the output of the double clock circuit 43 is 0, the memory panchro 0 is in the first read state.
Memory panchromatic 1 enters the write state or the second read state. When the angle is 1°, the above is reversed.

8-80 is for inputting the data given from each resource through separate signal lines 5 to the ball that is the supply destination.
(This 8-G conversion circuit 80 controls the operation based on the instruction information received from the instruction register 23 via the signal IM21.
is a G-8f conversion circuit for inputting the data from the data selector 441, that is, the data by the first read, to the resource that is the destination when sending the data from the data selector 441 as the VR specified by R2 of the instruction. 471 is R2 with command on the V side
When sending data from the read data register 461, that is, data by second read, as a raccoon designated by
-8 conversion circuit. 472 is G-8 for inputting data to the destination resource when data from the read data register 460, that is, data by first read, is sent as the VR whose v decoration is specified by R3 of the instruction.
It is a conversion circuit. 473 is a (3
-8 conversion circuit. The q-8 conversion circuits 470 to 473 receive the signal #! from the instruction register 25. The operation is controlled based on command information received via 21.

The signal lines to which the data from the G-13 conversion circuits 470 and 472 are output are connected to OR gates 48, respectively, if the destination is the same resource.

Also, the signal lines to which the data from the j-8 conversion circuits 471 and 473 are output are connected to the OR gates 49 that have the same destination.
connected to.

Next, the overall operation of the embodiment will be explained.

, :, :Teha, 几1 is VB, 4 is R2, VB5 is R3, VR1 is R3, and vector addition instructions specifying a certain adder among several arithmetic units F18N are activated. Furthermore, it is assumed that VB, 5 is in the process of writing the multiplication result, and vRl is in the process of first reading to the multiplier. That is, in FIG. 4, it is assumed that the situation is immediately after the multiplication instruction of the second chain group is activated.

From the above situation, ■ In the starting circuit 2, VB5°V
The first read state signals sent from the VR management circuits 56 of B and 1 to the signal line 54 are o' and 'i', respectively.

Therefore, the output of the selection circuit 240 is 0', and the output of the selection circuit 241 is 1', so the decoding circuit 250 is enabled and the VR
The signal line corresponding to 3 becomes "1". Also, the decoding circuit 261 is enabled, and the second read activation signal line group 2
Among the 11, the signal line corresponding to the VRI is 1. As a result, the state of the VR management circuit 36 of VB3 becomes the first read state (chain) in the write state, and the VR1
The state of the VR and management circuit 56 becomes the second read state in the first read state.

On the other hand, in the v start circuit 2, the decode circuit 270 is enabled, the operand data synchronization signal is sent to the signal line 220 corresponding to VR, 5K, and F'F44 in be done.

Therefore, the data selection circuit 441 in VB3 selects the output of the data register 462.

Furthermore, in the vR+ control unit 3, G-8 is
The conversion circuit 571 connects the path for inputting the read permission signal from the RW logic circuit 36 corresponding to VB5 to the input terminal V12 of the operand control circuit 38 corresponding to the adder.
8 conversion circuit 372 is a vFLw logic circuit 3 corresponding to VRI.
6 to the operand control circuit 38.
A new path for input to the input terminal vi3 is established respectively. Further, the SG conversion circuit 355 provides a path for inputting the read instruction signal from the operand control circuit 58 to VB5, and the SG conversion circuit 358 provides a path for inputting the read instruction signal from the operand control circuit 58 to the operand control circuit 3
Establish a new path for inputting the read instruction signal from 8 to VRl! do. Further, the 8-G conversion circuit 351 converts the read end signal from the operand control circuit 58 to VB.
■The path to be input to the management circuit 56 corresponding to 3 is set to S-G.
The conversion circuit 354 is a VB corresponding to VRI, and the management circuit 56
Establish a new path for each input.

In addition, in the vR data unit 4, command information sent from the VR start circuit 2 via the signal line 21 causes
The q-8 conversion circuit 470 converts the path for manually inputting data from VB5 (data from the first read) to the adder into the G-8 conversion circuit 470.
The 8-conversion circuit 475 connects a path for manually inputting data (W, 2 read data) from VRl to the adder by 5-t.
3 conversion circuit 80 receives data (operation result) from the adder.
Establish a new path for inputting the information into VB4.

FIG. 10 shows a time chart illustrating the operation of the VR data unit 4 when executing the addition instruction. In FIG. 10, 460, 461, and 462 are shown with 1 E and 0 added thereto to indicate that read data from memory panchromatic 0 or 61 is set.

Also, the numbers inside 00 are RAClo.

This shows the value of WAC411.

By performing the above operations, the VRI can perform two systems of read operations in parallel, and as shown in FIG. Can be shortened to group.

〔Effect of the invention〕

The embodiment in which the second read operation for vR is one series has been described above, but according to the present invention, the second read operation is performed for one VR in parallel with the first read operation, Since each read data can be sent to each resource executing a separate vector instruction, the number of chain groups can be reduced, resources can be operated efficiently, and vector processing time can be reduced.

[Brief explanation of the drawing]

1 to 4 are diagrams for illustrating the operation of the prior art, FIG. 5 is a diagram showing a schematic configuration of an instruction execution determination section of a vector processing device according to an embodiment of the present invention, and FIG. 7 is a detailed configuration diagram of the VB startup circuit in FIG. 6, and FIG. 8 is the same (VR Figure 9 is a detailed configuration diagram of the control circuit, Figure 9 is a detailed configuration diagram of the VR data unit, Figure 10 is a time chart explaining its operation, and Figure 11 is an example of Figure 4 improved by the present invention. In the figure, 1...VR control unit 2...■ Starting circuit 5...
・■Control circuit 4...VR data unit 6...
・Vf'L 8, 23...Instruction register 9...Rinse management circuit 10...Instruction execution determination circuit 56...VB, management circuit 58...Operand control circuit 60.61...Memory bank 70.71...Write data register 80, 550
58...5-(j conversion circuit 571.572,470
~473...(J-8 conversion circuit 410...Read address register (RIAc) 411...Write address register (WAC) 420, 421...Address selector 441.450.451...Data selector 4
60, 461...Read data register procedure correction sound (
猷)

Claims (3)

[Claims] (1) In a vector processing device including a plurality of vector registers, means for detecting that each vector register is in the first read state, and a vector detected by the detecting means when the vector register is in the first read state.・Vector register reading means for performing at least one series of second reading from the register in parallel with the first reading, and separating data from the first reading and data from the second reading read by the means. 1. A vector processing device comprising: data sending means for sending a vector instruction to each resource that executes the vector instruction. (2) In paragraph 1, each of the vector registers has a plurality of memory banks, and the vector register reading means includes means for alternately retrieving data by first reading and second reading from each of the memory banks. have (3) In item 2, the retrieval means has means for delaying data by the first read.