JP2684752B2 - Extended storage control method - Google Patents

Description

The present invention relates to an extended storage control system of a memory access control device connected to an extended storage device.

[Prior Art] Conventionally, in a memory access control device connected to a main storage device and an extension storage device, a request from a request source is transferred (for example, in page units) between the extension storage device and the main storage device. At that time, it was general to perform the following two processes separately.

In the case of a transfer request from the expanded storage device to the main storage device, (1-a) read processing from the expanded storage device (1-b) write processing to the main storage device A transfer request from the main storage device to the expanded storage device In the above case, (2-a) read processing from the main storage device (2-b) write processing to the extended storage device In the above case, the read / write processing to the extended storage device is connected only to the main storage device. As compared with a memory access control device that does not have a memory access control device, it is naturally performed using an interface with an extended storage device and a dedicated control circuit. Also,
In the above processes (1-b) and (2-a), the transfer unit is generally larger than the access unit of the main storage device. For this reason, it is necessary to have a dedicated port for performing the processing by decomposing into read requests and write requests for a plurality of main storage devices. Therefore, the number of request receiving ports has increased, that is, the amount of HW (hardware) has increased, and since the number of ports has increased, the control becomes complicated and the delay time of the busy check of the main storage device becomes severe.

[Problems to be Solved by the Invention] In the above-described conventional extended storage control method, by having a dedicated port for extended storage processing, the amount of HW increases, control becomes complicated, and a busy check of the main storage is performed. There is a drawback that the delay time becomes severe.

[Means for Solving the Problems] The extended storage control method according to the present invention includes a plurality of request sources,
An access request to the main storage device from the request source, a first data transfer request from the main storage device to the extension storage device, and an extension storage device connected to a main storage device and a diffusion storage device. In a memory access control device for performing a process for a request including a second data transfer request from the request source to the main memory device, and diagnosing the main memory device in response to a diagnosis request. Selecting means for receiving a request, selecting one request, and outputting the selected request; and whether the selected request is the access request,
A determination circuit that determines whether the request is the diagnosis request, the first data transfer request, or the second data transfer request; and the access request and the diagnostic request, A main memory that generates a first read request and a first write request to the main memory device, and outputs the generated first read request and first write request together with a first request address to the main memory device. An access control unit, a main memory access control unit, a memory scan circuit connected to the selection unit and the determination circuit, and an extended storage access unit connected to the extended storage device, the selection unit and the determination circuit. An address generator, a first storage buffer connected to the memory scan circuit, and the extended storage access / address generator; A second storage buffer connected to the memory scan circuit, wherein the memory scan circuit receives the diagnosis request, the second request address, and the store data, and receives the diagnosis data from the main memory access control unit. The request address of No. 2 is updated multiple times, and the second address of the store data is updated together with the updated address.
Write request is output to the main memory access control unit, and then a second read request is output to the main memory access control unit at the same address as when the second write request is output. Memory scan function for comparing the first reply data with the above-mentioned store data and diagnosing the main memory device based on the match or non-match, and the request selected by the determination circuit is the first data transfer request. If determined, generate a third read request and address to the main storage device from the selected request, and output the generated third read request and address to the main storage access control unit. And a function of storing the second read data from the main storage device for the third read request and the address in the first storage buffer. -The address generator is the first
And a function of outputting a third write request and a third request address to the extended storage device together with the second reply data stored in the storage buffer, and the request selected by the determination circuit is the second request. If it is determined that the request is for data transfer, the fourth read request and address to the extension storage device are generated from the selected request, and the generated fourth read request and address are generated to the extension storage device. To the second read request and the third reply data from the extended storage device for the address.
And a fourth write request to the main memory access control unit together with the third reply data stored in the second storage buffer. Fourth
And a read / write process to the main memory device in the data transfer between the extended memory device and the main memory device is performed in common with the memory scan circuit. .

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a memory access control device to which an extended storage control system according to an embodiment of the present invention is applied is a request source such as an arithmetic processing unit or an input / output processing unit, a main storage unit, and an extended storage unit. It is connected. In this embodiment, there are three devices, device A, device B, and device C, as request sources. The memory access control device includes a request reception port unit 10, a request processing unit 75, and other HWs related to extended storage control.

The request reception port unit 10 includes a device A request reception buffer 20 that receives a request from the device A, a device B request reception buffer 30 that receives a request from the device B, and a device C request reception buffer 40 that receives a request from the device C. Have. Here, the request from the request source is a request address, a request code indicating operation instructions such as writing and reading,
Store data etc.

50, 60, 70 are device A, B, C buffer read registers which receive the buffer output. 80 is a selection circuit, device
Perform a busy check on the main memory of A, B, and C requests, and select only those that pass the busy check.
If there are multiple requests that pass the busy check,
Each priority is taken, and only one request is selected, and the selected request is output to the main memory access control unit 90 and the extended memory access determination circuit 140.

Generally, the main memory has an XN interleaved structure. Also in this embodiment, the XN interleaved configuration is also adopted. That is, the main memory 100 is composed of N banks, and busy F / F exists for each bank.
The access bank from the request source and the busy F / F are checked.

The main memory access control unit 90 receives the output of the selection circuit 80,
Only when there is no output, the memory scan circuit 150 receives the output. Selection circuit 80 and memory scan circuit 150
The output of is a request address from a request source, a request code (operation designation such as read / write), and store data. Based on these pieces of information, the main memory access control unit 90 creates and outputs an access request to the main memory device 100. Then, the main memory access control unit 90 receives the relieve data from the main memory device 100 for it, and when receiving the output of the selection circuit 80, the main memory access control unit 90 causes the reply register 110, 120, 130 of the request source to send the memory scan circuit 150. When the output of is received, it is output to the memory scan circuit 150.

The main memory device 100 returns a reply to the access request from the main memory access control unit 90. The device A reply register 110 is a register for storing reply data from the main storage device 100 to the device A, and outputs reply data to the device A. The device B reply register 120 is the device B
The reply data is output to the device B by a register for storing reply data to the device B. The device C reply register 130 is a register for storing reply data to the device C, and outputs reply data to the device C.

The unit of access in this embodiment is 8B (bytes) for both the main storage device 100 and the extended storage device 190. When accessing the main storage device 100, only the above HW operates.

The extended storage access determination circuit 140 detects that the output of the selection circuit 80 is a transfer access from the main storage 100 to the extended storage 190 or a transfer access from the extended storage 190 to the main storage 100. Then, the extended memory access determination circuit 140 outputs the signal to the memory scan circuit 150 and the extended memory access / address generation unit 160. Naturally, at the time of extended memory access, the main memory access control unit 90
Does not access the main storage device 100 at all.

A transfer unit between the extended storage device 190 and the main storage device 100 is generally a page unit (as is the case with IBM Corporation), and is 4 kB (one page unit) in this embodiment as well.
Further, the request address includes the extended storage address and the main storage address.

In order to reduce the number of interfaces, it is conceivable to set either address in the memory access control device in advance and then issue an access request together with the other address.

The memory scan circuit 150 inputs the output of the selection circuit 80, the output of the extended memory access determination circuit 140, the output of the extended memory reply data storage buffer 180, and the reply data of the main memory access control unit 90. The operation of this part includes the memory scan and the transfer between the main memory device and the extended memory device described below.

(1) During memory scan operation The write address and store data are input from the output of the selection circuit 80, and a write request to the main storage device 100 is generated. Update the write address multiple times,
By outputting the store data and the write request together with the updated address to the main memory access control unit 90, the store data is written to consecutive addresses of the main memory device 100. After that, a read request for the same address as the address specified in the write request output is output to the main memory access control unit 90, reply data from the main memory device 100 for the read request is received from the main memory access control unit 90, and it is received. Compare with the above store data. When the reply data from the main storage device 100 and the above-mentioned store data do not match, it is detected that the main storage device 100 has a failure.

(2) During transfer between main memory and extended memory (a) During transfer between main memory and extended memory The request address of the main memory 100 is input from the output of the selection circuit 80, and at the same time read to the main memory 100 Generate a request. A read request is output to the main memory access control unit 90 4 kB / 8B = 512 times while updating the address by 8B each. Then, the reply data from the main memory access control unit 90 is received, and the received reply data is output to the main memory reply data storage buffer 170.

(B) Transfer from extended storage device to main storage device The output of the extended storage reply data storage buffer 180 having reply data from the extended storage device 190 is received, and at the same time, a write request to the main storage device 100 is generated. 4 kB / 8B = 5 while updating the main memory address by 8B each
The write request is output to the main memory access control unit 90 12 times together with the reply data.

The extended memory access / address generator 160 includes a selection circuit 8
The output of 0, the output of the extended memory access determination circuit 140, and the output of the main memory reply data storage buffer 170 are input. The operation of this part is as follows:
There are extended storage transfer and extended storage → main storage transfer.

(A) Main memory-> extended storage device transfer Main memory reply data that stores reply data from the main storage device 100 for receiving the extended storage address from the output of the selection circuit 80 and transferring it to the expansion storage device 190 Received from the storage buffer 170. At the same time, a write request to the extended storage device 190 is generated. While updating the extended storage address by 8B, the read request is output to the extended storage device 190 together with the output of the main storage reply data storage buffer 170 4kB / 8B = 512 times.

(B) Transfer from extended storage device to main storage device The request address of the extended storage device 190 is received from the output of the selection circuit 80, and at the same time, a read request to the extended storage device 190 is generated. While updating the address by 8B, the read request is output to the extended storage device 190 4 kB / 8B = 512 times.

As described above, in the present embodiment, data transfer with the extended storage device 190 is performed in 8B units, but it may be performed in 128B units, for example. In the case of the 128B unit, the access to the extended storage device 190 is 4 kB / 128B = 32 times.

Further, the capacities of the main memory reply data storage buffer 170 and the extended memory reply data storage buffer 180 are
It is determined to be easy to control by the transfer amount for one access with the extended storage device 190.

The main memory reply data storage buffer 170 stores reply data from the main memory device 100. This buffer 1
The memory scan circuit 150 stores the data in the main memory access control unit 9 because the main memory is transferred to the extended memory.
This is when the main memory read request is output to 0 and the reply from the main memory device 100 for the request is returned. The output of the main memory reply data storage buffer 170 is input to the extended storage access / address generation unit 160, and this data becomes write data for the extended storage device 190.

The extended storage reply data storage buffer 180 stores reply data from the extended storage device 190 in response to a read request to the extended storage device 190. The output of the extended storage reply data storage buffer 180 is input to the memory scan circuit 150, and this data becomes write data to the main storage device 100.

The expanded storage device 190 generally has a capacity that is several times or more the storage capacity of the main storage device 100. In this embodiment, access is made in 8B units,
It is also possible to carry out in block units (for example, 128B).
The operation of the expanded storage device 190 is as follows.
In response to the read request and the write request from the address generation unit 160, the reply data is returned to the extended storage reply data storage buffer 180 (naturally, when the write request is made, there is no reply data).

The operation of transfer between the main storage device 100 and the extended storage device 150 is summarized as follows.

(1) When transferring from the main memory device to the expanded memory device When the expanded memory access from the request source is judged by the expanded memory access judgment circuit 140, the request code and address of the request are inputted from the selection circuit 80 to the memory scan circuit 150. To be done. Next, the memory scan circuit 150
While updating the request address, it outputs to the main memory access control unit 90 together with the read request 4 kB / 8B = 512 times. The main memory access control unit 90 accepts the request from the memory scan circuit 150 and executes the reading from the main memory device 100 only when there is no output from the selection circuit 80. When the reply data from the main memory access control unit 90 is returned, the memory scan circuit 150 stores the reply data in the main memory reply data storage buffer 170. Next, the output of the main memory reply data storage buffer 170 is input to the extended memory access / address generation unit 160. The extended storage access / address generation unit 160 generates a write request to the extended storage device 190, updates the write address to the extended storage device 190 4 kB / 8B = 512 times, and outputs the output of the main storage reply data storage buffer 170. The reply data is output to the extended storage device 190. As a result, the data in the main storage device 100 is transferred to the expansion storage device 190.

(2) At the time of transfer from the expanded memory device to the main memory device When the expanded memory access from the request source is judged by the expanded memory access judgment circuit 140, the request code and address of the request are generated from the selected circuit 80 by the expanded memory access address. It is input to the section 160. Next, the extended storage access / address generating unit 160 outputs the request address to the extended storage device 190 together with the read request while updating the request address 4 kB / 8B = 512 times. The reply data from the diffusion storage device 190 is stored in the diffusion storage reply data storage buffer 180.
Is output to Next, the output of the diffusion storage reply data storage buffer 180 is input to the memory scan circuit 150. The memory scan circuit 150 generates a write request to the main memory 100, updates the write address 4 kB / 8B = 512 times, and diffuses the memory reply data storage buffer 180.
Main memory access control unit 90 together with output reply data
Output to The main memory access control unit 90 accepts the output of the memory scan circuit 150, issues a write request to the main memory 100, and stores the data of the extended memory 190 in the main memory only when the selection circuit 80 does not output. Transfer to device 100.

As described above, according to the present invention, in the transfer process between the main memory device and the extended memory device, the processing part for the main memory device is shared with the existing memory scan circuit, so that the control is simplified. This has the effect of further reducing the amount of HW.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a memory access control device to which an extended storage control system according to an embodiment of the present invention is applied. 10: Request reception port section, 20: Device A request reception buffer, 30: Device B request reception buffer, 40: Device C request reception buffer, 50: Device A buffer read register, 60: Device B buffer Read register, 70 ... Device C buffer read register, 75
...... Request processing unit, 80 …… Selection circuit, 90 …… Main memory access control unit, 100 …… Main memory device, 110 …… Device A reply register, 120 …… Device B reply register, 130
...... Device C reply register, 140 ...... extended memory access determination circuit, 150 ...... memory scan circuit, 160 ・ ・ ・ diffused memory access / address generator, 170 …… main memory reply data storage buffer, 180 …… extended memory reply Data storage buffer, 190 ... Extended storage device.

Claims (1)

(57) [Claims] 1. A plurality of request sources, a main storage device, and an extended storage device, which are connected to an access request to the main storage device from the request source, and a first access from the main storage device to the extended storage device. A memory access control device that performs processing for a data transfer request of No. 1 and a request including a second data transfer request from the extended storage device to the main storage device, and diagnoses the main storage device in response to the diagnosis request. In the above, a selection unit that receives a plurality of requests from the request source, selects one request, and outputs the selected request; and whether the selected request is the access request or the diagnostic request And the first data transfer request or the second data transfer request, and a determination circuit that receives the access request and the diagnostic request, A main memory that generates a first read request and a first write request to the main memory device, and outputs the generated first read request and first write request together with a first request address to the main memory device. An access control unit, a main memory access control unit, a memory scan circuit connected to the selection unit and the determination circuit, and an extended storage access unit connected to the extended storage device, the selection unit and the determination circuit. An address generator, a first storage buffer connected to the memory scan circuit and the extended memory access / address generator, and a second storage buffer connected to the extended memory device and the memory scan circuit. The memory scan circuit receives the diagnosis request, the second request address, and store data, and sends the diagnosis data to the main memory access control unit. The second request address is updated a plurality of times and the second address of the store data is updated together with the updated address.
Write request is output to the main memory access control unit, and then a second read request is output to the main memory access control unit at the same address as when the second write request is output. Memory scan function for comparing the first reply data with the above-mentioned store data and diagnosing the main memory device based on the match or non-match, and the request selected by the determination circuit is the first data transfer request. If determined, generate a third read request and address to the main storage device from the selected request, and output the generated third read request and address to the main storage access control unit. And a function of storing the second read data from the main storage device for the third read request and the address in the first storage buffer. The address generator, together with the second reply data stored in the first storage buffer, makes a third write request and a third write request to the extended storage device.
And a fourth read request from the selected request to the expansion storage device when the selected request is determined to be the second data transfer request by the determination circuit. , An address is generated, the generated fourth read request and address are output to the extended storage device, and the third read data from the extended storage device for the fourth read request and address is output as the third reply data. And a second write request to the main memory access control unit together with the third reply data stored in the second storage buffer. And a function of outputting a fourth request address, and before read / write processing to / from the main storage device in data transfer between the extension storage device and the main storage device. Extended storage control method which is characterized in that by sharing the memory scan circuit.