JPH0236443A - System for controlling expansion storage - Google Patents

Abstract

PURPOSE:To simplify control and to reduce an HW quantity by sharing a processing part with respect to a main storage with an existing port in a transfer processing between the main storage and an expansion storage. CONSTITUTION:A main storage access/address generation part 150 inputs the request address of the main storage 100 from the output of a selection circuit 80 at the time of transfer from the main storage to the expansion storage, and outputs the request address to a device C buffer read register 70. At the time of transfer from the expansion storage to the main storage, the output of a expansion storage reply data storing buffer 180 having reply data from the expansion storage 190 is received, and a write request for the main storage 100 is simultaneously generated, whereby the main storage address is outputted with reply data to the register 70. Thus, the processing of access with respect to the main storage 100 is shared with the existed request acceptance port 10 in the transfer processing. Thus, control is simplified an the HW quantity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an extended memory control method for a memory access control device connected to an extended storage device.

[Prior Art] Conventionally, in a memory access control device connected to a main storage device and an expanded storage device, when a request from a request source is for transfer between expanded storage and main memory (for example, in page units), Generally, each process was divided into the following two processes.

■ In the case of a transfer request from extended memory to main memory - (1-a) Processing to read from extended memory (1-b) Processing to write to main memory ■ In the case of a request to transfer from main memory to extended memory - (2-a) Read processing from main memory (2-b) Write processing to extended memory In the above case, read and write processing to extended memory is performed by a memory access control device that is only connected to main memory. Naturally, this requires an interface with extended storage and a dedicated control circuit.

In addition, in the processing of (1-b) and (2-a) above, - Since the transfer unit is numerically larger than the main memory access unit, read requests to multiple main memories, write requests, etc. It became necessary to have a dedicated port to break down requests and process them.

As a result, the number of request receiving ports has increased, that is, the amount of HW has increased, and as the number of ports has increased, control has become complicated and the delay time for busy checking of the main memory has become severe.

[Problems to be solved by the invention] The above-mentioned conventional technology has a dedicated port for extended storage processing, which increases the amount of hardware, complicates control, and imposes severe delay times on pinot checks of the main memory. There is a problem with that.

In view of the above drawbacks, the second technical object of the present invention is to provide an extended storage control system that simplifies control and eliminates the amount of HW.

[Means for Solving the Problems] According to the present invention, access to a main storage device from a plurality of arithmetic processing units and input/output processing units.

In a memory access control device that transfers data between an expanded storage device and a main storage device.

a request receiving/holding means for inputting requests from the arithmetic processing unit and the input/output processing unit;

Selection means for performing a busy check on the requests output from the request reception/holding means, further determining the priority, and selecting one request.

Main memory access means receives the request from the selection means, generates read and write requests to the main memory, and outputs them to the main memory together with the requested address and data.

a reply means for receiving reply data from the main storage device for the main storage access means and returning it to the request source;

Is the main storage device accessed from the selection means output?

a determining means for determining whether data is being transferred between the extended storage device and the main storage device;

When it is determined by the output of the determination means that the request from i Mizumoto is for data transfer between the extended storage device and the main storage device, if the request is for data transfer from the main storage device to the expanded storage device, the selection means a first generation means for generating a request address and a read request to the main storage device from the output of the first generation means;

first request reception port access means for outputting the request address and read request to the main storage device generated by the first generation means to the request reception port means;

first reply data storage means for storing reply data from the main storage device in response to request processing from the first request reception port access means;

Sending means for sending the write address and write request to the extended storage device, when stored in the first reply data storage means, to the extended storage device together with the stored data that is the reply data from the main memory.

and second generating means for generating a request address and a read request to the expanded storage device from the output of the selection device if the transfer is from the expanded storage device to the main storage device.

extended storage device access means for outputting the request address and read request generated by the second generation means to the expanded storage device;

4) Second reply data storage means for storing reply data from the expanded storage device in response to a read request to the expanded storage device.

When stored in the second reply data storage means, a second reply data storage unit generates an address and a write request to the main storage device, and outputs the reply data to the request reception port means together with the reply data in the second reply data storage means. It has a request reception port access means.

During the transfer process between expanded storage and main storage.

An extended storage control method is obtained, which is characterized in that processing for accessing the main storage is performed in common with an existing request reception port.

[Example] An example of the present invention will be described below with reference to the drawings.

A memory access control device according to an embodiment of the present invention is connected to a request source such as an arithmetic processing device or an input/output processing device, a main memory, and an extended memory.

In this embodiment, the request sources are device A and device B.

and device C.

The memory access control device is the request reception port unit 10
and the request processing unit 75 and other extended memory control-related hardware.

The request reception port section IO receives and receives requests from the device A request reception buffer 20. Device B request reception buffer 30 that accepts requests from device B. It has a device C request reception buffer 40 that accepts requests from device C.

A request from a request source includes a request address, a request code indicating operation instructions such as writing and reading, and store data.

50.60.70 is device A that receives the above buffer output
, B, and C buffer read registers.

Reference numeral 80 denotes a selection circuit which performs a busy check on the main memory of requests from devices A, B, and C, and selects only those that pass the busy check. If a plurality of requests pass the pitch check, the priority of each request is determined, and only one request is selected and output to the main memory access control section 90 and the extended memory access determination circuit 140.

- Numerically, the main memory has an XN interleaved configuration. The present embodiment also has the same (XN interleaved configuration. That is, the main memory is composed of N punctures, and there is a busy f for each puncture, and an access bank from the request source and the busy F/F' are being checked.

90 is a main memory access control unit which receives the output of the selection circuit 80. The output of the selection circuit 80 is a request address from a request source, a request code (operation instruction such as read/write), and store data.

Based on this information, an access request is created and output to the main memory.

Then, it receives the reply data from the main memory and outputs it to the request source's reply data 1) 0°120.130.

100 is a main memory and returns reply data in response to an access request from the main memory access control section 90.

1) 0 is output to device A in a renostar that stores reply data from the main memory to device A.

1.20 is a renostar that stores reply data to device B and is output to device B.

Reference numeral 130 is a renostar that stores reply data to device C and outputs it to device C.

In this embodiment, the unit of access is 8B for both main memory and extended memory.
(byte). Access to main memory only works with the above hardware.

In this embodiment, the transfer commands from the main memory to the extended memory and from the extended memory to the main memory are always executed in response to the pinot check in the selection circuit 80. This is because, as will be explained later, a certain request reception is shared with a port for memory access, and a pin check is performed anew on that port, so there is no need for a pitch check when entering the request processing section for the first time. .

Reference numeral 140 denotes an extended storage access determination circuit that detects whether the output of the selection circuit 80 is main storage→extended storage transfer access or extended storage→main storage transfer access.

Then, the signal is used for main memory access and address generation unit 15
0 and extended storage access, output to the address generation unit 160. Naturally, the main memory access control section does not generate any access to the main memory when accessing the extended memory.

The unit of transfer between extended memory and main memory is one unit (IB).
(Company M and others do this) is numerically large, and in the second embodiment, the unit is 4 KB (1-!!-)).

It is also assumed that the request address includes an extended storage address and a main storage address.

In order to reduce the number of interfaces mentioned above, various other methods can be considered, such as setting one of the addresses in the memory access control device in advance and then issuing an access request together with the other address.

The main memory access and address generation unit 150 is the selection circuit 80
, the outputs of the extended storage access determination circuit 140 and the extended storage reply data storage buffer 180 are input.

The operation of this part is to input the request address of the main memory from the output of the III main memory to extended memory transfer selection circuit 80, and simultaneously generate a read request for the main memory.

4KB78B51 while updating the above address by 8B
Reads the device C buffer and outputs it to Renostav 0 twice.

At this time, there is a conflict with the request from device C, but this can be controlled by establishing priority logic between both requests.

(2) At the time of extended storage → main memory transfer: Receives the output of the extended storage reply data storage buffer 180 containing the reply data from the extended storage, and simultaneously generates a write request to the main memory.

4KB78B= while updating the main memory address in 8B increments
512 times, the device C buffer is read and output to Renostaf0 along with the reply data.

The extended memory access and address generation unit 160 is the selection circuit 8
0 and the output of the extended storage access determination circuit 140 and the main memory reply data storage buffer 7170 that stores reply data from the main memory.

The operation of this part is fil Main memory → extended memory transfer The extended storage address is input from the selection circuit 80.

The data to be transferred to the extended memory is a main memory reply data storage buffer 170 that stores reply data from the main memory.
Enter from. At the same time, a write request to extended storage is generated.

4KB/8B while updating extended memory address in 8B increments
=512 times While updating the address to the extended storage, the data is transferred together with the store data in the main memory reply data storage buffer 170.

(2) At the time of extended storage to main memory transfer, receiving the output of the extended storage reply data storage buffer 180 containing the reply data from the extended storage simultaneously generates a write request to the main memory. Selection circuit 80
4KB/8B = 512 times while updating the main memory address obtained from the output in 8B increments.

It is output to the device C buffer read register 70 together with the reply data.

As described above, in this embodiment, the interface with the expanded storage is performed in units of 8B, but various methods such as 2, for example, in units of 128B can be considered.

If the access is made in units of 128B, the access to the expanded storage will be 4KB7128B=32 times.

In addition, the main memory reply data storage buffer 170 and
The capacity of the extended storage reply data storage buffer 180 is
The transfer amount for one access to the extended storage is determined so as to be easily controlled.

A main memory reply data storage buffer 170 stores reply data from the main memory. What is stored in this buffer is the main memory access and address generation unit 1.
50 outputs a request to the device C buffer read register 70, and a reply to the request is returned, and no reply is returned to device C at this time.

The output is input to the extended storage access and address generation section 160, and this data becomes write data for the extended storage.

Reference numeral 180 denotes an extended storage reply data storage buffer for a read request to the extended storage. Stores reply data from extended storage.

The output is input to the main memory access and address generation section 150, and this data becomes data to be written to the main memory via the device C buffer read register.

Reference numeral 190 denotes expanded storage, which generally has a capacity several times or more larger than the main storage capacity.

In this embodiment, access is performed in units of 8B, but it is also possible to perform access in units of blocks (for example, 128B).

As for the operation, reply data is sent to the extended storage reply data storage buffer 18 in response to the extended storage access, read request, and write request from the address generation unit 160.
Returns 0 (of course, there is no reply data at the time of a write request).

To summarize the operation of transfer between main memory and extended memory (1)
In the case of main memory → extended memory transfer When the extended memory access from the request source is determined by the extended memory access determination circuit 140, the request code and address of the request are sent from the selection circuit 80 to the main memory access and address generation unit 15.
It is input to 0.

Next, accessing the main memory, the address generation unit 150 updates the request address while 4KB/8 B = 512
While updating the address, it is output to the device C buffer read register 70 along with the read request.

Request conflict with device C in the device C buffer read register is handled by priority logic or the like.

When the busy check is passed, the request is input to the main memory access control unit 90, and reading from the main memory is executed.

Next, when the reply data from the main memory is returned, it is stored in the main memory reply data storage buffer 170 without being set in the requester's request registers 1) 0, 120, and 130.

Next, the output of 170 main memory reply data storage buffers is output to the extended memory access and address generation section 160.
60 generates a write request to expanded storage. The output in the reply data storage buffer 170 is output to the extended storage together with the write request and address while updating the address.

Main memory data is transferred to extended memory.

2) When transferring from extended memory to main memory When the extended memory access from the request source is determined by the extended memory access determination circuit 140, the request code and address of the request are sent from the selection circuit 80 to the extended memory access and address generation unit. 160.

Next, the expanded storage access and address generation unit 160 reads 4KB/8B=512 times while updating the request address, and transfers the request address to the expanded storage 190 along with the request.
Output to.

Renolay data from extended storage 190 is input to extended storage reply data storage buffer 180 .

Next, the output of the extended memory reply data storage buffer 180 is input to the main memory access and address generation section 150.

The main memory access and address generation unit 150 generates a write request to the main memory.

At the same time, the request address (the write address to the main memory) is updated 4KB/8B=512 times and the reply data in the extended storage reply data storage buffer is output to the device C buffer reading and renostaff 0 along with the write request.

When the above request is passed to Pino Chie, Rini No Z.

It is sent to the main memory access control unit 90 via the selection circuit 80 and generates a write request to the main memory.

Transfer data from extended memory to main memory.

[Effects of the Invention] As explained above, the present invention simplifies control by sharing the processing part for the main memory with an existing port in transfer processing between the main memory and extended memory, and furthermore, the HW
This has the effect of reducing the amount.

μ bottom margin

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 10...Request reception port section, 20...Device A
Request reception buffer, 30...Device B request reception buffer, 40...Device C request reception buffer, 50 -Device A buffer read register 260-
...Device B buffer, 7A read register, 70...Device C buffer read register, 75...Request processing unit, 80...Selection circuit, 90...Main memory access control unit, 100...・・Main storage device, 1) 0 ・・Device A
Reply Reno Star, 120...Device B l)! Layrenostar, 130...Device C reply register, 14
0...Extended memory access determination circuit, 150...Main memory access, address generation unit, 160...Extended memory access, address generation! , 170... Main memory renolay data storage buffer, 180... Extended memory reply data storage buffer, 190... Extended memory.

Claims (1)

[Claims] (1) In a memory access control device that performs access to the main memory from multiple arithmetic processing units and input/output processing units, and data transfer between the extended storage device and the main storage device, request reception port means for inputting requests from the output processing device; selection means for performing a busy check on requests output from the request reception port means, further determining priority and selecting one request; and said selection means. main memory access means that inputs requests from the main memory, generates read and write requests to the main memory, and outputs them to the main memory along with the requested address and data; a reply means that receives reply data and returns it to the request source; a determination means that determines whether the output of the selection means is access to the main storage device or data transfer between the extended storage device and the main storage device; and the output of the determination means When it is determined that the request from the request source is a data transfer between the extended storage device and the main storage device, if the request is a data transfer from the main storage device to the expanded storage device, the output of the selection means indicates that the main memory a first generating means for generating a request address and a read request to the device; and outputting the request address and read request to the main storage device generated by the first generating means to the request reception port means. a first request reception port access means for processing a request from the first request reception port access means; a first reply data storage means for storing reply data from a main storage device in response to a request processing from the first request reception port access means; Sending means for sending the write address and write request to the extended storage device, when stored in the storage device, to the extended storage device together with stored data that is reply data from the main storage device; a second generating means for generating a request address and a read request to the expanded storage device from the output of the selecting means; and a second generating means for generating a request address and read request generated by the second generating means. expanded storage device access means for outputting a read request to the expanded storage device; second reply data storage means for storing reply data from the expanded storage device in response to the read request to the expanded storage device; A second request reception port that generates an address and a write request to the main storage device when the reply data is stored in the reply data storage means, and outputs the same to the request reception port means together with the reply data in the second reply data storage means. 1. An extended storage control method, comprising: an access means, wherein during transfer processing between an extended storage device and a main storage device, processing for accessing the main storage is performed in common with an existing request reception port.