JP2000066946A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve access efficiency by making data from bas masters writable in a memory in a page mode by providing a memory access sequencer having a specified function. SOLUTION: A memory access sequencer 5 has a function which compares addresses (c) to (f) from bus masters 2 and 3 and write data holding parts 10 and 11 with an address (g) at the time of the preceding memory access and preferentially selects a writeback request on the same page. The sequencer 5 selects the request of an address to be a page mode among the low addresses (c) and (d) of writeback requests (h) and (j) from the bas masters 2 and 3 and the row addresses (e) and (f) of the write data holding parts 10 and 11 and performs memory write to a memory element part 14. At the same time, it updates the low address (g) at the time of memory access held by an address latch 12. A flag 22 showing the existence of the address of the row address (g) is set in the address latch 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory controller for transferring data from a bus master to a memory, and more particularly to a memory controller for improving the data transfer speed.

[0002]

2. Description of the Related Art In recent computers, CPU, DM
Improving the data transfer speed from a bus master such as an A controller to a memory is indispensable for increasing the speed of computer operation. When a DRAM is used as a memory, it is usually necessary to divide and supply the two addresses of a row address and a column address. Conventionally, when there are a plurality of bus masters, there is only a means for writing the requests of each bus master to the memory in the same order, and the page mode that can be accessed at high speed cannot be used efficiently. However, if access to addresses with the same row address continues, data transfer can be performed by supplying only the column address. Therefore, access can be made in the page mode (high-speed page mode, hyper page mode), and faster data transfer. Becomes possible. As described above, by operating the access order of the DRAM and performing as many memory accesses as possible in the page mode,
Japanese Patent Application Laid-Open No. 6-103148 discloses a technique which is expected to improve the data transfer speed from the bus master to the memory.

In the technique described in this publication, a special write buffer is provided between a plurality of bus masters and a memory, and this write buffer is divided into a plurality of data holding units, an address latch, an address comparator, a data latch, and a write buffer control unit. , A bus arbitration unit. In particular, DRA
When there is access to M, the address is compared by an address comparator, and the row address of the data held in the data holding unit is compared with the row address at the time of the previous access, and the previous row address is compared. DRA with priority over the data holding unit that holds the same row address and the same data as
The writing (writing) to M is performed, thereby improving the efficiency of accessing the DRAM.

[0004]

In this prior art,
Since the write is performed by accessing the DRAM with priority given to the data having the same row address, it is effective in improving the access efficiency, but there is unwritten data in all the write data holding units that does not enter the page mode. in case of,
Even if a new write request from the bus master can enter the page mode, the memory cannot be accessed unless it is once held in the write data holding unit, and this processing is an obstacle to improving access efficiency. There is a problem. Further, in the above-described conventional technology, it is advantageous that the number of write data holding units is large in terms of access efficiency, but the write data holding unit needs to keep holding data for a long time. When a large number of write data holding units are provided, there is also a problem that a circuit scale for actually realizing the write data holding unit becomes large.

An object of the present invention is to regard the write data holding unit as a place where data is temporarily latched, and even if the write data holding unit is filled with unwritten data.
It is an object of the present invention to provide a memory controller capable of writing data from a bus master to a memory in a page mode to improve access efficiency and reducing the number of write data holding units.

[0006]

According to the present invention, a write-back request from the bus master is inserted between a memory element and a plurality of bus masters for issuing a data write-back request to the memory element. A memory controller that manages a data write operation to the memory element unit based on the memory controller, wherein the memory controller includes at least one write data holding unit that holds data from the bus master, and an access to the memory element unit. An address latch for storing the previous address, an address stored in the address latch, an address for which a write-back request is issued from the bus master, and an address of the write data holding unit, and a match with the address of the address latch. Priority to the bus master or write data holding unit of the address Characterized in that it comprises a memory access sequencer to perform the write operation. The memory element unit performs data access to an address set by a row address and a column address, the row latch can store the row address, and the memory access sequencer stores a row of the address latch. The sequence is set such that the bus master or the write data holding unit having the same address is accessed with priority.

According to the present invention, each address of the bus master having a write-back request and the address of the write data holding unit is compared with the address of the address latch, and the bus master or ride data holding unit which matches the address of the address latch is preferentially written. Perform the action. Therefore, a write operation in a direct page mode can be performed on the bus master, and access efficiency can be improved. Further, when the write data holding unit is prioritized, the data of the bus master is immediately held in the write data holding unit, so that the write data holding unit can be effectively used and the number of write data holding units can be reduced.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram of a main part of a memory controller according to the present invention. Two bus masters 2,
The memory controller 1 having a circuit for controlling write-back according to the present invention is interposed between the memory controller 3 and the memory element unit 14 for storing data. Here, in the present embodiment, the bus masters 2 and 3 are assumed to be either a CPU or a DMA controller, and the memory element section 14 is assumed to be a single DRAM. Each of the bus masters 2 and 3 outputs a write-back request signal h and j to the memory access sequencer 5 in accordance with the address and data output, receives the acknowledge signals i and k, and determines that one cycle is completed. Move on to processing. Addresses and data from the bus masters 2 and 3 are respectively applied to address selectors 6 and
8 and data selectors 7 and 9, output to an address bus a and a data bus b under the control of the memory access sequencer 5, and output an address latch 12 and a data latch 13.
It is determined whether to perform the memory write directly to the memory element unit 14 or to save the data to the write data holding units 10 and 11. In the write data holding units 10 and 11,
The presence or absence of unwritten data is stored in flags 20 and 21.

The memory access sequencer 5 includes the bus masters 2 and 3 and the write data holding units 10 and 11.
Has a function of comparing the addresses c, d, e, and f with the address g at the time of the previous memory access, and preferentially selecting a write-back request for the same page. In response to the selected write-back request, the write address is output to the address bus a and the write data is output to the data bus b. The write address and the write data are output from the address latch 12 and the data latch 13 to the memory element unit 14. And in the memory element section 14 according to a control signal from the memory access sequencer 5. At the same time, the row address g at the time of memory access held in the address latch 12 is updated. This address g is also updated at the time of memory reading. If there is a memory access even once, the row address g is latched, and the flag 22 indicating whether or not the row address g is present is set in the address latch 12.

Next, the operation of the circuit of FIG. 1 will be described. Row addresses c and d of write back requests h and j from bus masters 2 and 3 and write data holding units 10 and 11
If there is a request for an address to be set to the page mode among the row addresses e and f, the request is selected and a memory write is performed. Here, when there is a request at the same time, the write data holding unit 10 and the write data holding unit 1
1, the bus master 2 and the bus master 3 are set in this order. If all four requests are on pages, the row address e of the write data holding unit 10 is selected. If the row addresses of all requests are not on the same page as the row address g, the write data holding unit 1
0, a write data holding unit 11, a bus master 2, and a bus master 3 are sequentially selected to perform a memory write. Also, there is no request from the bus masters 2 and 3 and the write data holding unit 1
Even when data remains at 0 and 11, a request for the same page as the row address g, a request for the write data holding unit 10 and a request for the write data holding unit 11 are selected in this order, and memory write is performed. It should be noted that the write data holding unit 10 or 11 that has performed the memory write is provided with the flag 20 or the flag 2
Reset 1

Hereinafter, a specific operation will be described. If the flag 22 of the address latch 12 is not set, the write-back request h from the bus master 2 is accepted, the memory is directly written, an acknowledge signal i is output, and the next request can be accepted. At the same time, if there is a write back request j from the bus master 3, the address and data are saved in the write data holding unit 11, the flag 21 is set, and the write back request j saved in the write data holding unit 11 is sent to the write data holding unit 11. On the other hand, it outputs an acknowledgment signal k to enable the reception of the next request. When only the write-back request j from the bus master 3 is received, the write-back request j from the bus master 3 is accepted, the memory is directly written, the acknowledge signal k is output, and the next request can be accepted. In all cases, the row address latched at the time of performing the memory write is stored as the row address g, and the flag 22 is set.

On the other hand, in response to write-back requests h and j from the bus masters 2 and 3, the write data holding units 10 and 11
If the flags 20 and 21 are not set in the row addresses c and d of the requests h and j from the bus masters 2 and 3,
Is compared with the row address g at the time of the previous memory access, and a request for the same page is preferentially selected. When the bus master 2 is selected with priority, the write-back request h of the bus master 2 is selected, and the memory write is performed directly. In response to the request j of the bus master 3 at the same time, the address and data are saved in the write data holding unit 11 and the flag 21 is set. In response to a write-back request h for directly performing a memory write and a write-back request j saved to the write data holding unit 11, an acknowledge signal i,
k is output so that the next request can be accepted. Also,
When the bus master 3 is selected with priority, the write-back request j of the bus master 3 is selected and the memory write is performed directly. In response to the request h of the bus master 2 at the same time, the address and data are saved in the write data holding unit 10 and the flag 20 is set. An acknowledge signal k, i is output in response to a write-back request j in which a memory write has been directly performed and a write-back request h saved in the write data holding unit 10, so that the next request can be accepted.

The flag 2 of the write data holding unit 10
When only 0 is set, the row addresses c and d of the requests h and j from the bus masters 2 and 3 and the row address e of the write data holding unit 10 are compared with the row address g at the time of the previous memory access. Then, a request for the same page is preferentially selected. When the bus master 2 is selected with priority, the write-back request h of the bus master 2 is selected, and the memory write is performed directly. In response to the request j of the bus master 3 at the same time, the address and data are saved in the write data holding unit 11 and the flag 21 is set. In response to a write-back request h for which a direct memory write has been performed and a write-back request j saved to the write data holding unit 11, acknowledge signals i and k are output, and the next request can be accepted.

On the other hand, when the bus master 3 is selected preferentially, the request j of the bus master 3 is selected and the memory write is performed directly. At this time, the request h of the bus master 2 is not accepted, and the write data holding unit 10 is not changed. An acknowledgment signal k is output only for a write-back request j for which a direct memory write has been performed, and the next request can be accepted.

Alternatively, when the write data holding unit 10 is selected with priority, the address and data of the write data holding unit 10 are output to the address bus a and the data bus b, and the memory write is performed. Simultaneous bus master 2,
For the write-back requests h and j of No. 3, the address and data are saved in the write data holding units 10 and 11, and flags 20 and 21 are set. Write data holding unit 10, 1
In response to the write-back requests h and j saved in step 1, the acknowledgment signals i and k are output, and the next request can be accepted.

Next, the flag 2 of the write data holding unit 11
When only 1 is set, the row addresses c and d of the requests h and j from the bus masters 2 and 3 and the row address f of the write data holding unit 11 are compared with the row address g at the time of the previous memory access. Then, a request for the same page is preferentially selected. When the bus master 2 is selected with priority, the request h of the bus master 2 is selected and the memory write is performed directly. At this time, the request j of the bus master 3 is not accepted, and the write data holding unit 11 is not changed. An acknowledgment signal i is output only for a write-back request h for which a direct memory write has been performed, and the next request can be accepted.

When the bus master 3 is selected with priority, the write-back request j of the bus master 3 is selected, and
Perform memory write directly. In response to the request h of the bus master 2 at the same time, the address and data are saved in the write data holding unit 10 and the flag 20 is set. A write-back request j for directly performing a memory write and a write-back request h saved to the write data holding unit 10
Acknowledgment signals k and i are output in response to the next request.

On the other hand, when the write data holding unit 11 is selected with priority, the address and data of the write data holding unit 11 are output to the address bus a and the data bus b, and the memory write is performed. With respect to the write-back requests h and j of the bus masters 2 and 3 at the same time, the addresses and data are saved in the write data holding units 10 and 11, and the flags 20 and
Set 21. In response to the write-back requests h and j saved in the write data holding units 10 and 11, acknowledge signals i and k are output, and the next request can be accepted.

When the flags 20 and 21 of the write data holding units 10 and 11 are both set, the row addresses c and d of the requests h and j from the bus masters 2 and 3 and the write data holding units 10 and 11 The row addresses e and f are compared with the row address g at the time of the previous memory access, and a request for the same page is preferentially selected. When the bus master 2 is selected with priority, the request h of the bus master 2 is selected and the memory write is performed directly. At this time, the request j of the bus master 3 is not accepted and the write data holding unit 1
0 and 11 are not changed. An acknowledgment signal i is output only for a write-back request h for which a direct memory write has been performed, and the next request can be accepted.

When the bus master 3 is selected with priority, the request j of the bus master 3 is selected and the memory write is performed directly. At this time, the request h of the bus master 2 is not accepted, and the write data holding units 10 and 11 are not changed. An acknowledge signal k is output only for a write-back request h for which a direct memory write has been performed, and the next request can be accepted.

On the other hand, when the write data holding unit 10 is selected with priority, the address and data of the write data holding unit 10 are output to the address bus a and the data bus b, and the memory write is performed. Bus master 2 write-back request h
Then, the address and data are saved in the write data holding unit 10 and the flag 20 is set. At this time, the request j of the bus master 3 is not accepted, and the write data holding unit 11 is not changed. In response to the write-back request h saved in the write data holding unit 10, an acknowledgment signal i is output, so that the next request can be accepted. Write data holding unit 1
When 1 is selected, the address and data of the write data holding unit 11 are output to the address bus a and the data bus b, and the memory write is performed. Further, in response to the write back request j of the bus master 3, the address and data are saved in the write data holding unit 11, and the flag 21 is set. At this time, the request h of the bus master 2 is not accepted, and the write data holding unit 10 is not changed. In response to the write back request j saved in the write data holding unit 11, an acknowledge signal k
Is output, and the next request can be accepted.

For example, as shown in FIG. 2A, when the bus masters 2 and 3 are respectively requested as shown in FIG.
Regarding the memory access to this request, the difference between the operation of the conventional example and the operation of the present embodiment will be described. Since the priority bus master (processor) in the conventional example is undefined,
The address and data held in the write data holding unit are
It is assumed that the bus master 2 is preferentially held. In the conventional example, since the memory access is performed after holding the data of the priority bus master 2 in the data holding unit, even if there is data that can be accessed in the page mode in the data 3, the page priority is given to this data. Mode access cannot be performed. For this reason, the limit is that the write-back sequence is changed as shown in FIG. 2B and the number of page mode accesses is increased from three to five. On the other hand, in the present embodiment, since the priority between the bus masters 2 and 3 and the data holding units 10 and 11 is checked, the page mode access to the data of the bus master 3 can be performed preferentially. By changing the write-back sequence as shown in (c), it is possible to increase the number of page mode accesses to eight times, thereby realizing further higher data transfer speed. As described above, in the present embodiment, the number of write data holding units can be reduced by half while the number of page mode accesses can be increased, and the efficiency of access can be improved.

[0023]

As described above, according to the present invention, as a configuration of a memory controller that manages a data write operation to a memory element unit based on a write-back request from a bus master, one or more memories that hold data from the bus master are provided. A write data holding unit, an address latch for storing a previous address accessed to the memory element unit, an address stored in the address latch, an address for which a write-back request has been issued from the bus master, and an address of the write data holding unit. A memory access sequencer is provided for comparing the address with the address of the address latch and executing a write operation preferentially with respect to the bus master or the write data holding unit having an address matching the address of the address latch. Access in direct page mode Enabling scan and then, thereby improving the access efficiency. When the write data holding unit is prioritized, data can be held in the write data holding unit, the write data holding unit can be effectively used, the number of write data holding units can be reduced, and the circuit size can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an embodiment of a memory controller of the present invention.

FIG. 2 is a diagram showing an access sequence in the present invention in comparison with a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory controller 2, 3 Bus master 5 Memory sequencer 6, 7 Address selector 8, 9, Data selector 10, 11, Write data holding part 12 Address latch 13 Data latch 14, Memory element part 20, 21, 22, Flag

Claims (5)

[Claims] 1. A memory device, comprising: a plurality of bus masters that issue a data write-back request to the memory device; and a plurality of bus masters that issue a data write-back request to the memory device based on a write-back request from the bus master. A memory controller for managing a data write operation of the memory device, the memory controller comprising: at least one write data holding unit for holding data from the bus master; and an address for storing a previous address accessed to the memory element unit. A latch, an address stored in the address latch, an address for which a write-back request is received from the bus master, and an address of the write data holding unit, and a bus master or write data holding of an address that matches the address of the address latch. Memo that gives priority to the write operation A memory controller comprising a reaccess sequencer. 2. The memory element section executes data access to an address set by a row address and a column address, the address latch can store the row address, and the memory access sequencer includes: 2. The memory controller according to claim 1, wherein a sequence is set such that the bus master or the write data holding unit having a matching row address of the address latch is accessed with priority. 3. When the memory access sequencer gives priority to the bus master, the memory access sequencer directly writes data of the bus master to the memory element section,
When giving priority to the write data holding unit, the data of the write data holding unit is directly written to the memory element unit, and the write data holding unit that has performed the write operation holds data from the bus master. 3. The memory controller according to claim 1, wherein the sequence is set to be performed. 4. The memory according to claim 1, wherein a plurality of said write data holding units are provided, and an address selector and a data selector which distribute data of said plurality of bus masters to said plurality of write data holding units. controller. 5. A method according to claim 1, wherein the address latch and the write data holding unit are respectively provided with a flag indicating that an address and data are held, and the memory access sequencer executes the sequence operation based on the flag. Item 5. The memory controller according to any one of Items 1 to 4.