JPH0561769A - Memory access method - Google Patents

Abstract

PURPOSE:To accelerate data transfer from a cache memory to a main memory by allocating the row address of the main memory in the index range of the cache memory and obtaining continuity in the index. CONSTITUTION:Among addresses outputted from a processor 1, the high-order address is allocated to the tag address of an external cache memory 3 and the column address of a main memory 4, and the low-order address is allocated to the index of the external cache memory 3 and the row address of the main memory 4. Therefore, concerning the external cache memory 3, the index as the low-order address is made continuous, and the tag address as the high-order address is made discontinuous. In this case, after the index is generated, a row address strobe signal can be asserted without waiting for the generation of the tag address and the start of access to the main memory 4 can be accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention writes the contents of a cache memory provided in order to reduce the time required for memory access by a processor to a main memory and also partially writes the contents of the main memory to the cache memory. The present invention relates to a memory access method for reading data in a memory.

[0002]

2. Description of the Related Art Conventionally, it has been generalized to provide a cache memory in order to reduce the time required for memory access by a processor. In such a system, the main memory is composed of a DRAM (dynamic random access memory), and the cache memory is composed of a memory which can be accessed at a higher speed than the DRAM so that the memory access time required by the processor is reduced. A configuration is adopted that shortens the cost and suppresses an increase in the cost of the entire memory.

Of the addresses for memory access, the upper address is the tag of the cache memory.
Addresses and main memory row addresses are assigned, and lower addresses are assigned to cache memory indexes and main memory column addresses. Therefore, data can be written from the cache memory to the main memory and data can be read from the main memory to the cache memory by appropriately setting the upper address and the lower address. By accessing the cache memory instead of accessing the main memory when the corresponding data exists, the time required for memory access by the processor can be greatly shortened.

[0004]

Most of the conventional memory access methods described above are single-processor systems. In this system, it is sufficient if the time required for memory access by the processor can be shortened. Write data from memory to main memory and cache from main memory
There was almost no demand that the reading of data from the memory should be speeded up. However, in a multi-processor system, depending on the application program, data may have to be transferred from the cache memory to the main memory at once, but due to the nature of the cache memory, the tag address ( DRA because there is no continuity in the upper address)
The fast access mode cannot be adopted in the write access to the main memory configured by M, and the time required for the above data transfer becomes remarkably long, and other processors are forced to wait during this time. There is an inconvenience that Further, since it is not possible to perform pipeline access to the main memory, the time required for the data transfer becomes extremely long, and there is a disadvantage that another processor is also put in a wait state.

Further, an index is given to the cache memory so that the access to the main memory is started after the tag address is output (a row address strobe signal (hereinafter abbreviated as RAS) and a column address).・ Strobe signal (hereinafter referred to as CAS
Will be asserted) (see FIG. 5) (see FIG. 5), the time required until the access to the main memory is started becomes longer, and as a result, the time required for memory access is further increased. There is an inconvenience that it becomes long and similarly causes other processors to wait.

In the above description, only the case of application to a multi-processor system has been described.
Also in the processor system, there is a disadvantage that the processing capacity of the entire system is lowered due to the long wait time of the processor.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a memory access time required for transferring data from a cache memory to a main memory in a memory system having a cache memory. It is an object of the present invention to provide a new memory access method capable of significantly shortening the memory size.

[0008]

To achieve the above object, a memory access method according to claim 1 allocates a row address of a main memory within a range of an index of a cache memory and a column address. cache·
This is a method of assigning to an index that has not been used for the tag address and row address of the memory.

[0009]

According to the memory access method of the first aspect, the index of the cache memory that can be accessed faster than the main memory has continuity. Since this index is assigned to the low address of the main memory, it is possible to preempt the address, and pipeline access to the main memory can be achieved. -High-speed transfer can be achieved when transferring to memory, and the time required for memory access can be greatly shortened.

Further, in a memory system having a plurality of sets of cache memory and a main memory composed of a DRAM, a plurality of tag addresses exist for a certain index. Since the index is assigned to the low address, high-speed access to the DRAM is possible when data is transferred from the cache memory to the main memory.
A mode (for example, high speed page mode) can be adopted, high speed transfer can be achieved when the contents of the cache memory are transferred to the main memory at once, and the memory access time can be greatly shortened.

Further, when the cache memory is accessed, the tag address is given next to the address with respect to the address, and when the main memory is accessed, the row address is followed by the column address with respect to the address. The address is given. In the present invention, the cache
Since the lower address given to the memory is the index and the low address of the main memory is assigned as the lower address, the order of the addresses when accessing both memories is the same, and high-speed memory access is possible. It is possible to easily achieve high efficiency and secure timing margin, and it is possible to greatly reduce the time required for memory access.

[0012]

Embodiments will now be described in detail with reference to the accompanying drawings showing embodiments. FIG. 1 is a block diagram showing an embodiment of a memory access system in which the memory access method of the present invention is implemented. A main unit including a processor 1, a memory controller 2, an external cache memory 3 and a DRAM. -Has memory 4. Of the addresses output from the processor 1, the upper address is assigned to the tag address of the external cache memory 3 and the column address of the main memory 4, and the lower address is assigned to the index of the external cache memory 3 and It is assigned to the low address of the main memory 4. However, more accurately, within the range of the index of the external cache memory 3, the main memory 4
Row address is assigned to the lower address.

By allocating the upper address and the lower address as described above, the external cache memory 3 becomes
The index as the lower address has continuity, and the tag address as the upper address becomes discontinuous. The memory access operation according to the above memory access method will be described with reference to the timing chart shown in FIG.

In the above memory access system, since the index (see FIG. 2A) for the external cache memory is assigned to the lower address, the tag address is not generated after the index is generated. RAS can be asserted without waiting (Fig. 2
(See (B) and (C)). Since CAS can be asserted after the tag address is generated and access to the main memory 4 can be started, RAS and CA are generated after both the index and the tag address are generated.
Compared with the conventional method that asserts S in this order,
It is possible to speed up the start of access to the memory 4, speed up memory access, and secure a timing margin.

[0015]

Second Embodiment FIG. 3 is a diagram schematically illustrating a memory access system having an external cache memory 3 having an N-way set cache configuration.
N tags Tag1, Tag for one index
2, ... I have TagN.

In this case, since each tag includes tag information, state and data, and instruction, the tag address has no continuity. Therefore, in the conventional method that uses the tag address as the lower address, the cache address corresponding to the index value is
When writing data to the main memory 4, RAS and CAS must be asserted for each tag, and the time required for writing cache data becomes extremely long as a whole.

However, in this embodiment, since the index value common to the N tags is assigned to the row address, it is only necessary to assert RAS once and then CAS CAS N times. Since the known fast page mode can be applied to the access to the DRAM, the time required for writing the cache data can be remarkably shortened as a whole.

[0018]

[Third Embodiment] FIG. 4 is a block diagram showing another embodiment of the memory access system for implementing the memory access method of the present invention, in which the main memory 4 is divided into two main memories 4a and 4b. Has been done. Then, two kinds of addresses output from the address generator 5 are supplied to the external cache memory 3 as an index through the selector 6, and at the same time, an address terminal of the corresponding main memory is supplied through the corresponding address bus. As a low address. Further, the tag address output from the external cache memory 3 is supplied to the address terminals of the main memories 4a and 4b as a column address, and the data output from the external cache memory 3 is supplied to the data terminal. ing.
Further, RAS is provided in each of the main memories 4a and 4b.
Is to be asserted. The two types of addresses are preferably even addresses and odd addresses, for example.

The operation of this embodiment is as follows. For example, a0 and a0 + 1 are output as addresses for calling the tag data from the external cache memory 3. In this case, the selector 6 first selects the address a0. Then, after the address a0 is determined, RAS is asserted for the main memory 4a, and when the tag address and data output from the external cache memory 3 are determined, the write access to the main memory 4a is performed. While the main memory 4a is being accessed for writing, the main memory 4a
Assert RAS for b.

After completion of the write access to the main memory 4a, the selector 6 is switched to select the address a0 + 1, and the address generator 5 generates the next address a0 + 2. And the address a0
When +1 is determined and the tag address and data output from the external cache memory 3 are determined, write access to the main memory 4b is performed. Also,
The RAS for the main memory 4a is asserted while the write access for the main memory 4b is being performed.

By repeating the above operation, the data writing from the external cache memory 3 to the main memories 4a and 4b is performed in a pipeline manner, and the time required for writing the cache data can be remarkably shortened. The above embodiments have been described only with respect to the case of transferring data from the external cache memory 3 to the main memories 4, 4a and 4b.
Also in the case of transferring data from a and 4b to the external cache memory 3, the same memory access speed as the conventional method can be achieved as follows.

That is, conventionally, a tag address is assigned to a row address, and a bit and an index indicating a word address when one line of the external cache memory 3 is set to a plurality of words are assigned as column addresses. The external cache memory 3 is accessed based on the address. Therefore, high-speed access can be achieved by using the tag address as a low address in a high-speed page mode or the like. On the other hand, in the present invention, only the index is assigned as the row address, the tag address and the bit indicating the word address are assigned as the column address, and the external cache memory 3 is accessed based on both addresses. To do. Therefore, the index
High-speed access can be achieved by using the high-speed page mode as an address.

[0023]

As described above, according to the first aspect of the present invention, the order of addresses when accessing both memories is the same, and it is possible to easily achieve high-speed memory access and secure timing margin. Memory access time can be greatly shortened, pipeline access to main memory can be achieved, and DRAM high-speed access mode can be used when data is transferred from cache memory to main memory. Can be adopted,
High-speed transfer can be achieved in the case of transferring the contents of the cache memory to the main memory at one time, and the memory access required time can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory access system in which a memory access method of the present invention is implemented.

FIG. 2 is a timing chart illustrating a memory access operation according to the memory access method of the present invention.

FIG. 3 is a memory access with external cache memory having an N-way set cache configuration.
It is a figure which illustrates a system roughly.

FIG. 4 is a block diagram showing another embodiment of a memory access system for implementing the memory access method of the present invention.

FIG. 5 is a timing chart illustrating a memory access operation according to a conventional memory access method.

[Explanation of symbols]

 1 processor 3 external cache memory 4, 4a, 4b main memory

Claims (1)

[Claims] 1. Main memory (4) (4a) (4b)
A part of the contents of the above is read into the cache memory (3), and when the corresponding data exists in the cache memory (3), the processor (1) accesses the cache memory (3), If necessary, the contents of the cache memory (3) are transferred to the main memory (4) (4
a) (4b) and the main memory (4)
In the memory access method of reading the contents of the corresponding portions of (4a) and (4b) into the cache memory (3), the row address of the main memory (4) (4a) (4b) is set to the cache memory (3). Memory access method, wherein the column address is allocated to the index not used in the tag address and row address of the cache memory (3).